Features. Description. Table 1: Device summary Order code Marking Package Packaging STW38N65M5-4 38N65M5 TO247-4 Tube

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1 N-channel 650 V, Ω typ., 30 A MDmesh M5 Power MOSFET in a TO247-4 package Datasheet - preliminary data Features Order code V T Jmax R DS(on) max I D STW38N65M V Ω 30 A Extremely low R DS(on) Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Figure 1: Internal schematic diagram Drain(1) Applications High efficiency switching applications: Servers PV inverters Telecom infrastructure Multi kw battery chargers Gate(4) Driver source(3) Power source(2) ND1PS2DS3G4 Description This device is an N-channel Power MOSFET based on the MDmesh M5 innovative vertical process technology combined with the wellknown PowerMESH horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. Table 1: Device summary Order code Marking Package Packaging STW38N65M5-4 38N65M5 TO247-4 Tube April 2016 DocID Rev 1 1/13 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

2 Contents STW38N65M5-4 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curve) Test circuits Package information TO247-4 package information Revision history /13 DocID Rev 1

3 Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit V GS Gate- source voltage ±25 V I D Drain current (continuous) at T C = 25 C 30 A I D Drain current (continuous) at T C = 100 C 19 A I DM (1) Drain current (pulsed) 120 A P TOT Total dissipation at T C = 25 C 190 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns T stg T j Storage temperature range Operating junction temperature range Notes: (1) Pulse width limited by safe operating area (2) ISD 30 A, di/dt = 400 A/µs, V DS(peak) < V (BR)DSS, V DD = 400 V (3) VDS 520 V - 55 to 150 C Table 3: Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max 0.66 C/W R thj-amb Thermal resistance junction-ambient max 50 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetitive or not repetitive (pulse width limited by T jmax ) Single pulse avalanche energy (starting T J = 25 C, I D = I AR, V DD = 50 V) 8 C/W 660 mj DocID Rev 1 3/13

4 Electrical characteristics STW38N65M5-4 2 Electrical characteristics (T C = 25 C unless otherwise specified) Table 5: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS I GSS Drain-source breakdown voltage Zero gate voltage drain current Gate-body leakage current I D = 1 ma, V GS = V V DS = 650 V 1 µa V GS = 0, V DS = 650 V, (1) 100 µa T C=125 C V DS = 0, V GS = ± 25 V ±100 na V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa V R DS(on) Static drain-source on- resistance Notes: (1) Defined by design, not subject to production test V GS = 10 V, I D = 15 A Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS = 100 V, f = 1 MHz, pf C rss Reverse transfer V GS = 0 capacitance pf Equivalent capacitance time related V GS = 0, V DS = 0 to 520 V pf Equivalent capacitance energy related pf R G Intrinsic gate resistance f = 1 MHz, I D=0 A Ω Q g Total gate charge V DD = 520 V, I D = 15 A, nc Q gs Gate-source charge V GS = 10 V (see Figure 16: nc Q gd Gate-drain charge "Gate charge test circuit") nc C o(tr) (1) C o(er) (2) Notes: (1) Co(tr) is a constant capacitance value that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. (2) Co(er) is a constant capacitance value that gives the same stored energy as Coss while V DS is rising from 0 to 80% V DSS. 4/13 DocID Rev 1

5 Electrical characteristics Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(v) Voltage delay time V DD = 400 V, I D = 20 A, ns t r(v) Voltage rise time R G = 4.7 Ω, V GS = 10 V ns (see Figure 17: " Test circuit for t f(i) Current fall time inductive load switching and diode ns t c(off) Crossing time recovery times" and Figure 20: "Switching time waveform") ns Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 30 A Source-drain current (pulsed) A I SDM (1) V SD (2) Forward on voltage I SD = 30 A, V GS = V t rr Reverse recovery time I SD = 30 A, ns Q rr I RRM Reverse recovery charge Reverse recovery current di/dt = 100 A/µs V DD = 100 V (see Figure 20: "Switching time waveform") t rr Reverse recovery time Reverse recovery charge Reverse recovery current I SD = 30 A, di/dt = 100 A/µs V DD = 100 V, T j = 150 C (see Figure 20: "Switching time waveform") Q rr I RRM Notes: (1) Pulse width limited by safe operating area (2) Pulsed: pulse duration = 300 µs, duty cycle 1.5% µc - 35 A ns µc - 40 A DocID Rev 1 5/13

6 Electrical characteristics 2.2 Electrical characteristics (curve) Figure 2: Safe operating area AM12636v1 ID (A) STW38N65M5-4 Figure 3: Thermal impedance Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Sinlge pulse VDS(V) 10µs 100µs 1ms 10ms Figure 4: Output characteristics ID (A) VGS = 10 V 80 VGS = 8 V AM12637v1 ID (A) 80 Figure 5: Tranfer characteristics AM12638v1 60 VGS = 7 V 60 VDS= 25V VGS = 6 V VDS(V) VGS(V) Figure 6: Gate charge vs gate-source voltage AM12639v1 VGS VDS (V) VDD=520V (V) ID=15A VDS 400 Figure 7: Static drain-source on-resistance Qg(nC) 6/13 DocID Rev 1

7 Figure 8: Capacitance variations C (pf) AM12641v1 Electrical characteristics Figure 9: Output capacitance stored energy AM12642v1 Eoss (µj) Ciss Coss 10 Crss VDS(V) VDS(V) Figure 10: Normalized gate threshold voltage vs temperature VGS(th) AM05459v1 (norm) 1.10 ID = 250 µa 1.00 Figure 11: Normalized on-resistance vs temperature RDS(on) (norm) VGS = 10 V ID = 15 A AM05460v TJ( C) TJ( C) Figure 12: Source-drain diode forward characteristics VSD AM05461v1 (V) TJ=-50 C TJ=25 C 0.6 TJ=150 C ISD(A) Figure 13: Normalized V (BR)DSS vs temperature V(BR)DSS AM10399v1 (norm) 1.08 ID = 1mA TJ( C) DocID Rev 1 7/13

8 Electrical characteristics Figure 14: Switching energy vs gate resistance E (µj) ID=20A VDD=400V Eon AM18024v1 STW38N65M Eoff RG(Ω) E on including reverse recovery of a SiC diode. 8/13 DocID Rev 1

9 Test circuits 3 Test circuits Figure 15: Switching times test circuit for resistive load Figure 16: Gate charge test circuit VDD VGS VD RG RL + D.U.T µf 3.3 µf VDD Vi VGS µf 12V IG=CONST 2.7kΩ 47kΩ 100nF 100Ω 1kΩ D.U.T. VG PW 47kΩ GND1 (driver signal) GND2 (power) AM15855v1 PW 1kΩ GND1 GND2 AM15856v1 Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit 25Ω G A D D.U.T. S B A FAST DIODE B A B L=100µH D µf + µf VDD VD L µf 3.3 µf VDD G ID RG S D.U.T. Vi D.U.T. GND1 GND2 AM15857v1 Pw GND1 GND2 AM15858v1 Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform Id Concept waveform for Indu ctive Load Turn-off 90%Vds 90%Id Tdelay -off Vgs 90%Vgs on Vgs(I(t )) 10%Vds 10%Id Vds Trise Tfall Tcross -over AM05540v2_for_M5 DocID Rev 1 9/13

10 Package information STW38N65M5-4 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 4.1 TO247-4 package information Figure 21: TO247-4 package outline 10/13 DocID Rev 1

11 Package information Table 9: TO247-4 mechanical data mm. Dim. Min. Typ. Max. A A A b b b c c D D D D E E E E e e L P P P Q S 6.15 T U DocID Rev 1 11/13

12 Revision history STW38N65M5-4 5 Revision history Table 10: Document revision history Date Revision Changes 20-Apr Initial release. 12/13 DocID Rev 1

13 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DocID Rev 1 13/13

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