STB100N10F7, STD100N10F7, STF100N10F7 STI100N10F7, STP100N10F7 Datasheet

Transcription

1 STB100N10F7, STD100N10F7, STF100N10F7 STI100N10F7, STP100N10F7 Datasheet N-channel 100 V, 6.8 mω typ., 80 A STripFET F7 Power MOSFETs in D 2 PAK, DPAK, TO-220FP, I 2 PAK and TO-220 packages TAB TAB Features 1 3 D 2 PAK DPAK Order codes V DS R DS(on) max. I D Package STB100N10F7 80 A D 2 PAK TAB TAB STD100N10F7 80 A DPAK STF100N10F7 100 V 8.0 mω 45 A TO-220FP TO-220FP I 2 PAK TO STI100N10F7 80 A I 2 PAK STP100N10F7 80 A TO-220 D(2, TAB) Among the lowest R DS(on) on the market Excellent FoM (figure of merit) Low C rss /C iss ratio for EMI immunity High avalanche ruggedness G(1) S(3) AM01475v1_noZen Product status links Applications Switching applications Description These N-channel Power MOSFETs utilize STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. STB100N10F7 STD100N10F7 STF100N10F7 STI100N10F7 STP100N10F7 DS Rev 5 - June 2018 For further information contact your local STMicroelectronics sales office.

2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Value Symbol Parameter DPAK TO-220FP TO-220 D 2 PAK Unit I 2 PAK V DS Drain-source voltage 100 V V GS Gate-source voltage ±20 V I Drain current (continuous) at T C = 25 C (1) 80 A D Drain current (continuous) at T C = 100 C (1) 70 A I DM (2) Drain current (pulsed) A P TOT (1) Total dissipation at T C = 25 C W V ISO Insulation withstand voltage (RMS) from all three leads to external heatsink (t = 1 s, T C = 25 C) 2.5 kv T J Operating junction temperature C -55 to 175 T stg Storage temperature range C 1. This value is limited by package. 2. Pulse width is limited by safe operating area. Table 2. Thermal resistance Value Symbol Parameter D 2 PAK DPAK TO-220FP TO-220 I 2 PAK Unit R thj-case Thermal resistance junction-case C/W R thj-amb Thermal resistance junction-ambient 62.5 C/W R (1) thj-pcb Thermal resistance junction-pcb C/W 1. When mounted on an 1-inch 2 FR-4 board, 2oz CU, t < 10 s. Table 3. Avalanche characteristics Symbol Parameter Value Unit E AS Single pulse avalanche energy (T J = 25 C, L = 3.5 mh, I AS = 15 A, V DD = 50 V, V GS = 10 V) 400 mj DS Rev 5 page 2/28

3 Electrical characteristics 2 Electrical characteristics (T CASE = 25 C unless otherwise specified) Table 4. On-/off-states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS Drain-source breakdown voltage I D = 250 μa, V GS = 0 V 100 V V DS = 100 V, V GS = 0 V 1 µa I DSS Zero gate voltage drain current V DS = 100 V, V GS = 0 V, T C = 125 C (1) 100 µa I GSS Gate-body leakage current V GS = 20 V, V DS = 0 V 100 na V GS(th) Gate threshold voltage V DS = V GS, I D = 250 μa V For D 2 PAK, DPAK, I 2 PAK and TO-220: R DS(on) Static drain-source on-resistance V GS = 10 V, I D = 40 A For TO-220FP: mω V GS = 10 V, I D = 22.5 A 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS = 50 V, f = 1 MHz, V GS = 0 V pf C rss Reverse transfer capacitance pf Q g Total gate charge V DD = 50 V, I D = 80 A, nc Q gs Gate-source charge V GS = 0 to 10 V nc Q gd Gate-drain charge (see Figure 17. Test circuit for gate charge behavior) nc Table 6. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 50 V, I D = 40 A, ns t r Rise time R G = 4.7 Ω, V GS = 10 V ns t d(off) Turn-off delay time (see Figure 16. Test circuit for resistive load switching times and ns t f Fall time Figure 21. Switching time waveform) ns DS Rev 5 page 3/28

4 Electrical characteristics Table 7. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 80 A I (1) SDM Source-drain current (pulsed) A V (2) SD Forward on voltage I SD = 80 A, V GS = 0 V V t rr Reverse recovery time I SD = 80 A, di/dt = 100 A/µs - 77 ns Q rr Reverse recovery charge V DD = 80 V, T J = 150 C nc I RRM Reverse recovery current (see Figure 18. Test circuit for inductive load switching and diode recovery times) - 4 A 1. Pulse width is limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS Rev 5 page 4/28

5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area for DPAK Figure 2. Thermal impedance for DPAK ID (A) Operation in this area is Limited by max RDS(on) AM15754v1 100µs 1 Tj=175 C Tc=25 C Single pulse VDS(V) 1ms 10ms Figure 3. Safe operating area for TO-220FP ID (A) 100 Operation in this area is Limited by max RDS(on) AM15755v1 Figure 4. Thermal impedance for TO-220FP µs * 1 Tj=175 C Tc=25 C Single pulse VDS(V) 1ms 10ms Figure 5. Safe operating area for D 2 PAK, I 2 PAK and TO-220 Figure 6. Thermal impedance for D 2 PAK, I 2 PAK and TO-220 ID (A) Operation in this area is Limited by max RDS(on) AM15756v1 100µs K 10-1 δ= AM15761v1 1 Tj=175 C Tc=25 C Single pulse VDS(V) 1ms 10ms Single pulse tp(s) DS Rev 5 page 5/28

6 Electrical characteristics (curves) Figure 7. Output characteristics Figure 8. Transfer characteristics ID (A) 300 VGS=10V AM15757v1 9V ID (A) 300 VDS=5V AM15745v V V V 50 5V VDS(V) VGS(V) Figure 9. Normalized V (BR)DSS vs temperature Figure 10. Static drain-source on-resistance V(BR)DSS (norm) ID=250 µa AM15747v1 RDS(on) (mω) 14.0 VGS=10V AM15748v TJ( C) ID(A) Figure 11. Gate charge vs gate-source voltage Figure 12. Capacitance variations VGS (V) VDD=50V ID=80A AM15758v1 C (pf) AM15759v1 Ciss Qg(nC) Coss Crss VDS(V) DS Rev 5 page 6/28

7 Electrical characteristics (curves) Figure 13. Normalized gate threshold voltage vs temperature VGS(th) (norm) ID= 250 µa TJ( C) AM15746v1 Figure 14. Normalized on-resistance vs temperature R DS(on) (norm) I D = 40 A V GS = 10 V TJ( C) AM15760v2 Figure 15. Source-drain diode forward characteristics VSD (V) 1.1 TJ=-55 C AM15749v TJ=25 C TJ=150 C ISD(A) DS Rev 5 page 7/28

8 Test circuits 3 Test circuits Figure 16. Test circuit for resistive load switching times Figure 17. Test circuit for gate charge behavior VDD VD RL μf 3.3 μf VDD VGS 12 V IG= CONST 47 kω 100 Ω 100 nf D.U.T. 1 kω VGS pulse width RG D.U.T. pulse width 2200 μf kω 47 kω VG 1 kω AM01468v1 AM01469v1 Figure 18. Test circuit for inductive load switching and diode recovery times Figure 19. Unclamped inductive load test circuit G 25 Ω A D D.U.T. S B A fast diode B A B G 100 µh D µf + µf VDD D.U.T. VD ID L µf 3.3 µf VDD + _ RG S Vi pulse width D.U.T. AM01471v1 AM01470v1 Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform V(BR)DSS t on t off VD t d(on) t r t d(off) t f 90% 90% IDM ID 0 10% V DS 10% VDD VDD V GS 90% AM01472v1 0 10% AM01473v1 DS Rev 5 page 8/28

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DS Rev 5 page 9/28

10 D²PAK (TO-263) type A package information 4.1 D²PAK (TO-263) type A package information Figure 22. D²PAK (TO-263) type A package outline _25 DS Rev 5 page 10/28

11 D²PAK (TO-263) type A package information Table 8. D²PAK (TO-263) type A package mechanical data Dim. mm Min. Typ. Max. A A b b c c D D D E E E e 2.54 e H J L L L R 0.40 V2 0 8 DS Rev 5 page 11/28

12 D²PAK (TO-263) type A package information Figure 23. D²PAK (TO-263) recommended footprint (dimensions are in mm) Footprint DS Rev 5 page 12/28

13 DPAK (TO-252) type A2 package information 4.2 DPAK (TO-252) type A2 package information Figure 24. DPAK (TO-252) type A2 package outline _type-A2_rev25 DS Rev 5 page 13/28

14 DPAK (TO-252) type A2 package information Table 9. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e e H L L L L R 0.20 V2 0 8 DS Rev 5 page 14/28

15 DPAK (TO-252) type A2 package information Figure 25. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_ _25 DS Rev 5 page 15/28

16 D²PAK and DPAK packing information 4.3 D²PAK and DPAK packing information Figure 26. Tape outline DS Rev 5 page 16/28

17 D²PAK and DPAK packing information Figure 27. Reel outline B 40mm min. access hole at slot location T D C A N Full radius Tape slot in core for tape start 2.5mm min.width G measured at hub AM06038v1 Table 10. D²PAK tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 D C D D 20.2 E G F N 100 K T 30.4 P P Base quantity 1000 P Bulk quantity 1000 R 50 T W DS Rev 5 page 17/28

18 D²PAK and DPAK packing information Table 11. DPAK tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty P R 40 T W DS Rev 5 page 18/28

19 TO-220FP package information 4.4 TO-220FP package information Figure 28. TO-220FP package outline _Rev_12_B DS Rev 5 page 19/28

20 TO-220FP package information Table 12. TO-220FP package mechanical data Dim. mm Min. Typ. Max. A B D E F F F G G H L2 16 L L L L L Dia DS Rev 5 page 20/28

21 I²PAK package information 4.5 I²PAK package information Figure 29. I²PAK package outline _Rev_H DS Rev 5 page 21/28

22 I²PAK package information Table 13. I²PAK package mechanical data Dim. mm Min. Typ. Max. A A b b c c D e e E L L L DS Rev 5 page 22/28

23 TO-220 type A package information 4.6 TO-220 type A package information Figure 30. TO-220 type A package outline _typeA_Rev_21 DS Rev 5 page 23/28

24 TO-220 type A package information Table 14. TO-220 type A package mechanical data Dim. mm Min. Typ. Max. A b b c D D E e e F H J L L L L øp Q DS Rev 5 page 24/28

25 Ordering information 5 Ordering information Table 15. Order codes Order code Marking Package Packing STB100N10F7 D 2 PAK Tape and reel STD100N10F7 DPAK Tape and reel STF100N10F7 100N10F7 TO-220FP Tube STI100N10F7 I 2 PAK Tube STP100N10F7 TO-220 Tube DS Rev 5 page 25/28

26 Revision history Table 16. Document revision history Date Version Changes 05-Oct Initial release. 07-Feb Apr Nov Jun Inserted device in TO-220FP. Updated title and features on the cover page, Table 1: Device summary, Table 2: Absolute maximum ratings, Table 3: Thermal resistance and Table 5: On/off states accordingly. Updated Table 6: Dynamic, Table 7: Switching times, Table 8: Source drain diode and Section 4: Package mechanical data. Added Section 5: Packaging mechanical data. Modified: the entire typical values in Table 6, tf typical value in Table 7, VSD and typical values for trr, qrr, IRRM Inserted: Table 4: Avalanche characteristics and Section 2.1: Electrical characteristics (curves) Minor text changes Inserted device in D 2 PAK. Updated title and features on the cover page, Table 1: Device summary, Table 2: Absolute maximum ratings, Table 3: Thermal resistance and Table 5: On/off states accordingly. Updated Table 6: Dynamic, Section 4: Package mechanical data and Section 5: Packaging mechanical data. Added STI100N10F7 device and updated the document accordingly. Removed maturity status indication, updated title, features and description on cover page. Updated Table 1. Absolute maximum ratings. Updated Section 4 Package information. Minor text changes DS Rev 5 page 26/28

27 Contents Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information D²PAK (TO-263) type A package information DPAK (TO-252) type A2 package information D²PAK and DPAK packing information TO-220FP package information I²PAK package information TO-220 type A package information Ordering information...25 Revision history...26 DS Rev 5 page 27/28

28 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DS Rev 5 page 28/28