STD7N60M2, STP7N60M2, STU7N60M2

Transcription

1 Datasheet N-channel 600 V, 0.86 Ω typ., 5 A, MDmesh M2 Power MOSFETs in DPAK, TO-220 and IPAK packages TAB TAB Features DPAK 1 3 TAB TO Order codes V T Jmax R DS(on) max. I D STD7N60M2 STP7N60M2 650 V 0.95 Ω 5 A IPAK D(2, TAB) STU7N60M2 Extremely low gate charge Excellent output capacitance (C OSS ) profile 100% avalanche tested Zener-protected G(1) Applications Switching applications S(3) AM01475V1 Description These devices are N-channel Power MOSFETs developed using MDmesh M2 technology. Thanks to their strip layout and improved vertical structure, these devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high efficiency converters. Product status link STD7N60M2 STP7N60M2 STU7N60M2 Product summary Order code Marking Package Packing Order code Marking Package Packing Order code Marking Package Packing STD7N60M2 7N60M2 DPAK Tape and reel STP7N60M2 7N60M2 TO-220 Tube STU7N60M2 7N60M2 IPAK Tube DS Rev 2 - July 2018 For further information contact your local STMicroelectronics sales office.

2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ±25 V I (1) Drain current (continuous) at T case = 25 C 5 D Drain current (continuous) at T case = 100 C 3.5 A I DM (2) Drain current (pulsed) 20 A P TOT Total dissipation at T case = 25 C 60 W dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns T stg T j Storage temperature range Operating junction temperature range -55 to 150 C 1. Limited by maximum junction temperature. 2. Pulse width limited by safe operating area. 3. I SD 5 A, di/dt 400 A/μs; V DS peak < V (BR)DSS, V DD =400 V 4. V DS 480 V Table 2. Thermal data Symbol Parameter Value DPAK TO-220 IPAK Unit R thj-case Thermal resistance junction-case 2.08 C/W R (1) thj-pcb Thermal resistance junction-pcb 50 C/W R thj-amb Thermal resistance junction-ambient C/W 1. When mounted on 1 inch² FR-4, 2 Oz copper board Table 3. Avalanche characteristics Symbol Parameter Value Unit I AR Avalanche current, repetitive or non-repetitive (pulse width limited by T Jmax ) 1.5 A E AS Single pulse avalanche energy (starting T j = 25 C, I D = I AR, V DD = 50 V) 99 mj DS Rev 2 page 2/26

3 Electrical characteristics 2 Electrical characteristics (T case = 25 C unless otherwise specified) Table 4. Static Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS Drain-source breakdown voltage V GS = 0 V, I D = 1 ma 600 V I DSS Zero gate voltage drain current V GS = 0 V, V DS = 600 V 1 V GS = 0 V, V DS = 600 V, T case = 125 C (1) 100 µa I GSS Gate-body leakage current V DS = 0 V, V GS = ±25 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa V R DS(on) Static drain-source onresistance V GS = 10 V, I D = 2.5 A Ω 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance C oss Output capacitance V DS = 100 V, f = 1 MHz, V GS = 0 V pf C rss Reverse transfer capacitance C oss eq. (1) Equivalent output capacitance V DS = 0 to 480 V, V GS = 0 V pf R G Intrinsic gate resistance f = 1 MHz, I D = 0 A Ω Q g Total gate charge V DD = 480 V, I D = 5 A, Q gs Gate-source charge V GS = 0 to 10 V (see Figure 17. Test Q gd Gate-drain charge circuit for gate charge behavior) nc 1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS. Table 6. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f Turn-on delay time Rise time Turn-off delay time Fall time V DD = 300 V, I D = 2.5 A, R G = 4.7 Ω, V GS = 10 V (see Figure 16. Test circuit for resistive load switching times and Figure 21. Switching time waveform) ns DS Rev 2 page 3/26

4 Electrical characteristics Table 7. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 5 A I (1) SDM Source-drain current (pulsed) - 20 A V (2) SD Forward on voltage V GS = 0 V, I SD = 5 A V t rr Reverse recovery time I SD = 5 A, di/dt = 100 A/µs, ns Q rr Reverse recovery charge V DD = 60 V (see Figure 18. Test circuit for inductive load switching and μc I RRM Reverse recovery current diode recovery times ) - 11 A t rr Reverse recovery time I SD = 5 A, di/dt = 100 A/µs, ns Q rr Reverse recovery charge V DD = 60 V, T j = 150 C (see Figure 18. Test circuit for inductive load μc I RRM Reverse recovery current switching and diode recovery times ) - 11 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS Rev 2 page 4/26

5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for DPAK and IPAK Figure 3. Thermal impedance for DPAK and IPAK ID (A) AM15887v Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Single pulse 10µs 100µs 1ms 10ms VDS(V) Figure 4. Safe operating area for TO-220 Figure 5. Thermal impedance for TO-220 ID (A) AM15814v Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Single pulse 10µs 100µs 1ms 10ms VDS(V) Figure 6. Output characteristics Figure 7. Transfer characteristics I D (A) V GS =7, 8, 9, 10, 11V AM15815v1 I D (A) AM15816v1 8 6V 8 V DS = 19 V V V 4V V DS (V) V GS (V) DS Rev 2 page 5/26

6 Electrical characteristics (curves) Figure 8. Gate charge vs gate-source voltage VGS (V) VDS VDD=480V ID=5A GADG SA VDS (V) Qg(nC) Figure 9. Static drain-source on-resistance AM15817v1 RDS(on) (W) VGS=10V ID(A) Figure 10. Capacitance variations C AM15818v1 (pf) 1000 Figure 11. Output capacitance stored energy E OSS (µj) 2.5 AM15819v1 100 Ciss f = 1 Mhz Coss Crss V DS (V) V DS (V) Figure 12. Normalized gate threshold voltage vs temperature VGS(th) (norm) AM15718v1 Figure 13. Normalized on-resistance vs temperature R DS(on) (norm) 2.5 AM15821v1 1.1 ID=250µA V GS = 10 V TJ( C) T j ( C) DS Rev 2 page 6/26

7 Electrical characteristics (curves) Figure 14. Source-drain diode forward characteristics VSD GADG SA (V) TJ=-50 C TJ=150 C TJ=25 C ISD(A) Figure 15. Normalized V (BR)DSS vs temperature GADG SA VDS (norm) 1.11 ID = 1mA TJ( C) DS Rev 2 page 7/26

8 Test circuits 3 Test circuits Figure 16. Test circuit for resistive load switching times Figure 17. Test circuit for gate charge behavior VDD VD RL μf 3.3 μf VDD VGS 12 V IG= CONST 47 kω 100 Ω 100 nf D.U.T. 1 kω VGS pulse width RG D.U.T. pulse width 2200 μf kω 47 kω VG 1 kω AM01468v1 AM01469v1 Figure 18. Test circuit for inductive load switching and diode recovery times Figure 19. Unclamped inductive load test circuit G 25 Ω A D D.U.T. S B A fast diode B A B G 100 µh D µf + µf VDD D.U.T. VD ID L µf 3.3 µf VDD + _ RG S Vi pulse width D.U.T. AM01471v1 AM01470v1 Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform V(BR)DSS t on t off VD t d(on) t r t d(off) t f 90% 90% IDM ID 0 10% V DS 10% VDD VDD V GS 90% AM01472v1 0 10% AM01473v1 DS Rev 2 page 8/26

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DS Rev 2 page 9/26

10 DPAK (TO-252) type A package information 4.1 DPAK (TO-252) type A package information Figure 22. DPAK (TO-252) type A package outline _A_25 DS Rev 2 page 10/26

11 DPAK (TO-252) type A package information Table 8. DPAK (TO-252) type A mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e e H L (L1) L L R 0.20 V2 0 8 DS Rev 2 page 11/26

12 DPAK (TO-252) type C package information 4.2 DPAK (TO-252) type C package information Figure 23. DPAK (TO-252) type C package outline _C_25 DS Rev 2 page 12/26

13 DPAK (TO-252) type C package information Table 9. DPAK (TO-252) type C mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e H L L REF L L BSC L L BSC θ θ V2 0 8 DS Rev 2 page 13/26

14 DPAK (TO-252) type E package information 4.3 DPAK (TO-252) type E package information Figure 24. DPAK (TO-252) type E package outline _type-E_rev.25 DS Rev 2 page 14/26

15 DPAK (TO-252) type E package information Table 10. DPAK (TO-252) type E mechanical data Dim. mm Min. Typ. Max. A A b b c c D D E E e e H L L L L Figure 25. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_ _25 DS Rev 2 page 15/26

16 DPAK (TO-252) packing information 4.4 DPAK (TO-252) packing information Figure 26. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T Top cover tape P0 D P2 E B1 K0 B0 F W For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R User direction of feed Bending radius AM08852v1 DS Rev 2 page 16/26

17 DPAK (TO-252) packing information Figure 27. DPAK (TO-252) reel outline B 40mm min. access hole at slot location T D C A N Full radius Tape slot in core for tape start 2.5mm min.width G measured at hub AM06038v1 Table 11. DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty P R 40 T W DS Rev 2 page 17/26

18 TO-220 type A package information 4.5 TO-220 type A package information Figure 28. TO-220 type A package outline _typeA_Rev_21 DS Rev 2 page 18/26

19 TO-220 type A package information Table 12. TO-220 type A package mechanical data Dim. mm Min. Typ. Max. A b b c D D E e e F H J L L L L øp Q DS Rev 2 page 19/26

20 IPAK (TO-251) type A package information 4.6 IPAK (TO-251) type A package information Figure 29. IPAK (TO-251) type A package outline _IK_typeA_rev14 DS Rev 2 page 20/26

21 IPAK (TO-251) type A package information Table 13. IPAK (TO-251) type A package mechanical data Dim. mm Min. Typ. Max. A A b b b B c c D E e 2.28 e H L L L V1 10 DS Rev 2 page 21/26

22 IPAK (TO-251) type C package information 4.7 IPAK (TO-251) type C package information Figure 30. IPAK (TO-251) type C package outline _IK_typeC_rev14 DS Rev 2 page 22/26

23 IPAK (TO-251) type C package information Table 14. IPAK (TO-251) type C package mechanical data Dim. mm Min. Typ. Max. A A b b b c c D D E E e e H L L L θ θ DS Rev 2 page 23/26

24 Revision history Table 15. Document revision history Date Revision Changes 06-Jun First release. 12-Jul Removed maturity status indication from cover page. The document status is production data. Added Section 4.2 DPAK (TO-252) type C package information and Section 4.3 DPAK (TO-252) type E package information. Minor text changes. DS Rev 2 page 24/26

25 Contents Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information DPAK (TO-252) type A package information DPAK (TO-252) type C package information DPAK (TO-252) type E package information DPAK (TO-252) packing information TO-220 type A package information IPAK (TO-251) type A package information IPAK (TO-251) type C package information Revision history...24 DS Rev 2 page 25/26

26 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DS Rev 2 page 26/26