STD7NM60N, STF7NM60N, STU7NM60N

Transcription

1 Datasheet N-channel 600 V, 0.8 Ω typ., 5 A MDmesh II Power MOSFETs in DPAK, TO-220FP and IPAK packages Features Order code V DS R DS(on) max. I D Package STD7NM60N STF7NM60N 600 V 0.9 Ω 5 A DPAK TO-220FP D(2, TAB) STU7NM60N 100% avalanche tested Low input capacitance and gate charge Low gate input resistance IPAK G(1) Applications Switching applications S(3) AM01475v1_noZen Description These devices are N-channel Power MOSFETs developed using the second generation of MDmesh technology. These revolutionary Power MOSFETs associate a vertical structure to the company s strip layout to yield one of the world s lowest on-resistance and gate charge. They are therefore suitable for the most demanding high-efficiency converters. Product status link STD7NM60N STF7NM60N STU7NM60N DS Rev 5 - September 2018 For further information contact your local STMicroelectronics sales office.

2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter DPAK, IPAK Value TO-220FP Unit V DS Drain-source voltage 600 V V GS Gate-source voltage ±25 V I D Drain current (continuous) at T C = 25 C 5 5 (1) A I D Drain current (continuous) at T C = 100 C 3 3 (1) A I (2) DM Drain current (pulsed) (1) A P TOT Total dissipation at T C = 25 C W V ISO Insulation withstand voltage (RMS) from all three leads to external heat-sink (t = 1 s, T C = 25 C) 2.5 kv dv/dt (3) Peak diode recovery voltage slope 15 V/ns T j T stg Operating junction temperature range Storage temperature range -55 to 150 C 1. Limited by maximum junction temperature. 2. Pulse width limited by safe operating area. 3. I SD 5 A, di/dt 100 A/μs, V DSpeak V (BR)DSS, V DD = 80% V (BR)DSS. Table 2. Thermal data Symbol Parameter Value DPAK TO-220FP IPAK Unit R thj-case Thermal resistance junction-case C/W R thj-amb Thermal resistance junction-ambient C/W R (1) thj-pcb Thermal resistance junction-pcb 50 C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu. Table 3. Avalanche characteristics Symbol Parameter Value Unit I (1) AS Avalanche current, repetitive or not-repetitive 2 A E (2) AS Single pulse avalanche energy 119 mj 1. Pulse width limited by T j max. 2. Starting T j = 25 C, I D = I AS, V DD = 50 V. DS Rev 5 page 2/26

3 Electrical characteristics 2 Electrical characteristics (T CASE = 25 C unless otherwise specified) Table 4. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS I GSS Drain-source breakdown voltage Zero gate voltage drain current Gate body leakage current I D = 1 ma, V GS = 0 V 600 V V GS = 0 V, V DS = 600 V 1 µa V GS = 0 V, V DS = 600 V, T C = 125 C (1) 100 µa V DS = 0 V, V GS = ±20 V 100 na V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa V R DS(on) Static drain-source on resistance V GS = 10 V, I D = 2.5 A Ω 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance 363 C oss Output capacitance V DS = 50 V, f = 1 MHz, V GS = 0 V C rss Reverse transfer capacitance pf C oss eq. (1) Equivalent capacitance time related V DS = 0 to 480 V, V GS = 0 V pf R G Intrinsic gate resistance f = 1 MHz open drain Ω Q g Total gate charge V DD = 480 V, I D = 5 A, V GS = 0 to 10 V 14 Q gs Gate-source charge (see Figure 14. Test circuit for gate charge Q gd Gate-drain charge behavior) nc 1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS. Table 6. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f Turn-on delay time Rise time Turn-off delay time Fall time V DD = 300 V, I D = 2.5 A, R G = 4.7 Ω, V GS = 10 V - (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) ns DS Rev 5 page 3/26

4 Electrical characteristics Table 7. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD I SDM (1) Source-drain current Source-drain current (pulsed) A V (2) SD Forward on voltage I SD = 5 A, V GS = 0 V V t rr Reverse recovery time I SD = 5 A, di/dt = 100 A/µs 213 ns Q rr Reverse recovery charge V DD = 60 V (see Figure 15. Test circuit for μc I RRM Reverse recovery current inductive load switching and diode recovery times) 14 A t rr Reverse recovery time I SD = 5 A, di/dt = 100 A/µs 265 ns Q rr Reverse recovery charge V DD = 60 V, T j = 150 C(see Figure 15. Test μc I RRM Reverse recovery current circuit for inductive load switching and diode recovery times) 14 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%. DS Rev 5 page 4/26

5 Electrical characteristics curves 2.1 Electrical characteristics curves Figure 1. Safe operating area for DPAK and IPAK Figure 2. Thermal impedance for DPAK and IPAK ID AM06474v Operation in this area is Limited by max RDS(on) -1 0 Tj=150 C Tc=25 C Single puls 2 DS 10µs 100µs 1ms 10ms Figure 3. Safe operating area for TO-220FP Figure 4. Thermal impedance for TO-220FP ID AM06475v1 K GC Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Single pulse DS 10µs 100µs 1ms 10ms t p (s) Figure 5. Output characterisics Figure 6. Transfer characteristics ID(A) 9 8 VGS=10V 6V AM06477v1 ID 9 VDS=20V 8 AM06478v V VDS(V) VGS(V) DS Rev 5 page 5/26

6 Electrical characteristics curves Figure 7. Gate charge vs gate-source voltage Figure 8. Static drain-source on-resistance VGS (V) VDS VDD=480V ID=5A AM06479v1 VDS (V) RDS(on) (Ohm) VGS=10V AM06480v Qg(nC) ID(A) Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs temperature VGS(th) (norm) 1.10 ID=250µA AM06483v TJ( C) Figure 11. Normalized on-resistance vs temperature AM06484v1 RDS(on) (norm) 2.1 ID=2.5A TJ( C) Figure 12. Normalized V (BR)DSS vs temperature V AM06485v1 (BR)DSS (norm) 1.07 ID=1mA TJ( C) DS Rev 5 page 6/26

7 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD VD RL μf 3.3 μf VDD VGS 12 V IG= CONST 47 kω 100 Ω 100 nf D.U.T. 1 kω VGS pulse width RG D.U.T. pulse width 2200 μf kω 47 kω VG 1 kω AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load switching and diode recovery times Figure 16. Unclamped inductive load test circuit G 25 Ω A D D.U.T. S B A fast diode B A B G 100 µh D µf + µf VDD D.U.T. VD ID L µf 3.3 µf VDD + _ RG S Vi pulse width D.U.T. AM01471v1 AM01470v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS t on t off VD t d(on) t r t d(off) t f 90% 90% IDM ID 0 10% V DS 10% VDD VDD V GS 90% AM01472v1 0 10% AM01473v1 DS Rev 5 page 7/26

8 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DS Rev 5 page 8/26

9 DPAK (TO-252) type A package information 4.1 DPAK (TO-252) type A package information Figure 19. DPAK (TO-252) type A package outline _A_25 DS Rev 5 page 9/26

10 DPAK (TO-252) type A package information Table 8. DPAK (TO-252) type A mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e e H L (L1) L L R 0.20 V2 0 8 DS Rev 5 page 10/26

11 DPAK (TO-252) type C package information 4.2 DPAK (TO-252) type C package information Figure 20. DPAK (TO-252) type C package outline _C_25 DS Rev 5 page 11/26

12 DPAK (TO-252) type C package information Table 9. DPAK (TO-252) type C mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e H L L REF L L BSC L L BSC θ θ V2 0 8 DS Rev 5 page 12/26

13 DPAK (TO-252) type E package information 4.3 DPAK (TO-252) type E package information Figure 21. DPAK (TO-252) type E package outline _type-E_rev.25 DS Rev 5 page 13/26

14 DPAK (TO-252) type E package information Table 10. DPAK (TO-252) type E mechanical data Dim. mm Min. Typ. Max. A A b b c c D D E E e e H L L L L Figure 22. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_ _25 DS Rev 5 page 14/26

15 DPAK (TO-252) packing information 4.4 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T Top cover tape P0 D P2 E B1 K0 B0 F W For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R User direction of feed Bending radius AM08852v1 DS Rev 5 page 15/26

16 DPAK (TO-252) packing information Figure 24. DPAK (TO-252) reel outline B 40mm min. access hole at slot location T D C A N Full radius Tape slot in core for tape start 2.5mm min.width G measured at hub AM06038v1 Table 11. DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty P R 40 T W DS Rev 5 page 16/26

17 TO-220FP package information 4.5 TO-220FP package information Figure 25. TO-220FP package outline _Rev_12_B DS Rev 5 page 17/26

18 TO-220FP package information Table 12. TO-220FP package mechanical data Dim. mm Min. Typ. Max. A B D E F F F G G H L2 16 L L L L L Dia DS Rev 5 page 18/26

19 IPAK (TO-251) type A package information 4.6 IPAK (TO-251) type A package information Figure 26. IPAK (TO-251) type A package outline _IK_typeA_rev14 DS Rev 5 page 19/26

20 IPAK (TO-251) type A package information Table 13. IPAK (TO-251) type A package mechanical data Dim. mm Min. Typ. Max. A A b b b B c c D E e 2.28 e H L L L V1 10 DS Rev 5 page 20/26

21 IPAK (TO-251) type C package information 4.7 IPAK (TO-251) type C package information Figure 27. IPAK (TO-251) type C package outline _IK_typeC_rev14 DS Rev 5 page 21/26

22 IPAK (TO-251) type C package information Table 14. IPAK (TO-251) type C package mechanical data Dim. mm Min. Typ. Max. A A b b b c c D D E E e e H L L L θ θ DS Rev 5 page 22/26

23 Ordering information 5 Ordering information Table 15. Order codes Order code Marking Package Packing STD7NM60N DPAK Tape and reel STF7NM60N STU7NM60N 7NM60N TO-220FP IPAK Tube DS Rev 5 page 23/26

24 Revision history Table 16. Document revision history Date Version Changes 29-Oct First release. 19-Jul Corrected values in Table 3: Thermal data. 11-Oct Inserted new value in Table 6: Dynamic 04-Nov Sep-2018 Changed R DS(on) typical value. The part number STP7NM60N has been moved to a separate datasheet. Removed maturity status indication from cover page. The document status is production data. Updated title and features in cover page. Updated Section 1 Electrical ratings, Section 2 Electrical characteristics and Section 4 Package information. Minor text changes. DS Rev 5 page 24/26

25 Contents Contents 1 Electrical ratings Electrical characteristics Electrical characteristics curves Test circuits Package information DPAK (TO-252) type A package information DPAK (TO-252) type C package information DPAK (TO-252) type E package information DPAK (TO-252) packing information TO-220FP package information IPAK (TO-251) type A package information IPAK (TO-251) type C package information Ordering information...23 Revision history...24 DS Rev 5 page 25/26

26 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DS Rev 5 page 26/26