AD5220* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017

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2 D522* PRODUCT PGE QUICK LINKS Last Content Update: 2/23/27 COMPRLE PRTS View a parametric search of comparable parts. DOCUMENTTION pplication Notes N-29: Digital Potentiometers: Frequently sked Questions N-58: Programmable Oscillator Uses Digital Potentiometers N-582: Resolution Enhancements of Digital Potentiometers with Multiple Devices N-686: Implementing an I 2 C Reset Data Sheet D522: Increment/Decrement Digital Potentiometer Data Sheet REFERENCE MTERILS Technical rticles Rotary Encoder Mates with Digital Potentiometer DESIGN RESOURCES D522 Material Declaration PCN-PDN Information Quality nd Reliability Symbols and Footprints DISCUSSIONS View all D522 EngineerZone Discussions. SMPLE ND UY Visit the product page to see pricing options. TECHNICL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDCK Submit feedback for this data sheet. This page is dynamically generated by nalog Devices, Inc., and inserted into this data sheet. dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 D522 SPECIFICTIONS ELECTRICL CHRCTERISTICS Parameter Symbol Conditions Min Typ Max Units DC CHRCTERISTICS RHEOSTT MODE Specifications pply to ll VRs Resistor Differential NL 2 R-DNL R, V = NC, R = kω ±.4 LS R, V = NC, R = 5 kω or kω.5 ±..5 LS Resistor Nonlinearity 2 R-INL R, V = NC, R = kω ±.5 LS R, V = NC, R = 5 kω or kω.5 ±..5 LS Nominal Resistor Tolerance R T = 25 C 3 3 % Resistance Temperature Coefficient R / T V = V DD, iper = No Connect 8 ppm/ C iper Resistance R I = V DD /R, V DD = 3 V or 5 V 4 Ω DC CHRCTERISTICS POTENTIOMETER DIVIDER MODE Specifications pply to ll VRs Resolution N 7 its Integral Nonlinearity 3 INL R = kω ±.5 LS R = 5 kω, kω.5 ±.2.5 LS Differential Nonlinearity Error 3 DNL R = kω ±.4 LS R = 5 kω, kω.5 ±..5 LS Voltage Divider Temperature Coefficient V / T Code = 4 H 2 ppm/ C Full-Scale Error V FSE Code = 7F H 2.5 LS Zero-Scale Error V ZSE Code = H.5 LS RESISTOR TERMINLS Voltage Range 4 V, V, V V DD V Capacitance 5, C, C f = MHz, Measured to GND, Code = 4 H pf Capacitance 5 C f = MHz, Measured to GND, Code = 4 H 48 pf Common-Mode Leakage I CM V = V = V 7.5 n DIGITL INPUTS ND OUTPUTS Input Logic High V IH V DD = 5 V/3 V 2.4/2. V Input Logic Low V IL V DD = 5 V/3 V.8/.6 V Input Current I IL V IN = V or 5 V ± µ Input Capacitance 5 C IL 5 pf POER SUPPLIES Power Supply Range V DD V Supply Current I DD V IH = 5 V or V IL = V, V DD = 5 V 5 4 µ Power Dissipation 6 P DISS V IH = 5 V or V IL = V, V DD = 5 V 75 2 µ Power Supply Sensitivity PSS.4.5 %/% 5, 7, 8 DYNMIC CHRCTERISTICS andwidth 3 d _K R = kω, Code = 4 H 65 khz _5K R = 5 kω, Code = 4 H 42 khz _K R = kω, Code = 4 H 69 khz Total Harmonic Distortion THD V = V rms 2.5 V dc, V = 2.5 V dc, f = khz.2 % V Settling Time t S V = V DD, V = V, 5% of Final Value, K/5K/K.6/3/6 µs Resistor Noise Voltage e N R = 5 kω, f = khz 4 nv/ Hz INTERFCE TIMING CHRCTERISTICS pplies to ll Parts 5, 9 Input Clock Pulsewidth t CH, t CL Clock Level High or Low 25 ns CS to CLK Setup Time t CSS 2 ns CS Rise to Clock Hold Time t CSH 2 ns U/D to Clock Fall Setup Time t UDS ns NOTES Typicals represent average readings at 25 C and V DD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit. 3 INL and DNL are measured at V with the RDC configured as a potentiometer divider similar to a voltage output D/ converter. V = V DD and V = V. DNL specification limits of ± LS maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit. 4 Resistor terminals,, have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 P DISS is calculated from (I DD V DD ). CMOS logic level inputs result in minimum power dissipation. 7 andwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 ll dynamic characteristics use V DD = 5 V. 9 See timing diagrams for location of measured values. ll input control voltages are specified with t R = t F = ns (% to 9% of V DD ) and timed from a voltage level of.6 V. Switching characteristics are measured using both V DD = 3 V or 5 V. Specifications subject to change without notice. (V DD = 3 V % or 5 V %, V = V DD, V = V, 4 C < T < 85 C unless otherwise noted) 2 REV.

4 D522 SOLUTE MXIMUM RTINGS* (T = 25 C, unless otherwise noted) V DD to GND V, 7 V V, V, V to GND V, V DD X X, X X, X X ±2 m Digital Input Voltage to GND V, V DD.3 V Operating Temperature Range C to 85 C Maximum Junction Temperature (T J MX) C Storage Temperature C to 5 C Lead Temperature (Soldering, sec) C Package Power Dissipation (T J max T )/θ J Thermal Resistance θ J P-DIP (N-8) C/ SOIC (SO-8) C/ µsoic (RM-8) C/ *Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CS Table I. Truth Table CS CLK U/D Operation L t H iper Increment Toward Terminal L t L iper Decrement Toward Terminal H X X iper Position Fixed t CSS t CH tcsh PIN CONFIGURTION CLK U/D GND D522 TOP VIE (Not to Scale) V DD CS PIN FUNCTION DESCRIPTIONS Pin No. Name Description CLK Serial Clock Input, Negative Edge Triggered 2 U/D UP/DON Direction Increment Control 3 Terminal 4 GND Ground 5 iper Terminal 6 Terminal 7 CS Chip Select Input, ctive Low 8 V DD Positive Power Supply CLK U/D t CL t UDS Figure 3. Detail Timing Diagram CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough the D522 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. RNING! ESD SENSITIVE DEVICE REV. 3

5 D522 Typical Performance Characteristics PERCENT OF NOMINL END-TO-END RESISTNCE % R R R Figure 4. iper to End Terminal Resistance vs. Code V V V DD = 5.5V R = 5k 7F H 4 H 2 H 8 H H 4H 2H H CONDUCTION CURRENT, I Figure 5. Resistance Linearity vs. Conduction Current FREQUENCY SS = 3 UNITS V DD = 2.7V T = 25 C IPER RESISTNCE Figure 6. iper Contact Resistance RDNL LS k VERSION T = 25 C k VERSION k VERSION RINL LS k VERSION T = 25 C 5k VERSION k VERSION INL LS k VERSION T = 25 C V = 5.5V V = V 5k VERSION k VERSION Figure 7. R-DNL Relative Resistance Step Position Nonlinearity Error vs. Code Figure 8. R-INL Resistance Nonlinearity Error vs. Supply Voltage Figure 9. Potentiometer Divider INL Error vs. Code DNL LS k VERSION 5k VERSION k VERSION T = 25 C V = 5.5V V = V Figure. Potentiometer Divider DNL Error vs. Code POTENTIOMETER DIVIDER NONLINERITY LS CODE = 4 H R = 5k V = V DD SUPPLY VOLTGE V Figure. Potentiometer Divider INL Error vs. Supply Voltage NOMINL END-TO-END RESISTNCE k k VERSION 5k VERSION k VERSION TEMPERTURE C Figure 2. Nominal Resistance vs. Temperature 4 REV.

6 D522 POTENTIOMETER MODE TEMPCO ppm/ C k VERSION 55 C < T < 85 C 5k ND k VERSION Figure 3. V / T Potentiometer Mode Tempco ( kω and 5 kω) RHEOSTT MODE TEMPCO ppm/ C 6 55 C < T < 85 C R MESURED V = NO CONNECT 39 k VERSION k ND k VERSION Figure 4. R / T Rheostat GIN d k DT = 4 H V DD = 5V V IN = V = mv rms V = 2.5V OP42 2.5V k k FREQUENCY Hz H 4 H 2 H H 8 H 4 H 2 H H M Figure 5. kω Gain vs. Frequency vs. Code GIN d k DT = 4 H V DD = 5V V IN = V = mv rms V = 2.5V OP42 2.5V H 4 H 2 H H 8 H 4 H 2 H H k k FREQUENCY Hz M Figure 6. 5 kω Gain vs. Frequency vs. Code GIN d k DT = 4 H V DD = 5V V IN = V = mv rms V = 2.5V H 4 H 2 H H 8 H 4 H 2 H H OP42 2.5V k k FREQUENCY Hz Figure 7. kω Gain vs. Frequency vs. Code M V TIME 2 s / DIV V = V = V f = khz Figure 8. Digital Feedthrough 2mV/ DIV V CLK V = 5.5V V = V f = khz TIME 5ns / DIV DT 4 H v 3F H 5mV mv 5mV mv 5V V Figure 9. Midscale Transition Glitch THD NOISE %..... T = 25 C V DD = 5.V OFFSET GND = 2.5V R = k NONINVERTING TEST CKT 32 INVERTING TEST CKT 3 k k k FREQUENCY Hz Figure 2. Total Harmonic Distortion Plus Noise vs. Frequency NORMLIZED GIN FLTNESS d DT = 4 H V DD = 5V V IN = V = 5mV rms V = 2.5V OP42 2.5V k 5k k 6.8 k k k M FREQUENCY Hz Figure 2. Normalized Gain Flatness vs. Frequency REV. 5

7 D522 PSRR d k V DD = 5V DC V p-p C T = 25 C CODE = 4 H C L = pf V = 4V, V = V k k FREQUENCY Hz M Figure 22. Power Supply Rejection vs. Frequency I DD SUPPLY CURRENT k DT = 3F H V = V T = 25 C V = 5.5V V DD = 2.7V V = 2.7V k k M CLOCK FREQUENCY Hz Figure 23. I DD Supply Current vs. Clock Frequency M R ON T = 25 C SEE FIGURE 34 FOR TEST CIRCUIT V DD = 2.7V V Volts Figure 24. Incremental iper Contact Resistance vs. V I DD SUPPLY CURRENT m... LOGIC = V OR V DD V D = 5.5V V DD = 3.3V SUPPLY CURRENT m.. T = 25 C LL LOGIC INPUT PINS TIED TOGETHER V DD = 3V V DD = 5V TEMPERTURE C Figure 25. Supply Current vs. Temperature I DD DIGITL INPUT VOLTGE V Figure 26. Supply Current vs. Input Logic Voltage 6 REV.

8 Parametric Test Circuits D522 V V = V DD LS = V/28 V MS OFFSET GND V IN ~ 2.5V DC 5V OP279 V OUT Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) Figure 3. Inverting Programmable Gain Test Circuit NO CONNECT 5V V MS I OFFSET GND V IN ~ 2.5V OP279 V OUT Figure 28. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 32. Noninverting Programmable Gain Test Circuit V MS2 I = V DD /R NOMINL V V R MS = [V MS V MS2 ]/I OFFSET GND V IN ~ 2.5V 5V OP42 V OUT 5V Figure 29. iper Resistance Test Circuit Figure 33. Gain vs. Frequency Test Circuit V ~ V V DD V MS V = V DD ± % V MS PSRR (d) = 2 LOG ( ) V DD V MS % PSS (%/%) = V DD % I S R S =.V I S CODE = ØØ H.V TO V DD Figure 3. Power Supply Sensitivity Test Circuit (PSS, PSRR) Figure 34. Incremental ON Resistance Test Circuit REV. 7

9 D522 OPERTION The D522 provides a 28-position digitally controlled variable resistor (VR) device. Changing the VR settings is accomplished by pulsing the CLK pin while CS is active low. The direction of the increment is controlled by the U/D (UP/DON) control input pin. hen the wiper hits the end of the resistor (Terminals or ) additional CLK pulses no longer change the wiper setting. The wiper position is immediately decoded by the wiper decode logic changing the wiper resistance. ppropriate debounce circuitry is required when push button switches are used to control the count sequence and direction of count. The exact timing requirements are shown in Figure 3. The D522 powers ON in a centered wiper position exhibiting nearly equal resistances of R and R. CLK CS U/D EN POR 4 H UP/ DON CNTR RS 7 D E C O D E D522 Figure 35. lock Diagram V DD GND DIGITL INTERFCING OPERTION The D522 contains a three-wire serial input interface. The three inputs are clock (CLK), CS and UP/DON (U/D). The negative-edge sensitive CLK input requires clean transitions to avoid clocking multiple pulses into the internal UP/DON counter register, see Figure 35. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. hen CS is taken active low the clock begins to increment or decrement the internal UP/DON counter dependent upon the state of the U/D control pin. The UP/DON counter value (D) starts at 4 H at system power ON. Each new CLK pulse will increment the value of the internal counter by one LS until the full scale value of 3F H is reached as long as the U/D pin is logic high. If the U/D pin is taken to logic low the counter will count down stopping at code H (zero-scale). dditional clock pulses on the CLK pin are ignored when the wiper is at either the H position or the 3F H position. ll digital inputs (CS, U/D, CLK) are protected with a series input resistor and parallel Zener ESD structure shown in Figure 36. k LOGIC Figure 36. Equivalent ESD Protection Digital Pins,, GND 2 Figure 37. Equivalent ESD Protection nalog Pins D D D2 D3 D4 D5 D6 RDC UP/DON CNTR & DECODE R S R S R S R S = R NOMINL /28 Figure 38. D522 Equivalent RDC Circuit PROGRMMING THE VRILE RESISTOR Rheostat Operation The nominal resistance of the RDC between terminals and is available with values of kω, 5 kω, and kω. The final three characters of the part number determine the nominal resistance value, e.g., kω =; 5 kω = 5; kω =. The nominal resistance (R ) of the VR has 28 contact points accessed by the wiper terminal, plus the terminal contact. t power ON the resistance from the wiper to either end Terminal or is approximately equal. Clocking the CLK pin will increase the resistance from the iper to Terminal by one unit of R S resistance (see Figure 38). The resistance R is determined by the number of pulses applied to the clock pin. Each segment of the internal resistor string has a nominal resistance value of R S = R /28, which becomes 78 Ω in the case of the kω D522N product. Care should be taken to limit the current flow between and in the direct contact state to a maximum value of 5 m to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDC replaces, it is totally symmetrical (see Figure 38). The resistance between the iper and Terminal also produces a digitally controlled resistance R. hen these terminals are used the terminal should be tied to the wiper. The typical part-to-part distribution of R is process lot dependent having a ± 3% variation. The change in R with temperature has a 8 ppm/ C temperature coefficient. The R temperature coefficient increases as the wiper is programmed near the -terminal due to the larger percentage contribution of the wiper contact switch resistance, which has a.5%/ C temperature coefficient. Figure 4 shows the effect of the wiper contact resistance as a function of code setting. nother performance factor influenced by the switch contact resistance is the relative linearity error performance between the kω, and the 5 kω or kω versions. The same switch contact resistance is used in all three versions. Thus the performance of the 5 kω and kω devices which have the least impact on wiper switch resistance exhibits the best linearity error, see Figures 7 and 8. x x x 8 REV.

10 D522 PROGRMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting Terminal to 5 V and Terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to LS less than 5 V. Each LS of voltage is equal to the voltage applied across terminals divided by the 28-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals is: V (D) = D/28 V V () D represents the current contents of the internal UP/DON counter. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value, therefore, the drift improves to 2 ppm/ C. PPLICTIONS INFORMTION The negative-edge sensitive CLK pin does not contain any internal debounce circuitry. This standard CMOS logic input responds to fast negative edges and needs to be debounced externally with an appropriate circuit designed for the type of switch closure device being used. Good performance results at the CLK input pin when the negative logic transition has a minimum slew rate of V/µs. wide variety of standard circuits can be used such as a one-shot multivibrator, Schmitt Triggered gates, cross coupled flip-flops, or RC filters to drive the CLK pin with uniform negative edges. This will prevent the digital potentiometer from skipping output codes while counting due to switch contact bounce. REV. 9

11 D522 OUTLINE DIMENSIONS.4 (.6).365 (9.27).355 (9.2).2 (5.33) MX.5 (3.8).3 (3.3).5 (2.92).22 (.56).8 (.46).4 (.36) 8. (2.54) SC 5.28 (7.).25 (6.35) 4.24 (6.).5 (.38) MIN SETING PLNE.5 (.3) MIN.6 (.52) MX.5 (.38) GUGE PLNE.325 (8.26).3 (7.87).3 (7.62).43 (.92) MX.95 (4.95).3 (3.3).5 (2.92).4 (.36). (.25).8 (.2).7 (.78).6 (.52).45 (.4) COMPLINT TO JEDEC STNDRDS MS- CONTROLLING DIMENSIONS RE IN INCHES; MILLIMETER DIMENSIONS (IN PRENTHESES) RE ROUNDED-OFF INCH EQUIVLENTS FOR REFERENCE ONLY ND RE NOT PPROPRITE FOR USE IN DESIGN. CORNER LEDS MY E CONFIGURED S HOLE OR HLF LEDS. Figure Lead Plastic Dual In-Line Package [PDIP] Narrow ody (N-8) Dimensions shown in inches and (millimeters) (.574) 3.8 (.497).25 (.98). (.4) COPLNRITY. SETING PLNE 5. (.968) 4.8 (.89) (.5) SC 6.2 (.244) 5.8 (.2284).75 (.688).35 (.532).5 (.2).3 (.22).25 (.98).7 (.67).5 (.96).25 (.99).27 (.5).4 (.57) COMPLINT TO JEDEC STNDRDS MS-2- CONTROLLING DIMENSIONS RE IN MILLIMETERS; INCH DIMENSIONS (IN PRENTHESES) RE ROUNDED-OFF MILLIMETER EQUIVLENTS FOR REFERENCE ONLY ND RE NOT PPROPRITE FOR USE IN DESIGN. Figure 4. 8-Lead Standard Small Outline Package [SOIC_N] Narrow ody (R-8) Dimensions in millimeters and (inches) PIN IDENTIFIER COPLNRITY SC MX 6 5 MX.23.9 COMPLINT TO JEDEC STNDRDS MO-87- Figure 4. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters REV.

12 D522 ORDERING GUIDE Model, 2, 3 R (kω) Temperature Range Package Description Package Option randing D522NZ 4 C to 85 C 8-Lead PDIP N-8 D522NZ 4 C to 85 C 8-Lead PDIP N-8 D522NZ5 5 4 C to 85 C 8-Lead PDIP N-8 D522R 4 C to 85 C 8-Lead SOIC_N R-8 D522R-REEL7 4 C to 85 C 8-Lead SOIC_N R-8 D522R 4 C to 85 C 8-Lead SOIC_N R-8 D522R-REEL 4 C to 85 C 8-Lead SOIC_N R-8 D522R-REEL7 4 C to 85 C 8-Lead SOIC_N R-8 D522RZ 4 C to 85 C 8-Lead SOIC_N R-8 D522RZ-REEL 4 C to 85 C 8-Lead SOIC_N R-8 D522RZ-REEL7 4 C to 85 C 8-Lead SOIC_N R-8 D522RZ-REEL7 4 C to 85 C 8-Lead SOIC_N R-8 D522RZ 4 C to 85 C 8-Lead SOIC_N R-8 D522RZ-REEL7 4 C to 85 C 8-Lead SOIC_N R-8 D522RZ5 5 4 C to 85 C 8-Lead SOIC_N R-8 D522RM 4 C to 85 C 8-Lead MSOP RM-8 DQC D522RM-REEL7 4 C to 85 C 8-Lead MSOP RM-8 DQC D522RMZ 4 C to 85 C 8-Lead MSOP RM-8 D9H D522RMZ-REEL7 4 C to 85 C 8-Lead MSOP RM-8 D9H D522RMZ 4 C to 85 C 8-Lead MSOP RM-8 #DQC D522RMZ-R7 4 C to 85 C 8-Lead MSOP RM-8 #DQC D522RMZ5 5 4 C to 85 C 8-Lead MSOP RM-8 #DQ D522RMZ5-RL7 5 4 C to 85 C 8-Lead MSOP RM-8 #DQ Z = RoHS Compliant Part. 2 The D522 die size is 37 mil 54 mil, 998 sq mil;.938 mm.372 mm,.289 sq mm. Contains 754 transistors. Patent Number applies. 3 = Qualified for utomotive Products. UTOMOTIVE PRODUCTS The D522 models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local nalog Devices account representative for specific product ordering information and to obtain the specific utomotive Reliability reports for these models. REVISION HISTORY 2/ Rev. to Rev. Changes to Features Section... Updated Outline Dimensions... Changes to Ordering Guide... dded utomotive Products Section... /98 Revision : Initial Version 2 nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /() REV. --