Dual 256-Position SPI Digital Potentiometer AD5162

Transcription

1 FETURES 2-Channel, 256-position End-to-end resistance 2.5 kω, kω, 5 kω, kω Compact MSOP- (3 mm 4.9 mm) Package SPI compatible interface Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 35 ppm/ C Low power, IDD = 5 µ ide operating temperature 4 C to +25 C Evaluation board available Dual 256-Position SPI Digital Potentiometer D562 FUNCTIONL LOCK DIGRM CLK CS SDI SPI INTERFCE = = IPER REGISTER PPLICTIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing utomotive electronics adjustment Gain control and offset adjustment IPER REGISTER 2 Figure. 2 2 GENERL OVERVIE The D562 provides a compact 3x4.9mm packaged solution for dual 256 position adjustment applications. Channel one is a three terminal potentiometer whereas channel two is a two terminal channel to be used in rheostat mode. This device performs the same electronic adjustment function as a mechanical potentiometer or a variable resistor. vailable in four different end-to-end resistance values (2.5k, k, 5k, k ) these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the SPI compatible digital interface. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDC latch. Operating from a 2.7 to 5.5 volt power supply and consuming less than 5µ allows for usage in portable battery operated applications. PIN CONFIGURTION CS SDI CLK Figure 2. ll parts are guaranteed to operate over the extended temperature range of -4 C to +25 C. Note: The terms digital potentiometer, VR, and RDC are used interchangeably. Rev. PrE5/2/3 Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology ay, P.O. ox 96, Norwood, M , U.S.. Tel: Fax: nalog Devices, Inc. ll rights reserved.

2 D562 TLE OF CONTENTS Electrical Characteristics 2.5 kω Version... 3 Electrical Characteristics kω, 5 kω, kω Versions... 4 Timing Characteristics 2.5 kω, kω, 5 kω, kω Versions... 5 bsolute Maximum Ratings... 5 Typical Performance Characteristics... 6 Test Circuits... 7 SPI Interface... 8 Operation... 9 Programming the Variable Resistor... 9 Programming the Potentiometer Divider... Preliminary Technical Data ESD Protection... Terminal Voltage Operating Range... Power-Up Sequence... Layout and Power Supply ypassing... Pin Configuration and Function Descriptions... 2 Pin Configuration... 2 Pin Function Descriptions... 2 Outline Dimensions... 3 Ordering Guide... 3 ESD Caution... 3 SPI Compatible 3-ire Serial us... REVISION HISTORY Revision : Initial Version Rev. PrE 5/2/3 Page 2 of 3

3 D562 ELECTRICL CHRCTERISTICS 2.5 kω VERSION (VDD = 5 V ± %, or 3 V ± %; V = +VDD; V = V; 4 C < T < +25 C; unless otherwise noted.) Table. Parameter Symbol Conditions Min Typ Max Unit DC CHRCTERISTICS RHEOSTT MODE Resistor Differential Nonlinearity 2 R-DNL R, V = no connect.8 ± LS Resistor Integral Nonlinearity 2 R-INL R, V = no connect 5 ± LS Nominal Resistor Tolerance 3 R T = 25 C 3 +3 % Resistance Temperature Coefficient R/ T V = VDD, iper = no connect 45 ppm/ C iper Resistance R 5 2 Ω DC CHRCTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N 8 its Differential Nonlinearity 4 DNL.5 ±. +.5 LS Integral Nonlinearity 4 INL.5 ± LS Voltage Divider Temperature Coefficient V/ T Code = x8 5 ppm/ C Full-Scale Error VFSE Code = xff LS Zero-Scale Error VZSE Code = x LS RESISTOR TERMINLS Voltage Range 5 V,, VDD V Capacitance 6, C, f = MHz, measured to, 45 pf Code = x8 Capacitance 6 C f = MHz, measured to, 6 pf Code = x8 Shutdown Supply Current 7 IDD_SD VDD = 5.5 V. µ Common-Mode Leakage ICM V = V = VDD/2 n DIGITL INPUTS ND OUTPUTS Input Logic High VIH 2.4 V Input Logic Low VIL.8 V Input Logic High VIH VDD = 3 V 2. V Input Logic Low VIL VDD = 3 V.6 V Input Current IIL VIN = V or 5 V ± µ Input Capacitance 6 CIL 5 pf POER SUPPLIES Power Supply Range VDD RNGE V Supply Current IDD VIH = 5 V or VIL = V 5 µ Power Dissipation 8 PDISS VIH = 5 V or VIL = V, VDD = 5 V.2 m Power Supply Sensitivity PSS VDD = +5 V ± %, ±.2 ±.5 %/% Code = Midscale DYNMIC CHRCTERISTICS 6, 9 andwidth 3d _2.5K R = 2.5 kω, Code = x8 2.4 MHz Total Harmonic Distortion THD V = V rms, V = V, f = khz.5 % V Settling Time ts V= 5 V, V = V, ± LS error µs band Resistor Noise Voltage Density en_ R = 2.5 kω, RS = 6 nv/ Hz Rev. PrE 5/2/3 Page 3 of 3

4 D562 Preliminary Technical Data ELECTRICL CHRCTERISTICS kω, 5 kω, kω VERSIONS (VDD = 5 V ± %, or 3 V ± %; V = VDD; V = V; 4 C < T < +25 C; unless otherwise noted.) Table 2. Parameter Symbol Conditions Min Typ Max Unit DC CHRCTERISTICS RHEOSTT MODE Resistor Differential Nonlinearity 2 R-DNL R, V = no connect ±.25 + LS Resistor Integral Nonlinearity 2 R-INL R, V = no connect 2 ±.5 +2 LS Nominal Resistor Tolerance 3 R T = 25 C 3 +3 % Resistance Temperature Coefficient R/ T V = VDD, 45 ppm/ C iper = no connect iper Resistance R VDD = 5 V 5 2 Ω DC CHRCTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N 8 its Differential Nonlinearity 4 DNL ±. + LS Integral Nonlinearity 4 INL ±.3 + LS Voltage Divider Temperature Coefficient V/ T Code = x8 5 ppm/ C Full-Scale Error VFSE Code = xff 3 LS Zero-Scale Error VZSE Code = x 3 LS RESISTOR TERMINLS Voltage Range 5 V,, VDD V Capacitance 6, C, f = MHz, measured to 45 pf, Code = x8 Capacitance 6 C f = MHz, measured to 6 pf, Code = x8 Shutdown Supply Current 7 IDD_SD VDD = 5.5 V. µ Common-Mode Leakage ICM V = V = VDD/2 n DIGITL INPUTS ND OUTPUTS Input Logic High VIH 2.4 V Input Logic Low VIL.8 V Input Logic High VIH VDD = 3 V 2. V Input Logic Low VIL VDD = 3 V.6 V Input Current IIL VIN = V or 5 V ± µ Input Capacitance 6 CIL 5 pf POER SUPPLIES Power Supply Range VDD RNGE V Supply Current IDD VIH = 5 V or VIL = V 5 µ Power Dissipation 8 PDISS VIH = 5 V or VIL = V,.2 m VDD = 5 V Power Supply Sensitivity PSS VDD = +5 V ± %, ±.2 ±.5 %/% Code = Midscale DYNMIC CHRCTERISTICS 6, 9 andwidth 3d R = kω/5 kω/ kω, 6//4 khz Code = x8 Total Harmonic Distortion THD V = V rms, V = V,.5 % f = khz, R = kω V Settling Time ( kω/5 kω/ kω) ts V = 5 V, V = V, 2 µs ± LS error band Resistor Noise Voltage Density en_ R = 5 kω, RS = 9 nv/ Hz Rev. PrE 5/2/3 Page 4 of 3

5 D562 TIMING CHRCTERISTICS 2.5 kω, kω, 5 kω, kω VERSIONS (VDD = +5V ± %, or +3V ± %; V = VDD; V = V; 4 C < T < +25 C; unless otherwise noted.) Table 3. Parameter Symbol Conditions Min Typ Max Unit SPI INTERFCE TIMING CHRCTERISTICS 6, (Specifications pply to ll Parts) Clock Frequency fclk 25 MHz Input Clock Pulsewidth tch, tcl Clock level high or low 2 ns Data Setup Time tds 5 ns Data Hold Time tdh 5 ns CS Setup Time tcss 5 ns CS High Pulsewidth tcs 4 ns CLK Fall to CS Fall Hold Time tcsh ns CLK Fall to CS Rise Hold Time tcsh ns CS Rise to Clock Rise Setup tcs ns NOTES Typical specifications represent average readings at +25 C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 V = VDD, iper (V) = no connect. 4 INL and DNL are measured at V with the RDC configured as a potentiometer divider similar to a voltage output D/ converter. V = VDD and V = V. DNL specification limits of ± LS maximum are guaranteed monotonic operating conditions. 5 Resistor terminals,, have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the terminal. The terminal is open circuited in shutdown mode. 8 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. 9 ll dynamic characteristics use VDD = 5 V. See timing diagram for location of measured values. ll input control voltages are specified with tr = tf = 2 ns (% to 9% of 3 V) and timed from a voltage level of.5 V. SOLUTE MXIMUM RTINGS (T = +25 C, unless otherwise noted.) Table 4. Parameter Value VDD to.3 V to +7 V V, V, V to VDD IMX ±2 m Digital Inputs and Output Voltage to V to +7 V Operating Temperature Range 4 C to +25 C Maximum Junction Temperature (TJMX) 5 C Storage Temperature 65 C to +5 C Lead Temperature (Soldering, sec) 3 C Thermal Resistance 2 θj: MSOP- 23 C/ NOTES Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the,, and terminals at a given resistance. 2 Package power dissipation = (TJMX T)/θJ. Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. PrE 5/2/3 Page 5 of 3

6 D562 Preliminary Technical Data TYPICL PERFORMNCE CHRCTERISTICS Rev. PrE 5/2/3 Page 6 of 3

7 D562 TEST CIRCUITS Figure 3 to Figure illustrate the test circuits that define the test conditions used in the product specification tables. 5V V+ V+ = LS = V+/2 N V MS OFFSET V IN OFFSET IS OP279 V OUT Figure 3. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 8. Test Circuit for Noninverting Gain NO CONNECT V MS I OFFSET V IN 2.5V +5V D86 5V V OUT Figure 4. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 9. Test Circuit for Gain vs. Frequency V MS2 V I = /R NOMINL I S R S =.V I S CODE = x.v V MS R = [V MS V MS2 ]/I V SS TO Figure 5. Test Circuit for iper Resistance Figure. Test Circuit for Incremental ON Resistance V+ V V+ = % VMS PSRR (d) = 2 LOG V MS % PSS (%/%) = % V MS ( ) V SS NC I CM V CM Figure 6. Test Circuit for Power Supply Sensitivity (PSS, PSSR) NC NC = NO CONNECT Figure. Test Circuit for Common-Mode Leakage current V IN 5V OFFSET OFFSET IS OP279 V OUT Figure 7. Test Circuit for Inverting Gain Rev. PrE 5/2/3 Page 7 of 3

8 D562 Preliminary Technical Data SPI INTERFCE Table 5. D56 Serial Data-ord Format D7 D6 D5 D4 D3 D2 D D MS LS SDI CLK CS D7 D6 D5 D4 D3 D2 D D RDC REGISTERLOD VOUT Figure 2. D562 SPI Interface Timing Diagram (V = 5 V, V = V, V = VOUT) SDI (DT IN) Dx Dx t DS t CH CLK t CH t CS t CSHO t CL t CSH CS t CSS t CS t S VOUT ±LS Figure 3. SPI Interface Detailed Timing Diagram (V = 5 V, V = V, V = VOUT) Rev. PrE 5/2/3 Page 8 of 3

9 OPERTION The D562 is a dual channel, 256-position digitally controlled variable resistor (VR) device. n internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. PROGRMMING THE VRILE RESISTOR Rheostat Operation The nominal resistance of the RDC between terminals and is available in 5 kω, kω, 5 kω, and kω. The final two or three digits of the part number determine the nominal resistance value, e.g., kω = ; 5 kω = 5. The nominal resistance (R) of the VR has 256 contact points accessed by the wiper terminal, plus the terminal contact. The 8-bit data in the RDC latch is decoded to select one of the 256 possible settings. ssume a kω part is used, the wiper s first connection starts at the terminal for data x. Since there is a 6 Ω wiper contact resistance, such connection yields a minimum of 6 Ω resistance between terminals and. The second connection is the first tap point, which corresponds to 99 Ω (R = R/256 + R = 39 Ω + 6 Ω) for data x. The third connection is the next tap point, representing 77 Ω (2 39 Ω + 6 Ω) for data x2, and so on. Each LS data value increase moves the wiper up the resistor ladder until the last tap point is reached at 996 Ω (R LS + R). Figure 4 shows a simplified diagram of the equivalent RDC circuit where the last resistor string will not be accessed; therefore, there is LS less of the nominal resistance at full scale in addition to the wiper resistance. D7 D6 D5 D4 D3 D2 D D RDC LTCH ND DECODER R S R S R S R S Figure 4. D562 Equivalent RDC Circuit D562 The general equation determining the digitally programmed output resistance between and is D R ( D) = R + R () 256 where D is the decimal equivalent of the binary code loaded in the 8-bit RDC register, R is the end-to-end resistance, and R is the wiper resistance contributed by the on resistance of the internal switch. In summary, if R = kω and the terminal is open circuited, the following output resistance R will be set for the indicated RDC latch codes. Table 6. Codes and Corresponding R Resistance D (Dec.) R (Ω) Output State 255 9,96 Full Scale (R LS + R) 28 5,6 Midscale 99 LS 6 Zero Scale (iper Contact Resistance) Note that in the zero-scale condition a finite wiper resistance of 6 Ω is present. Care should be taken to limit the current flow between and in this state to a maximum pulse current of no more than 2 m. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDC between the wiper and terminal also produces a digitally controlled complementary resistance R. hen these terminals are used, the terminal can be opened. Setting the resistance value for R starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is 256 D R ( D) = R + R (2) 256 For R = kω and the terminal open circuited, the following output resistance R will be set for the indicated RDC latch codes. Table 7. Codes and Corresponding R Resistance D (Dec.) R (Ω) Output State Full Scale 28 5,6 Midscale 9,96 LS,6 Zero Scale Typical device to device matching is process lot dependent and may vary by up to ±3%. Since the resistance element is processed in thin film technology, the change in R with temperature has a very low 45 ppm/ C temperature coefficient. Rev. PrE 5/2/3 Page 9 of 3

10 D562 PROGRMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to- and wiper-to- proportional to the input voltage at -to-. Unlike the polarity of VDD to, which must be positive, voltage across -, -, and - can be at either polarity. If ignoring the effect of the wiper resistance for approximation, connecting the terminal to 5 V and the terminal to ground produces an output voltage at the wiper-to- starting at V up to LS less than 5 V. Each LS of voltage is equal to the voltage applied across terminal divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at V with respect to ground for any valid input voltage applied to terminals and is V D 256 D ( D) = V + V (3) For a more accurate calculation, which includes the effect of wiper resistance, V, can be found as V R ( D) R ( D) ( D) = V + V (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors R and R and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/ C. ESD PROTECTION Preliminary Technical Data ll digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 5 and Figure 6. This applies to the digital input pins SDI, CLK, and CS. 34Ω V SS LOGIC Figure 5. ESD Protection of Digital Pins,, V SS Figure 6. ESD Protection of Resistor Terminals TERMINL VOLTGE OPERTING RNGE The D562 VDD and power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals,, and that exceed VDD or will be clamped by the internal forward biased diodes (see Figure 7). V SS SPI COMPTILE 3-IRE SERIL US The D562 contains a 3-wire SPI compatible digital interface (SDI, CS, and CLK). The 9-bit serial word must be loaded MS first. The format of the word is shown in Table 5. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. hen CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 2). The data setup and data hold times in the specification table determine the valid timing requirements. The D562 uses an 9-bit serial input data register word that is transferred to the internal RDC register when the CS line returns to logic high. Extra MS bits are ignored. Figure 7. Maximum Terminal Voltages Set by VDD and VSS POER-UP SEQUENCE Since the ESD protection diodes limit the voltage compliance at terminals,, and (see Figure 7), it is important to power VDD/ before applying any voltage to terminals,, and ; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user s circuit. The ideal power-up sequence is in the following order:, VDD, digital inputs, and then V//. The relative order of powering V, V, V, and the digital inputs is not important as long as they are powered after VDD/. Rev. PrE 5/2/3 Page of 3

11 D562 LYOUT ND POER SUPPLY YPSSING It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. C3 + C µf. µ F D562 Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of. µf to. µf. Low ESR µf to µf tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 8). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. Figure 8. Power Supply ypassing Rev. PrE 5/2/3 Page of 3

12 D562 Preliminary Technical Data PIN CONFIGURTION ND FUNCTION DESCRIPTIONS PIN CONFIGURTION CS SDI 5 CLK Figure PIN FUNCTION DESCRIPTIONS Table 8. Pin Name Description Terminal. 2 Terminal Terminal. 4 Digital Ground. 5 VDD Positive Power Supply. 6 CLK Serial Clock Input. Positive edge triggered. 7 SDI Serial Data Input. 8 CS Chip Select Input, ctive Low. hen CS returns high, data will be loaded into the DC register Terminal. Terminal. Rev. PrE 5/2/3 Page 2 of 3

13 D562 OUTLINE DIMENSIONS 3. SC 3. SC SC PIN.5..5 SC.27.7 COPLNRITY.. MX SETING PLNE COMPLINT TO JEDEC STNDRDS MO-87 Figure 2. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters ORDERING GUIDE Model R (Ω) Temperature Package Description Package Option randing D562RM2.5-R2 2.5k 4 C to +25 C MSOP- RM- DQ D562RM2.5-RL7 2.5k 4 C to +25 C MSOP- RM- DQ D562RM-R2 k 4 C to +25 C MSOP- RM- DR D562RM-RL7 k 4 C to +25 C MSOP- RM- DR D562RM5-R2 5k 4 C to +25 C MSOP- RM- DS D562RM5-RL7 5k 4 C to +25 C MSOP- RM- DS D562RM-R2 k 4 C to +25 C MSOP- RM- DT D562RM-RL7 k 4 C to +25 C MSOP- RM- DT D562EVL See Note Evaluation oard The evaluation board is shipped with the kω R resistor option; however, the board is compatible with all available resistor value options. The D562 contains 2532 transistors. Die size: 3.7 mil 76.8 mil = 2,358 sq. mil. ESD CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 23 nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective companies. C3434 5/3() Rev. PrE 5/2/3 Page 3 of 3