64-Position Up/Down Control Digital Potentiometer AD5227

Transcription

1 64-Position Up/Down Control Digital Potentiometer FETURES 64-position digital potentiometer kω, 5 kω, kω end-to-end terminal resistance Simple up/down digital or manual configurable control Midscale preset Low potentiometer mode tempco = ppm/ C Low rheostat mode tempco = 35 ppm/ C Ultralow power, IDD =.4 μ typ and 3 μ max Fast adjustment time, ts = μs Chip select enable multiple device operation Low operating voltage, 2.7 V to 5.5 V utomotive temperature range, 4 C to +5 C Compact thin SOT-23-8 (2.9 mm 3 mm) Pb-free package FUNCTIONL LOCK DIGRM U/D 6-IT UP/DON CONTROL LOGIC POR MIDSCLE Figure. IPER REGISTER PPLICTIONS Mechanical potentiometer and trimmer replacements LCD backlight, contrast, and brightness controls Portable electronics level adjustment Programmable power supply Digital trimmer replacements utomatic closed-loop control GENERL DESCRIPTION The is nalog Devices latest 64-step up/down control digital potentiometer. This device performs the same electronic adjustment function as a 5 V potentiometer or variable resistor. Its simple 3-wire up/down interface allows manual switching or high speed digital control. The presets to midscale at power-up. hen is enabled, the devices changes step at every clock pulse. The direction is determined by the state of the U/D pin (see Table ). The interface is simple to activate by any host controller, discrete logic, or manually with a rotary encoder or pushbuttons. The s 64-step resolution, small footprint, and simple interface enable it to replace mechanical potentiometers and trimmers with typically 6 improved resolution, solid-state reliability, and design layout flexibility, resulting in a considerable cost savings in end users systems. The is available in a compact thin SOT-23-8 (TSOT-8) Pb-free package. The part is guaranteed to operate over the automotive temperature range of 4 C to +5 C. Users who consider EEMEM potentiometers should refer to some recommendations in the pplications section. Table. Truth Table U/D Operation R Decrement R Increment X X No Operation R increments if R decrements and vice versa. The terms digital potentiometer and RDC are used interchangeably. Rev. Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology ay, P.O. ox 96, Norwood, M , U.S.. Tel: Fax: nalog Devices, Inc. ll rights reserved.

2 TLE OF CONTENTS Electrical Characteristics... 3 Interface Timing Diagrams... 4 bsolute Maximum Ratings... 5 ESD Caution... 5 Pin Configuration and Function Descriptions... 6 Typical Performance Characteristics... 7 Theory of Operation... Programming the Digital Potentiometers... Digital Interface... Terminal Voltage Operation Range... Power-Up and Power-Down Sequences... pplications... 2 Manual Control with Toggle and Pushbutton Switches... 2 Manual Control with Rotary Encoder... 2 djustable LED Driver... 2 djustable Current Source for LED Driver... 2 djustable High Power LED Driver... 3 utomatic LCD Panel acklight Control it Controller... 3 Constant ias with Supply to Retain Resistance Setting... 4 Outline Dimensions... 5 Ordering Guide... 5 Layout and Power Supply iasing... REVISION HISTORY 5/9 Rev. to Rev. Changes to Table 2 3 4/9 Rev. to Rev. Changes to Table 2 3 Changes to Ordering Guide 5 3/4 Revision : Initial Version Rev. Page 2 of 6

3 ELECTRICL CHRCTERISTI kω, 5 kω, kω versions: VDD = 3 V ± % or 5 V ± %, V = VDD, V = V, 4 C < T < +5 C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit DC CHRCTERISTI RHEOSTT MODE Resistor Differential Nonlinearity 2 R-DNL R, = no connect.5 ± LS Resistor Integral Nonlinearity 2 R-INL R, = no connect ±.3 + LS Nominal Resistor Tolerance 3 R/R 2 +2 % Resistance Temperature Coefficient ( R/R)/ T 6 35 ppm/ C iper Resistance R VDD = 2.7 V 25 Ω VDD = 2.8 V to 5.5 V 5 2 Ω DC CHRCTERISTI POTENTIOMETER DIVIDER MODE Resolution N 6 its Integral Nonlinearity 3 INL ±. + LS Differential Nonlinearity 3, 4 DNL.5 ±. +.5 LS Voltage Divider Temperature Coefficient ( V/V)/ T 6 Midscale 5 ppm/ C Full-Scale Error VFSE +3 steps from midscale.2.5 LS 4 C < T < +6 C,.5 LS VDD = 2.8 V to 5.5 V Zero-Scale Error VZSE 32 steps from midscale.5.2 LS 4 C < T < +6 C,.5 LS VDD = 2.8 V to 5.5 V RESISTOR TERMINLS Voltage Range 5 V,, ith respect to VDD V Capacitance, 6 C, f = MHz, measured to 4 pf Capacitance 6 C f = MHz, measured to 5 pf Common-Mode Leakage ICM V = V = V n DIGITL INPUTS (,, U/D) Input Logic High VIH V Input Logic Low VIL.8 V Input Current II VIN = V or 5 V ± μ Input Capacitance 6 CI 5 pf POER SUPPLIES Power Supply Range VDD V Supply Current IDD VIH = 5 V or VIL = V,.4 3 μ VDD = 5 V Power Dissipation 7 PDISS VIH = 5 V or VIL = V, 7 μ VDD = 5 V Power Supply Sensitivity PSSR VDD = 5 V ± %..5 %/% 6, 8, 9 DYNMIC CHRCTERISTI andwidth 3 d _ k R = kω, midscale 46 khz _5 k R = 5 kω, midscale khz _ k R = kω, midscale 5 khz Total Harmonic Distortion THD V = V rms, R = kω,.5 % V = V dc, f = khz djustment Settling Time ts V = 5 V ± LS error band, V =, measured at μs Resistor Noise Voltage en_ R = 5 kω, f = khz 4 nv/ Hz Footnotes on the next page. V Rev. Page 3 of 6

4 Parameter Symbol Conditions Min Typ Max Unit INTERFCE TIMING CHRCTERISTI (applies to all parts 6, ) Clock Frequency f 5 MHz Input Clock Pulse idth tch, tcl Clock level high or low ns to Setup Time ts ns Rise to Hold Time th ns U/D to Clock Fall Setup Time tuds ns Typicals represent average readings at 25 C, VDD = 5 V. 2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 NL and DNL are measured at V with the RDC configured as a potentiometer divider similar to a voltage output D/ converter. V = VDD and V = V. 4 DNL specification limits of ± LS maximum are guaranteed monotonic operating conditions. 5 Resistor Terminals,, have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. 8 andwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 ll dynamic characteristics use VDD = V. ll input control voltages are specified with tr = tf = ns (% to 9% of VDD) and timed from a voltage level of.6 V. Switching characteristics are measured using VDD = 5 V. INTERFCE TIMING DIGRMS = LO U/D = HIGH R Figure 2. Increment R = LO U/D = R Figure 3. Decrement R t S t CH t H t CL U/D t UDS t S R Figure 4. Detailed Timing Diagram (Only R Decrement Shown) Rev. Page 4 of 6

5 SOLUTE MXIMUM RTINGS Table 3. Parameter VDD to V, V, V to Digital Input Voltage to (,, U/D) Rating.3 V, +7 V V, VDD V, VDD Maximum Current I, I Pulsed ±2 m I Continuous (R 5 kω, open) ± m I Continuous (R 5 kω, open) ± m I Continuous (R = kω/5 kω/ kω) ±5 μ/ ± μ/±5 μ Operating Temperature Range 4 C to +5 C Maximum Junction Temperature (TJmax) 5 C Storage Temperature 65 C to +5 C Lead Temperature (Soldering, s 3 s) 245 C Thermal Resistance 2 θj 23 C/ Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum terminal current is bounded by the maximum applied voltage across any two of the,, and terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2 Package power dissipation = (TJmax T) / θj. ESD CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. Page 5 of 6

6 PIN CONFIGURTION ND FUNCTION DESCRIPTIONS U/D TOP VIE (Not to Scale) Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined by the state of the U/D pin. is a negative-edge trigger. Logic high signal can be higher than VDD, but lower than 5.5 V. 2 U/D Up/Down Selections. Logic selects up and Logic selects down. U can be higher than VDD, but lower than 5.5 V. 3 Resistor Terminal. V VDD. 4 Common Ground. 5 iper Terminal. V VDD. 6 Resistor Terminal. V VDD. 7 Chip Select. ctive Low. Logic high signal can be higher than VDD, but lower than 5.5 V. 8 VDD Positive Power Supply, 2.7 V to 5.5 V. Rev. Page 6 of 6

7 TYPICL PERFORMNCE CHRCTERISTI RHEOSTT MODE INL (LS) C +25 C +85 C +5 C CODE (Decimal) Figure 6. R-INL vs. Code vs. Temperature, VDD = 5 V POTENTIOMETER MODE DNL (LS) C +25 C +85 C +5 C CODE (Decimal) Figure 9. DNL vs. Code vs. Temperature, VDD = 5 V RHEOSTT MODE DNL (LS) C +25 C +85 C +5 C FSE (LS) = 2.7V CODE (Decimal) TEMPERTURE ( C) Figure 7. R-DNL vs. Code vs. Temperature, VDD = 5 V Figure. Full-Scale Error vs. Temperature POTENTIOMETER MODE INL (LS) C +25 C +85 C +5 C CODE (Decimal) ZSE (LS)..9.8 = 2.7V TEMPERTURE ( C) Figure 8. INL vs. Code, VDD = 5 V Figure. Zero-Scale Error vs. Temperature Rev. Page 7 of 6

8 SUPPLY CURRENT (μ) TEMPERTURE ( C) RHEOSTT MODE TEMPCO (ppm/ C) kω 5kΩ kω CODE (Decimal) Figure 2. Supply Current vs. Temperature Figure 5. Rheostat Mode Tempco ΔR/ΔT vs. Code NOMINL RESISTNCE, R (kω) R = kω R = 5kΩ R = kω TEMPERTURE ( C) POTENTIOMETER MODE TEMPCO (ppm/ C) kω 5kΩ kω CODE (Decimal) Figure 3. Nominal Resistance vs. Temperature Figure 6. Potentiometer Mode Tempco ΔR/ΔT vs. Code IPER RESISTNCE, R (Ω) = 2.7V d REF LEVEL d /DIV 6.d 32 STEPS 6 STEPS 8 STEPS 4 STEPS 2 STEPS STEP MRKER Hz MG (/R) 8.957d T = 25 C V = 5mV rms TEMPERTURE ( C) k k k M STRT.Hz STOP.Hz Figure 4. iper Resistance vs. Temperature Figure 7. Gain vs. Frequency vs. Code, R = kω Rev. Page 8 of 6

9 REF LEVEL d 6 6 /DIV 6.d 32 STEPS MRKER Hz MG (/R) 9.6d T = 25 C V = 5mV rms STEPS d STEPS 4 STEPS 2 STEPS STEP I DD (μ) 5 = k k k M STRT.Hz STOP.Hz = 3V k k M M FREQUENCY (Hz) Figure 8. Gain vs. Frequency vs. Code, R = 5 kω Figure 2. IDD vs. Frequency d REF LEVEL d /DIV 6.d 32 STEPS 6 STEPS 8 STEPS 4 STEPS 2 STEPS STEP MRKER Hz MG (/R) 9.39d T = 25 C V = 5mV rms THEORETICL I _MX (m) R = 5kΩ R = kω = OPEN T = 25 C k k k M STRT.Hz STOP.Hz R = kω CODE (Decimal) Figure 9. Gain vs. Frequency vs. Code, R = kω Figure 22. Maximum I vs. Code STEP = MIDSCLE, V =, V = V V = V V 2 PSRR (d) 4 = 3V DC ±% p-p C 2 STEP N STEP N+ = V = V = V V = DC ±% p-p C 6 k k k M FREQUENCY (Hz) Figure 2. PSRR CH 2.V CH2 5.mV M 4ns CH2 6.mV T.s Figure 23. Step Change Settling Time Rev. Page 9 of 6

10 THEORY OF OPERTION The is a 64-position 3-terminal digitally controlled potentiometer device. It presets to a midscale at system poweron. hen is enabled, changing the resistance settings is achieved by clocking the pin. It is negative-edge triggered, and the direction of stepping is determined by the state of the U/D input. hen the wiper reaches the maximum or the minimum setting, additional pulses do not change the wiper setting. The end-to-end resistance, R, has 64 contact points accessed by the wiper terminal, plus the terminal contact, assuming that R is used (see Figure 25). Clocking the input steps, R by one step. The direction is determined by the state of U/D pin. The change of R can be determined by the number of clock pulses, provided that the has not reached its maximum or minimum scale. ΔR can, therefore, be approximated as ΔR R = ± CP + R 64 () U/D 6-IT UP/DON CONTROL LOGIC POR MIDSCLE IPER REGISTER Figure 24. Functional lock Diagram where: CP is the number of clock pulses. R is the end-to-end resistance. R is the wiper resistance contributed by the on-resistance of the internal switch. Since in the lowest end of the resistor string a finite wiper resistance is present, care should be taken to limit the current flow between and in this state to a maximum pulse current of no more than 2 m. Otherwise, degradation or possible destruction of the internal switches can occur. D D D2 D3 D4 D5 R S R S R S Similar to the mechanical potentiometer, the resistance of the RDC between the iper and Terminal also produces a digitally controlled complementary resistance, R. hen these terminals are used, the terminal can be opened or shorted to. Similarly, ΔR can be approximated as RDC UP/DON CTRL ND DECODE R ΔR R = ± ( 64 CP) + R (2) 64 R S R S = R /64 Figure 25. Equivalent RDC Circuit PROGRMMING THE DIGITL POTENTIOMETERS Rheostat Operation If only the -to- or -to- terminals are used as variable resistors, the unused terminal can be opened or shorted with. This operation is called rheostat mode and is shown in Figure Equations and 2 do not apply when CP =. The typical distribution of the resistance tolerance from device to device is process lot dependent. It is possible to have ±2% tolerance. Potentiometer Mode Operation If all three terminals are used, the operation is called potentiometer mode. The most common configuration is the voltage divider operation as shown in Figure 27. Figure 26. Rheostat Mode Configuration V I V C Figure 27. Potentiometer Mode Configuration Rev. Page of 6

11 The change of V is known provided that the has not reached the maximum or minimum scale. If one ignores the effect of the wiper resistance, the transfer functions can be simplified as CP V = + V 64 Δ U/D = (3) CP V = V 64 Δ U/D = (4) Unlike rheostat mode operation where the absolute tolerance is high, potentiometer mode operation yields an almost ratiometric function of CP/64 with a relatively small error contributed by the R term. The tolerance effect is, therefore, almost canceled. lthough the thin film step resistor, RS, and CMOS switches resistance, R, have very different temperature coefficients, the ratiometric adjustment also reduces the overall temperature coefficient to 5 ppm/ C except at low value codes where R dominates. Potentiometer mode operation includes an op amp gain configuration among others. The,, and terminals can be input or output terminals and have no polarity constraint provided that V, V, and V do not exceed VDD-to-. DIGITL INTERFCE The contains a 3-wire serial input interface. The three inputs are clock (), chip select (), and up/down control (U/D). These inputs can be controlled digitally for optimum speed and flexibility hen is pulled low, a clock pulse increments or decrements the up/down counter. The direction is determined by the state of the U/D pin. hen a specific state of the U/D remains, the device continues to change in the same direction under consecutive clocks until it comes to the end of the resistance setting. ll digital inputs,,, and U/D pins, are protected with a series input resistor and a parallel Zener ESD structure as shown in Figure 28. operating voltages. Voltage present on Terminal,, or that exceeds VDD by more than.5 V is clamped by the diode and, therefore, elevates VDD. There is no polarity constraint between V, V, and V, but they cannot be higher than VDD-to-. POER-UP ND POER-DON SEQUENCES ecause of the ESD protection diodes, it is important to power on VDD before applying any voltage to Terminals,, and. Otherwise, the diodes are forward-biased such that VDD can be powered unintentionally and can affect the rest of the system circuit. Similarly, VDD should be powered down last. The ideal power-on sequence is in the following order:, VDD, V//, and digital inputs. Figure 29. Maximum Terminal Voltages Set by VDD and LYOUT ND POER SUPPLY ISING It is a good practice to use compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Low ESR (equivalent series resistance) μf to μf tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 3 illustrates the basic supply bypassing configuration for the. The ground pin of the is a digital ground reference that should be joined to the common ground at a single point to minimize the digital ground bounce kω LOGIC Figure 28. Equivalent ESD Protection Digital Pins TERMINL VOLTGE OPERTION RNGE The is designed with internal ESD protection diodes (Figure 29), but the diodes also set the boundary of the terminal C2 μf C.μF Figure 3. Power Supply ypassing Rev. Page of 6

12 PPLICTIONS MNUL CONTROL ITH TOGGLE ND PUSHUTTON SITCHES The s simple interface allows it to be used with mechanical switches for simple manual operation. The states of the and U/D can be selected by toggle switches and the input can be controlled by a pushbutton switch. ecause of the numerous bounces due to contact closure, the pushbutton switch should be debounced by flip-flops or by the DM82 as shown in Figure 3. UP/DON INCREMENT V CC MR RESET DM82 U/D Figure 3. Manual Push utton Up/Down Control MNUL CONTROL ITH ROTRY ENCODER Figure 32 shows another way of using to emulate mechanical potentiometer in a rotary knob operation. The rotary encoder U has a C ground terminal and two out-ofphase signals, and. hen U is turned clockwise, a pulse generated from the terminal leads a pulse generated from the terminal and vice versa. Signals and of U pass through a quadrature decoder U2 that translates the phase difference between and of U into compatible inputs for U3. Therefore, when leads (clockwise), U2 provides the with a logic high U/D signal, and vice versa. U2 also filters noise, jitter, and other transients as well as debouncing the contact bounces generated by U. R kω U ROTRY ENCODER C RECT-VY2-EF2 R2 kω R3 kω QUDRTURE DECODER U2 LS784 RIS 8 U/D 7 VSS X4/X 6 5 Figure 32. Manual Rotary Control DIGITL POTENTIOMETER U3 8 2 U/D DJUSTLE LED DRIVER The can be used in many electronics-level adjustments such as LED drivers for LCD panel backlight control. Figure 33 shows an adjustable LED driver. The sets the voltage across the white LED D for the brightness control. Since U2 handles up to 25 m, a typical white LED with VF of 3.5 V requires a resistor, R, to limit the U2 current. This circuit is simple but not power-efficient, therefore the U2 shutdown pin can be toggled with a PM signal to conserve power. C μf C2.μF U/D U kω V+ U2 D859 + V C3.μF SD PM R 6Ω Figure 33. Low Cost djustable LED Driver HITE LED D DJUSTLE CURRENT SOURCE FOR LED DRIVER Since LED brightness is a function of current rather than forward voltage, an adjustable current source is preferred over a voltage source as shown in Figure 34. PM V IN V OUT U DP3333 RM-.5 SD U2 kω U/D R 48kΩ V+ U3 D859 V + R SET.Ω Figure 34. djustable Current Source for LED Driver VL D ID The load current can be found as the V of the divided by RSET. V I D = (5) RSET Rev. Page 2 of 6

13 The U DP3333RM-.5 is a.5 V LDO that is lifted above or lowered below V. hen V of the is at minimum, there is no current through D, so the pin of U would be at.5 V if U3 were biased with the dual supplies. s a result, some of the U2 low resistance steps have no effect on the output until the U pin is lifted above V. hen V of the is at its maximum, VOUT becomes VL + V, so the U supply voltage must be biased with adequate headroom. Similarly, a PM signal can be applied at the U shutdown pin for power efficiency. This circuit works well for a single LED. DJUSTLE HIGH POER LED DRIVER Figure 35 shows a circuit that can drive three to four high power LEDs. DP6 is an adjustable boost regulator that provides the voltage headroom and current for the LEDs. The and the op amp form an average gain of 2 feedback network that servos the RSET voltage and DP6 s F pin.2 V band gap reference voltage. s the loop is set, the voltage across RSET is regulated around. V and adjusted by the digital potentiometer. I V RSET LED = (6) RSET RSET should be small enough to conserve power but large enough to limit maximum LED current. R3 should also be used in parallel with to limit the LED current within an achievable range. wider current adjustment range is possible by lowering the R2 to R ratio, as well as changing R3 accordingly. C2 μf R4 3.5kΩ L SLF625-MR D MR52LT PM.2V R C kω C C 39pF C8.μF U R2.kΩ IN U2 DP6 SD S F COMP SS RT C SS nf V+ U3 + D854 V L μf D U kω R3 2Ω C3 μf R SET.25Ω R Ω Figure 35. djustable Current Source for LEDs in Series D2 D3 D4 V OUT UTOMTIC LCD PNEL CKLIGHT CONTROL ith the addition of a photocell sensor, an automatic brightness control can be achieved. s shown in Figure 36, the resistance of the photocell changes linearly but inversely with the light output. The brighter the light output, the lower the photocell resistance and vice versa. The sets the voltage level that is gained up by U2 to drive N to a desirable brightness. ith the photocell acting as the variable feedback resistor, the change in the light output changes the R2 resistance, therefore causing U2 to drive N accordingly to regulate the output. This simple low cost implementation of the LED controller can compensate for the temperature and aging effects typically found in high power LEDs. Similarly, for power efficiency, a PM signal can be applied at the gate of N2 to switch the LED on and off without any noticeable effect. C μf C2.μF U/D U kω R kω PHOTOCELL V+ U2 D859 + C3.μF SD V PM Figure 36. utomatic LCD Panel acklight Control R2 N D HITE LED 2N72 6-IT CONTROLLER The can form a simple 6-bit controller with a clock generator, a comparator, and some output components. Figure 37 shows a generic 6-bit controller with a comparator that first compares the sampling output with the reference level and outputs either a high or low level to the U/D pin. The then changes step at every clock cycle in the direction indicated by the U/D state. lthough this circuit is not as elegant as the one shown in Figure 36, it is self-contained, very easy to design, and can adapt to various applications. U/D U2 COMPRTOR + U SMPLING_OUTPUT REF U3 D853 + OP MP Figure it Controller OUTPUT Rev. Page 3 of 6

14 CONSTNT IS ITH SUPPLY TO RETIN RESISTNCE SETTING Users who consider EEMEM potentiometers but cannot justify the additional cost and programming for their designs can consider constantly biasing the with the supply to retain the resistance setting as shown in Figure 38. The is designed specifically with low power to allow power conservation even in battery-operated systems. s shown in Figure 39, a similar low power digital potentiometer is biased with a 3.4 V 45 m/hour Li-Ion cell phone battery. The measurement shows that the device drains negligible power. Constantly biasing the potentiometer is a practical approach because most portable devices do not require detachable batteries for charging. lthough the resistance setting of the is lost when the battery needs to be replaced, this event occurs so infrequently that the inconvenience is minimal for most applications. TTERY VOLTGE (V) 3.5 T = 25 C DYS Figure 39. attery Consumption Measurement S + U U2 U3 TTERY OR SYSTEM POER COMPONENT X COMPONENT Y Figure 38. Constant ias for Resistance Retention Rev. Page 4 of 6

15 OUTLINE DIMENSIONS 2.9 SC SC 2.8 SC PIN INDICTOR * SC.65 SC. MX *. MX.2.8 SETING PLNE *COMPLINT TO JEDEC STNDRDS MO-93- ITH THE EXCEPTION OF PCKGE HEIGHT ND THICKNESS. Figure 4. 8-Lead Thin Small Outline Transistor Package [TSOT] (UJ-8) Dimensions shown in millimeters ORDERING GUIDE Model R (kω) Temperature Range Package Description Package Option Ordering Quantity randing UJZ-RL7 2 4 C to +5 C 8-Lead TSOT UJ-8 3 D3G UJZ-R2 2 4 C to +5 C 8-Lead TSOT UJ-8 25 D3G UJZ5-RL C to +5 C 8-Lead TSOT UJ-8 3 D3H UJZ5-R C to +5 C 8-Lead TSOT UJ-8 25 D3H UJZ-RL7 2 4 C to +5 C 8-Lead TSOT UJ-8 3 D3J UJZ-R2 2 4 C to +5 C 8-Lead TSOT UJ-8 25 D3J EVL Evaluation oard The end-to-end resistance R is available in kω, 5 kω, and kω versions. The final three characters of the part number determine the nominal resistance value, for example, kω =. 2 Z = RoHS Compliant Part. Rev. Page 5 of 6

16 NOTES nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D449 5/9() Rev. Page 6 of 6