15 V Operation Digital Potentiometer AD7376*

Transcription

1 a FETURES 128 Position Potentiometer Replacement 1 k, 5 k, 1 k, 1 M Power Shutdown: Less than 1 3-ire SPI Compatible Serial Data Input +5 V to +3 V Single Supply Operation 5 V to 15 V Dual Supply Operation Midscale Preset PPLICTIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset djustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply djustment GENERL DESCRIPTION The D7376 provides a single channel, 128-position digitallycontrolled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment applications where a combination of high voltage with a choice between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The D7376 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the terminal and the wiper or the terminal and the wiper. The fixed to terminal resistance of 1 kω, 5 kω, 1 kω or 1 MΩ has a nominal temperature coefficient of 3 ppm/ C. The VR has its own VR latch which holds its programmed resistance value. The VR latch is updated from an internal serial-toparallel shift register which is loaded from a standard 3-wire serial-input digital interface. Seven data bits make up the data word clocked into the serial data input register (SDI). Only the last seven bits of the data word loaded are transferred into the 7-bit VR latch when the CS strobe is returned to logic high. serial data output pin (SDO) at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to the midscale position by loading 4 H into the VR latch. The SHDN pin forces the resistor *Patent Number: SDO SDI CLK CS 15 V Operation Digital Potentiometer D7376* FUNCTIONL LOCK DIGRM D7376 Q 7-IT SERIL REGISTER D GND CK 7 7-IT LTCH R RS 7 SHDN SHDN to an end-to-end open circuit condition on the terminal and shorts the wiper to the terminal, achieving a microwatt power shutdown state. hen shutdown is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown as long as power to is not removed. The digital interface is still active in shutdown so that code changes can be made that will produce a new wiper position when the device is taken out of shutdown. The D7376 is available in both surface mount (SOL-16) and the 14-lead plastic DIP package. For ultracompact solutions selected models are available in the thin TSSOP package. ll parts are guaranteed to operate over the extended industrial temperature range of 4 C to +85 C. For operation at lower supply voltages (+3 V to +5 V), see the D84/D842/ D843 products. SDI (DT IN) SDO (DT OUT) 1 CLK t CSH V OUT CS V t CSS D X D' X t CH t DS t CL D' X D X t DH t CSH t PD_MX t CS1 1 LS ERROR ND V SS t CS 1 LS Figure 1. Detail Timing Diagram The last seven data bits clocked into the serial input register will be transferred to the VR 7-bit latch when CS returns to logic high. Extra data bits are ignored. t S REV. Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. One Technology ay, P.O. ox 916, Norwood, M , U.S.. Tel: 781/ orld ide eb Site: Fax: 781/ nalog Devices, Inc., 1997

2 D7376 SPECIFICTIONS ( /V SS = 15 V 1% or 5 V 1%, V = +, V = V SS / V, 4 C < T < +85 C ELECTRICL CHRCTERISTICS unless otherwise noted.) Parameter Symbol Conditions Min Typ 1 Max Units DC CHRCTERISTICS RHEOSTT MODE (Specifications pply to ll VRs) Resistor Differential NL 2 R-DNL R, V = NC 1 ± LS Resistor Nonlinearity 2 R-INL R, V = NC 1 ±.5 +1 LS Nominal Resistor Tolerance R T = +25 C 3 3 % Resistance Temperature Coefficient R / T V =, iper = No Connect 3 ppm/ C iper Resistance R I = ± 15 V/R NOMINL 12 2 Ω iper Resistance R I = ±5 V/R NOMINL 2 Ω DC CHRCTERISTICS POTENTIOMETER DIVIDER MODE (Specifications pply to ll VRs) Resolution N 7 its Integral Nonlinearity 3 INL 1 ±.5 +1 LS Differential Nonlinearity 3 DNL 1 ±.1 +1 LS Voltage Divider Temperature Coefficient V / T Code = 4 H 5 ppm/ C Full-Scale Error V FSE Code = 7F H LS Zero-Scale Error V ZSE Code = H LS RESISTOR TERMINLS Voltage Range 4 V,, V SS V Capacitance 5, C, f = 1 MHz, Measured to GND, Code = 4 H 45 pf Capacitance 5 C f = 1 MHz, Measured to GND, Code = 4 H 6 pf Shutdown Supply Current 6 I _SD V =, V = V, SHDN =.1 1 µ Shutdown iper Resistance R _SD V =, V = V, SHDN =, = +15 V 17 4 Ω Common-Mode Leakage I CM V = V = V 1 n DIGITL INPUTS ND OUTPUTS Input Logic High V IH = +5 V or +15 V 2.4 V Input Logic Low V IL = +5 V or +15 V.8 V Output Logic High V OH R L = 2.2 kω to +5 V 4.9 V Output Logic Low 7 V OL I OL = 1.6 m, V LOGIC = +5 V, = +15 V.4 V Input Current I IL V IN = V or +15 V ± 1 µ Input Capacitance 5 C IL 5 pf POER SUPPLIES Power Supply Range /V SS Dual Supply Range ± 4.5 ±16.5 V Power Supply Range Single Supply Range, V SS = V Supply Current I DD V IH = +5 V or V IL = V, = +5 V.1.1 m Supply Current I DD V IH = +5 V or V IL = V, = +15 V.75 2 m Supply Current I SS V IH = +5 V or V IL = V, V SS = 5 V or 15 V.2.1 m Power Dissipation 8 P DISS V IH = +5 V or V IL = V, = +15 V, V SS = 15 V 11 3 m Power Supply Sensitivity PSS = +5 V ± 1%, or V SS = 5 V ± 1%.5.15 %/% PSS = +15 V ± 1% or V SS = 15 V ± 1%.1.2 %/% 5, 9, 1 DYNMIC CHRCTERISTICS andwidth 3 d _1K R = 1 kω, Code = 4 H 52 khz andwidth 3 d _5K R = 5 kω, Code = 4 H 125 khz andwidth 3 d _1K R = 1 kω, Code = 4 H 6 khz Total Harmonic Distortion THD V = 1 V rms, V = V, f = 1 khz.5 % V Settling Time t S V = 1 V, V = V, ±1 LS Error and 4 µs Resistor Noise Voltage e N_ R = 25 kω, f = 1 khz, RS = 14 nv Hz INTERFCE TIMING CHRCTERISTICS (pplies to ll Parts [Notes 5, 11]) Input Clock Pulsewidth t CH, t CL Clock Level High or Low 12 ns Data Setup Time t DS 3 ns Data Hold Time t DH 2 ns CLK to SDO Propagation Delay 12 t PD R L = 2.2 kω, C L < 2 pf 1 1 ns CS Setup Time t CSS 12 ns CS High Pulsewidth t CS 15 ns Reset Pulsewidth t RS 12 ns CLK Rise to CS Rise Hold Time t CSH 12 ns CS Rise to Clock Rise Setup t CS1 12 ns 2 REV.

3 D7376 NOTES 11 Typicals represent average readings at +25 C, = +15 V, and V SS = 15 V. 12 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit. 13 INL and DNL are measured at V with the RDC configured as a potentiometer divider similar to a voltage output D/ converter. V = and V = V. DNL specification limits of ±1 LS maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit. 14 Resistor terminals,, have no limitations on polarity with respect to each other. 15 Guaranteed by design and not subject to production test. 16 Measured at the terminal. terminal is open circuit in shutdown mode. 17 I OL = 2 µ for the 5 kω version operating at = +5 V. 18 P DISS is calculated from (I DD ). CMOS logic level inputs result in minimum power dissipation. 19 andwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 1 ll dynamic characteristics use = +15 V and V SS = 15 V. 11 See timing diagram for location of measured values. ll input control voltages are specified with t R = t F = 1 ns (1% to 9% of ) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both = +5 V or +15 V. 12 Propagation delay depends on value of, R L and C L see pplications section. Specifications subject to change without notice. SOLUTE MXIMUM RTINGS (T = +25 C, unless otherwise noted) to GND V, +3 V V SS to GND V, 16.5 V to V SS V, +44 V V, V, V to GND V SS, X X, X X, X X ±2 m Digital Input Voltages to GND V, +.3 V Digital Output Voltage to GND V, +3 V Operating Temperature Range C to +85 C Maximum Junction Temperature (T J MX) C Storage Temperature C to +15 C Lead Temperature (Soldering, 1 sec) C Package Power Dissipation (T J MX T )/θ J Thermal Resistance θ J P-DIP (N-14) C/ SOIC (SOL-16) C/ TSSOP C/ ORDERING GUIDE PDIP & TSSOP V SS 3 GND 4 CS 5 RS 6 CLK 7 D7376 TOP VIE (Not to Scale) NC = NO CONNECT PIN CONFIGURTIONS NC SDO 1 SHDN 9 SDI 8 NC 1 2 V SS 3 GND 4 CS 5 RS 6 Temperature Package Package Model k Range Description Options D7376N1 1 4 C to +85 C PDIP-14 N-14 D7376R1 1 4 C to +85 C SOL-16 R-16 D7376RU1 1 4 C to +85 C TSSOP-14 RU-14 D7376N5 5 4 C to +85 C PDIP-14 N-14 D7376R5 5 4 C to +85 C SOL-16 R-16 D7376RU5 5 4 C to +85 C TSSOP-14 RU-14 D7376N1 1 4 C to +85 C PDIP-14 N-14 D7376R1 1 4 C to +85 C SOL-16 R-16 D7376RU1 1 4 C to +85 C TSSOP-14 RU-14 D7376N1M 1, 4 C to +85 C PDIP-14 N-14 D7376R1M 1, 4 C to +85 C SOL-16 R-16 D7376RU1M 1, 4 C to +85 C TSSOP-14 RU-14 Die Size: 11.6 mil mil, 2.58 mm 3.24 mm Number Transistors: 84 CLK NC 7 8 SOL-16 D7376 TOP VIE (Not to Scale) NC = NO CONNECT NC SDO 12 SHDN 11 SDI 1 NC 9 NC CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough the D7376 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. RNING! ESD SENSITIVE DEVICE REV. 3

4 D7376 Typical Performance Characteristics PERCENT OF NOMINL END-TO-END RESISTNCE % R R R R-INL ERROR LS T = +85 C T = 55 C T = +25 C V = 2.5V V = V R = 5k R-DNL ERROR LS T = +25 C T = +85 C T = 55 C R = 5k Figure 2. iper To End Terminal Percent Resistance vs. Code Figure 3. Resistance Step Position Nonlinearity Error vs. Code Figure 4. Relative Resistance Step Change from Ideal vs. Code NOMINL END-TO-END RESISTNCE k R = 5k NOMINL TEMPERTURE C Figure 5. Nominal Resistance vs. Temperature V V H 1H 2 H 4 H CODE = 7 H T = +25 C R = 5k 7F H I m Figure 6. Resistance Linearity vs. Conduction Current R_INL LS I w = 1, T = +25 C DT = 4 H SUPPLY VOLTGE ( - V SS ) Volts Figure 7. Resistance Nonlinearity Error vs. Supply Voltage INL LS V = 2.5V V = V CODE = 4 H R = 5k SUPPLY VOLTGE ( - V SS ) Volts Figure 8. Potentiometer Divider Nonlinearity Error vs. Supply Voltage V / T POTENTIOMETER MODE TEMPCO ppm/ C V = +2.5V V = V 55 C < T < +85 C R = 5k Figure 9. V / T Potentiometer Mode Tempco IPER CONTCT RESISTNCE R = 5k = +5V V SS = 5V = +5V V SS = V TEMPERTURE C Figure 1. iper Contact Resistance vs. Temperature 4 REV.

5 D7376 INL NONLINERITY ERROR LS V = +2.5V V = V R = 5k T = +25 C T = 55 C T = +85 C DNL LS V = +2.5V V = V R = 5k RHEOSTT MODE TEMPCO ppm/ C R = 5k Figure 11. Potentiometer Divider Nonlinearity Error vs. Code Figure 12. Potentiometer Divider Differential Nonlinearity Error vs. Code Figure 13. R / T Rheostat Mode Tempco GIN d k CODE = 7F H CODE = 4 H CODE = 2 H CODE = 1 H CODE = 8 H CODE = 4 H CODE = 2 H CODE = 1 H R = 1k CODE = H OP275 V MPL = 5mVrms 1k 1k 1M Figure kω Gain vs. Frequency vs. Code GIN d CODE = 7F H CODE = 4 H CODE = 2 H CODE = 1 H CODE = 8 H CODE = 4 H CODE = 2 H R = 1M CODE = 1 H V MPL = 5mVrms OP275 R = 1M 1k 1k 1k Figure MΩ Gain vs. Frequency vs. Code 5m Lw s V SS = 15V CODE = 3F H 4 H 3F H V = 2.5V V = V f = 1 khz 5 S/DIV H O 5 s Figure 16. Midscale Transition Glitch GIN d CODE = 7F H R = 5k 6 CODE = 4 H 128kHz 2 H 12 1 H 18 8 H 24 MP = 5mV V 4 H 3 DD = +15V 2 H 36 R L = 1M 1 H OP k 1k 1k 1M Figure kω Gain vs. Frequency vs. Code V DLY CODE = 3F H V = 12V V = V f = 1 MHz 27.8 s 5V 5V Lw H O 2 s 2 S/DIV Figure 18. Large Signal Settling Time THD % NON-INVERTING MODE TEST CKT FIG 36 NON-INVERTING MODE TEST CKT FIG 35 V = 1V p p CODE = 4 H R = 5k 1 1k 1k 2k Figure 19. Total Harmonic Distortion Plus Noise vs. Frequency REV. 5

6 D7376 GIN d k CODE = 7F H 4H 2H 1H 8H 4H 2H 1H OP275 V MPL = 5mVrms R = 1k 1k 1k 1M Figure 2. 1 kω Gain vs. Frequency vs. Code GIN d k 24 5k 3 36 V MPL = 5mVrms 1k CODE = 4 H 42 R = 1M 48 OP k 1k 1k 1M Figure d andwidth vs. Nominal Resistance 2m V DLY Lw s H O2 s Figure 22. Clock Feedthrough GIN d.1 R = 1k.1 5k.2 1M.3 1k V MPL = 5mVrms CODE = 4 H.7.8 OP k 1k 1k 1M Figure 23. Gain Flatness vs Frequency vs. Nominal Resistance R PSRR d PSRR = +5V V SS = 5V 1% +PSRR 1% +PSRR = +5V 1% V SS = 5V PSRR 1% k 1k 1k Figure 24. Power Supply Rejection vs. Frequency RON 4 T = +25 C 35 = +5V V SS = 5V SEE FIGURE 38 TEST CIRCUIT V Volts 1 15 Figure 25. Incremental iper Contact Resistance vs. Common-Mode Voltage SUPPLY CURRENT m I V LOGIC = +5V I V LOGIC = V I V LOGIC = +15V I = +5V, V LOGIC = +.8V I = +5V, V LOGIC = +5V R = 5k TEMPERTURE C Figure 26. Supply Current (I DD, I SS ) vs. Temperature SHUTDON CURRENT TEMPERTURE C Figure 27. I _SD Shutdown Current vs. Temperature SUPPLY CURRENT m , V = +2.5V V = T = +25 C DT = 55 H DT = 3F H. 1k 1k 1k 1M 1M CLOCK Figure 28. I DD Supply Current vs. Input Clock Frequency 6 REV.

7 D I MS 3. INPUT LOGIC THRESHOLD VOLTGE Volts V = +5V V = V V SS = V V+ I = 1V/R NOMINL V V+ V MS R = V 2 - (V 1 + I [R R ]) I HERE V 1 = V MS HEN I = ND V 2 = V MS HEN I = 1/R Figure 33. iper Resistance Test Circuit SUPPLY VOLTGE ( ) Volts V Figure 29. Input Logic Threshold Voltage vs. Supply Voltage V+ V MS V+ = 1% OR V SS 1% PSRR (d) = 2LOG( VMS V+ PSS (%/%) = VMS% V+% ( Figure 34. Power Supply Sensitivity Test Circuit (PSS, PSRR) I DD 8 4 = +5V V SS = V OR 5V V LOGIC Figure 3. Supply Current (I DD ) vs. Logic Voltage +18V V IN OP275 V OUT 18V Figure 35. Inverting Programmable Gain Test Circuit PRMETRIC TEST CIRCUITS +18V V+ V+ = 1LS = V+/128 V MS V IN OP275 18V V OUT Figure 31. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) Figure 36. Noninverting Programmable Gain Test Circuit NO CONNECT I V IN +18V OP275 V OUT V MS 18V Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 37. Gain vs. Frequency Test Circuit REV. 7

8 D7376 I S.1V R S = I S CODE = OO H V SS TO.1V Figure 38. Incremental ON Resistance Test Circuit V SS GND NC NC Figure 39. Common-Mode Leakage Current Test Circuit OPERTION The D7376 provides a 128-position digitally-controlled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in a 7-bit serial data word into the SDI (Serial Data Input) pin, while CS is active low. hen CS returns high the last seven bits are transferred into the RDC latch setting the new wiper position. The exact timing requirements are shown in Figure 1. The D7376 resets to a midscale by asserting the RS pin, simplifying initial conditions at power-up. oth parts have a power shutdown SHDN pin which places the RDC in a zero power consumption state where terminal is open circuited and the wiper is connected to, resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained so that, returning to operational mode from power shutdown, the VR settings return to their previous resistance values. SHDN D6 D5 D4 D3 D2 D1 D RDC LTCH & DECODER R S R S R S R S I CM V CM R S = R NOMINL /128 PROGRMMING THE VRILE RESISTOR Rheostat Operation The nominal resistance of the RDC between terminals and are available with values of 1 kω, 5 kω, 1 kω and 1 MΩ. The final three characters of the part number determine the nominal resistance value, e.g., 1 kω = 1; 5 kω = 5; 1 kω = 1; 1 MΩ = 1M. The nominal resistance (R ) of the VR has 128 contact points accessed by the wiper terminal, plus the terminal contact. The 7-bit data word in the RDC latch is decoded to select one of the 128 possible settings. The wiper s first connection starts at the terminal for data H. This terminal connection has a wiper contact resistance of 12 Ω. The second connection (1 kω part) is the first tap point located at 198 Ω (= R [nominal resistance]/128 + R = 78 Ω + 12 Ω) for data 1 H. The third connection is the next tap point representing = 276 Ω for data 2 H. Each LS data value increase moves the wiper up the resistor ladder until the last tap point is reached at 141 Ω. The wiper does not directly connect to the terminal. See Figure 4 for a simplified diagram of the equivalent RDC circuit. The general transfer equation that determines the digitally programmed output resistance between and is: R (D) = (D)/128 R + R (1) where D is the data contained in the 7-bit VR latch, and R is the nominal end-to-end resistance. For example, when V = V and terminal is open circuit, the following output resistance values will be set for the following VR latch codes (applies to the 1 kω potentiometer). Table I. D R (DEC) ( ) Output State Full-Scale Midscale (RS = Condition) LS 198 Zero-Scale (iper Contact Resistance) Note that in the zero-scale condition a finite wiper resistance of 12 Ω is present. Care should be taken to limit the current flow between and in this state to a maximum value of 5 m to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDC replaces, it is totally symmetrical. The resistance between the wiper and terminal also produces a digitally controlled resistance R. hen these terminals are used the terminal should be tied to the wiper. Setting the resistance value for R starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: R (D) = (128-D)/128 R + R (2) where D is the data contained in the 7-bit RDC latch, and R is the nominal end-to-end resistance. For example, when V = V and terminal is tied to the wiper the following output resistance values will be set for the following RDC latch codes. Figure 4. D7376 Equivalent RDC Circuit 8 REV.

9 D7376 Table II. D R (DEC) ( ) Output State Full-Scale Midscale (RS = Condition) LS 135 Zero-Scale The typical distribution of R from device to device matching is process lot dependent having a ±3% variation. The change in R with temperature has a 3 ppm/ C temperature coefficient. PROGRMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting terminal to +5 V and terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LS less than +5 V. Each LS of voltage is equal to the voltage applied across terminal divided by the 128-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals is: V (D) = D/128 V + V Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 5 ppm/ C. SDO SDI CLK CS D7376 Q 7-IT SERIL REGISTER D GND CK 7 7-IT RDC LTCH R RS 7 SHDN SHDN Figure 41. lock Diagram DIGITL INTERFCING The D7376 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires V SS clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. hen CS is taken active low the clock loads data into the serial register on each positive clock edge, see Table III. The last seven bits clocked into the serial register will be transferred to the 7-bit RDC latch, see Figure 41. Extra data bits are ignored. The serial-data-output (SDO) pin contains an open drain n-channel FET. This output requires a pull-up resistor in order to transfer data to the next package s SDI pin. This allows for daisy chaining several RDCs from a single processor serial data line. Clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO-SDI between devices must be accounted for to successfully transfer data. hen daisy chaining is used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the data bits are in the proper decoding location. This would require 14 bits of data when two D7376 RDCs are daisy chained. During shutdown (SHDN) the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull up resistor. See Figure 42 for equivalent SDO output circuit schematic. Table III. Input Logic Control Truth Table CLK CS RS SHDN Register ctivity L L H H Enables SR, enables SDO pin. P L H H Shifts one bit in from the SDI pin. The seventh previously entered bit is shifted out of the SDO pin. X P H H Loads SR data into 7-bit RDC latch. X H H H No Operation. X X L H Sets 7-bit RDC latch to midscale, wiper centered, and SDO latch cleared. X H P H Latches 7-bit RDC latch to 4 H. X H H L Opens circuits resistor terminal, connects to, turns off SDO output transistor. NOTE P = positive edge, X = don t care, SR = shift register. REV. 9

10 D7376 The data setup and data hold times in the specification table determine the data valid time requirements. The last seven bits of the data word entered into the serial register are held when CS returns high. t the same time CS goes high it transfers the 7-bit data to the VR latch. 1 LOGIC Figure 43. Equivalent ESD Protection Circuit SHDN CS SDI SERIL REGISTER D Q SDO,, CK RS CLK V SS RS Figure 44. Equivalent ESD Protection nalog Pins Figure 42. Detail SDO Output Schematic of the D7376 ll digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 43. pplies to digital input pins CS, SDI, SDO, RS, SHDN, CLK 1 REV.

11 D7376 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Plastic DIP (N-14) 14-Lead TSSOP (RU-14).795 (2.19).725 (18.42).21 (5.1).193 (4.9) (7.11).24 (6.1) PIN 1.6 (1.52).21 (5.33).15 (.38) MX (4.6).115 (2.93).22 (.558).14 (.356).1 (2.54) SC.7 (1.77).45 (1.15) (3.3) MIN SETING PLNE.325 (8.25).3 (7.62).195 (4.95).115 (2.93).15 (.381).8 (.24).177 (4.5).169 (4.3).6 (.15).2 (.5) SETING PLNE PIN (.65) SC (.3).75 (.19).256 (6.5).246 (6.25).433 (1.1) MX.79 (.2).35 (.9) 8.28 (.7).2 (.5) 16-Lead ide ody SOIC (R-16).4133 (1.5).3977 (1.) (7.6).2914 (7.4).4193 (1.65).3937 (1.).118 (.3).4 (.1) PIN (2.65).926 (2.35).291 (.74).98 (.25) x 45.5 (1.27) SC.192 (.49).138 (.35) SETING PLNE.125 (.32).91 (.23) 8.5 (1.27).157 (.4) REV. 11

12 PRINTED IN U.S.. C /97 12