Increment/Decrement Dual Digital Potentiometer AD5222

Transcription

1 a FETURES 128-Position, 2-Channel Potentiometer Replacement 1 k, 5 k, 1 k, 1 M Very Low Power: 4 Max 2.7 V Dual Supply Operation or 2.7 V to 5.5 V Single Supply Operation Increment/Decrement Count Control PPLICTIONS Stereo Channel udio Level Control Mechanical Potentiometer Replacement Remote Incremental djustment pplications Instrumentation: Gain, Offset djustment Programmable Voltage-to-Current Conversion Line Impedance Matching V DD Increment/Decrement Dual Digital Potentiometer D5222 CS DCSEL GND FUNCTIONL LOCK DIGRM D5222 POR DC SELECT ND ENLE UP/DON UP/DON DECODE DECODE GENERL DESCRIPTION The D5222 provides a dual channel, 128-position, digitally controlled variable-resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment push-button applications. Choices between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The D5222 contains two fixed resistors with wiper contacts that tap the fixed resistor value at a point determined by a digitally controlled up/down counter. The resistance between the wiper and either end point of the fixed resistor provides a constant resistance step size that is equal to the end-to-end resistance divided by the number of positions (e.g., R STEP = 1 kω/128 = 78 Ω). The variable resistor offers a true adjustable value of resistance, between Terminal and the wiper, or Terminal and the wiper. The fixed -to- terminal resistance of 1 kω, 5 kω, 1 kω, or 1 MΩ has a nominal temperature coefficient of 35 ppm/ C. The chip select CS, count and direction control inputs set the variable resistor position. The determines whether both VRs are incremented together or independently. ith at logic zero, both wipers are incremented UP or DON without changing the relative settings between the wipers. lso, the relative ratio between the wipers is preserved if either wiper reaches the end of the resistor array. In the independent (Logic 1) only the VR determined by the DCSEL pin is changed. DCSEL (Logic ) changes RDC 1. These inputs, which control the internal up/down counter, can be easily generated with mechanical or push-button switches (or other contact closure devices). This simple digital interface eliminates the need for microcontrollers in front panel interface designs. The D5222 is available in the surface-mount (SO-14) package. For ultracompact solutions, selected models are available in the thin TSSOP-14 package. ll parts are guaranteed to operate over the extended industrial temperature range of 4 C to +85 C. For 3-wire, SPI-compatible interface applications, see the D523/D524/D526, D7376, and D84/D842/ D843 products. INCREMENT 5V CS DCSEL GND V DD Figure 1. Typical Push-utton Control pplication REV. Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. One Technology ay, P.O. ox 916, Norwood, M , U.S.. Tel: 781/ orld ide eb Site: Fax: 781/ nalog Devices, Inc., 1999

2 D5222* PRODUCT PGE QUICK LINKS Last Content Update: 2/23/217 COMPRLE PRTS View a parametric search of comparable parts. EVLUTION KITS D5222 Evaluation Kit DOCUMENTTION pplication Notes N-1291: Digital Potentiometers: Frequently sked Questions N-58: Programmable Oscillator Uses Digital Potentiometers N-582: Resolution Enhancements of Digital Potentiometers with Multiple Devices N-686: Implementing an I 2 C Reset Data Sheet D5222: Increment/Decrement Dual Digital Potentiometer Data Sheet User Guides UG-349: Evaluation oard for the D5222 Digital Potentiometer DESIGN RESOURCES D5222 Material Declaration PCN-PDN Information Quality nd Reliability Symbols and Footprints DISCUSSIONS View all D5222 EngineerZone Discussions. SMPLE ND UY Visit the product page to see pricing options. TECHNICL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDCK Submit feedback for this data sheet. This page is dynamically generated by nalog Devices, Inc., and inserted into this data sheet. dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 D5222 SPECIFICTIONS (V DD = 3 V 1% or 5 V 1%, = V, V = +V DD, V = V, 4 C < T < +85 C, unless otherwise noted.) Parameter Symbol Condition Min Typ 1 Max Unit DC CHRCTERISTICS RHEOSTT (Specifications pply to ll VRs) Resistor Differential NL 2 R-DNL R, V = NC 1 ±1/4 +1 LS Resistor Nonlinearity 2 R-INL R, V = NC 1 ±.4 +1 LS Nominal Resistor Tolerance R V = V DD, iper = No Connect, T = 25 C 3 +3 % Resistance Temperature Coefficient R / T V = V DD, iper = No Connect 35 ppm/ C iper Resistance 3 R I = V DD /R, V DD = 3 V or 5 V 45 1 Ω Nominal Resistance Match R/R O CH 1 to 2, V = V DD, T = 25 C.2 1 % DC CHRCTERISTICS POTENTIOMETER DIVIDER (Specifications pply to ll VRs) Resolution N 7 its Integral Nonlinearity 4 INL R = 1 kω, 5 kω, or 1 kω 1 ±1/4 +1 LS INL R = 1 MΩ 2 ±1/2 +2 LS Differential Nonlinearity 4 DNL 1 ±1/4 +1 LS Voltage Divider Temperature Coefficient V / T Code = 4 H 2 ppm/ C Full-Scale Error V FSE Code = 7F H LS Zero-Scale Error V ZSE Code = H.5 1 LS RESISTOR TERMINLS Voltage Range 5 V,, V DD V Capacitance 6, C, f = 1 MHz, Measured to GND, Code = 4 H 45 pf Capacitance 6 C f = 1 MHz, Measured to GND, Code = 4 H 6 pf Common-Mode Leakage I CM V = V = V 1 n DIGITL INPUTS ND OUTPUTS Input Logic High V IH V DD = 5 V/3 V 2.4/2.1 V Input Logic Low V IL V DD = 5 V/3 V.8/.6 V Input Current I IL V IN = V or 5 V ±1 µ Input Capacitance 6 C IL 5 pf POER SUPPLIES Power Single-Supply Range V DD RNGE = V V Power Dual-Supply Range V DD/SS RNGE ±2.3 ±2.7 V Positive Supply Current I DD V IH = 5 V or V IL = V 15 4 µ Negative Supply Current I SS = 2.5 V, V DD = +2.7 V 15 4 µ Power Dissipation 7 P DISS V IH = 5 V or V IL = V, V DD = 5 V 15 4 µ Power Supply Sensitivity PSS.2.5 %/% 6, 8, 9 DYNMIC CHRCTERISTICS andwidth 3 d _1K R = 1 kω, Code = 4 H 1 khz _5K R = 5 kω, Code = 4 H 18 khz _1K R = 1 kω, Code = 4 H 78 khz _1M R = 5 kω, Code = 4 H 7 khz Total Harmonic Distortion THD V = 1 V rms + 2 V dc, V = 2 V dc, f = 1 khz.5 % V Settling Time t S R = 1 kω, ± 1 LS Error and 2 µs Resistor Noise Voltage e N_ R = 5 kω, f = 1 khz 14 nv Hz 6, 1 INTERFCE TIMING CHRCTERISTICS (pplies to ll Parts) Input Clock Pulsewidth t CH, t CL Clock Level High or Low 3 ns CS to Setup Time t CSS 2 ns CS Rise to Hold Time t CSH 2 ns to Clock Fall Setup Time t UDS 1 ns to Clock Fall Hold Time t UDH 3 ns DCSEL to Clock Fall Setup Time t DSS 2 ns DCSEL to Clock Fall Hold Time t DSH 3 ns to Clock Fall Setup Time t MDS 2 ns to Clock Fall Hold Time t MDH 4 ns NOTES 1 Typicals represent average readings at 25 C, V DD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit. 3 iper resistance is not measured on the R = 1 MΩ models. 4 INL and DNL are measured at V with the RDC configured as a potentiometer divider similar to a voltage output D/ converter. V = V DD and V = V. DNL specification limits of ±1 LS maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit. 5 Resistor Terminals,, have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 P DISS is calculated from (I DD V DD ). CMOS logic level inputs result in minimum power dissipation. 8 andwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 ll dynamic characteristics use V DD = 5 V. 1 See timing diagram for location of measured values. ll input control voltages are specified with t R = t F = 2.5 ns (1% to 9% of +3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = 5 V or V DD = 3 V. Specifications subject to change without notice. 2 REV.

4 D5222 SOLUTE MXIMUM RTINGS (T = 25 C, unless otherwise noted) V DD to GND V, +7 V to GND V, 5 V V DD to V V, V, V to GND V, V DD X X, X X, X X ± 2 m Digital Input Voltage to GND V, V DD +.3 V Operating Temperature Range C to +85 C Maximum Junction Temperature (T J max) C Storage Temperature C to +15 C Lead Temperature (Soldering, 1 sec) C Package Power Dissipation (T J max T )/θ J Thermal Resistance θ J, SOIC (SO-14) C/ TSSOP C/ CS DCSEL t t CSS CH tcsh t CL t UDS t DSS t MDS t UDH t DSH t MDH Figure 2. Detail Timing Diagram Truth Table CS Operation L t H iper Increment Toward Terminal L t L iper Decrement Toward Terminal H X X iper Position Fixed Common Mode ( = ) moves both wipers together either UP or DON the resistor array without changing the relative distance between the wipers. lso, the distance between both wipers is preserved if either reaches the end of the array. Independent Mode ( = 1) allows user to control each RDC individually: DCSEL = sets RDC1; DCSEL = 1: sets RDC2. ORDERING GUIDE Kilo Package Package Model Ohms Temperature Description Option D5222R1 1 4 C/+85 C SO-14 R-14 D5222RU1 1 4 C/+85 C TSSOP-14 RU-14 D5222R5 5 4 C/+85 C SO-14 R-14 D5222RU5 5 4 C/+85 C TSSOP-14 RU-14 D5222R1 1 4 C/+85 C SO-14 R-14 D5222RU1 1 4 C/+85 C TSSOP-14 RU-14 D5222R1M 1, 4 C/+85 C SO-14 R-14 D5222RU1M 1, 4 C/+85 C TSSOP-14 RU-14 The D5222 die size is 56 mil 6 mil, 336 sq. mil; mm mm, sq. mm. Contains 153 transistors. Patent Number applies. PIN FUNCTION DESCRIPTIONS Pin Name Description 1 1 Terminal RDC # Terminal RDC # iper RDC #1, DCSEL =. 4 Negative Power Supply. Specified for operation at both V or 2.7 V (Sum of V DD + < 5.5 V). 5 2 iper RDC #2, DCSEL = Terminal RDC # Terminal RDC #2. 8 GND Ground. 9 Common =, Independent = 1. 1 DCSEL DC Select determines which wiper is incremented in the Independent = 1. DCSEL = sets RDC1, DCSEL = 1 sets RDC2. 11 UP/DON Direction Control. 12 Serial Clock Input, Negative Edge Triggered. 13 CS Chip Select Input, ctive Low. hen CS is high, the UP/DON counter is disabled. 14 V DD Positive Power Supply. Specified for operation at both +3 V or +5 V. (Sum of V DD + < 5.5 V). PIN CONFIGURTION V DD CS 1 3 D TOP VIE 11 (Not to Scale) 1 DCSEL GND CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. lthough the D5222 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. RNING! ESD SENSITIVE DEVICE REV. 3

5 D5222 Typical Performance Characteristics PERCENT OF NOMINL END-TO-END RESISTNCE % R R R R-DNL ERROR LS T = +25 C T = +85 C T = 55 C V DD = +15V = 15V R = 5k Figure 3. iper-to-end Terminal Resistance vs. Code Figure 6. R-DNL Relative Resistance Step Position Change vs. Code 5 3F H H 1..8 V DD / = 2.7V/V T = 25 C V VOLTGE V H 8 H 5 H 2 H R-INL ERROR LS k VERSION 5k VERSION 1M VERSION 1k VERSION 1.5 R = 1k V DD = 5V T = 25 C I CURRENT m Figure 4. Resistance Linearity vs. Conduction Current Figure 7. R-INL Resistance Nonlinearity Error vs. Code SS = 6 UNITS T = 25 C.6.4 V DD / = 2.7V/V T = 25 C FREQUENCY INL LS k VERSION 1k VERSION 5k VERSION M VERSION IPER RESISTNCE Figure 5. iper Contact Resistance Figure 8. Potentiometer Divider INL Error vs. Code 4 REV.

6 D5222 POTENTIOMETER TEMPCO ppm/ C M VERSION 1k VERSION 1k VERSION 5k VERSION V DD / = 2.7V/V T = 25 C Figure 9. V / T Potentiometer Mode Tempco GIN d V DD = +2.7V = 2.7V DT = 4 H V = 5mV rms V = V 6 OP42 1M 5k k 15 1k 764kHz 18 5k 132kHz 1k 64kHz 21 1M 6.6kHz 1 1k 1k 1k 1M FREQUENCY Hz Figure 12. Gain vs. Frequency vs. R 1k RHEOSTT TEMPCO ppm/ C k VERSION 1M VERSION 5k VERSION 1k VERSION V DD / = 2.7V/V T = 25 C Figure 1. R / T Rheostat Mode Tempco THD + NOISE % FILTER = 22kHz V DD = 2.7V V IN = 1V rms T = 25 C SEE TEST CIRCUIT FIGURE 25 SEE TEST CIRCUIT FIGURE k 1k FREQUENCY Hz 1k Figure 13. Total Harmonic Distortion Plus Noise vs. Frequency GIN - d CODE = 3F H 2 H 1 H 8 H 4 H 2 H 1 H T = 25 C SEE TEST CIRCUIT FIGURE k 1k 1k 1M FREQUENCY Hz Figure kω Gain vs. Frequency vs. Code 1M NORMLIZED GIN FLTNESS.1d/DIV SEE TEST CIRUIT 27 = 2.7V V = 5mV rms V = V DT = 4 H OP42 1M 1k 5k 1k 1 1 1k 1k 1k 1M FREQUENCY Hz Figure 14. Normalized Gain Flatness vs. Frequency REV. 5

7 D5222 I DD SUPPLY CURRENT V DD = 5.5V CODE = 15 H V DD = 3.3V CODE = 15 H C V DD = 5.5V CODE = 3F H D V DD = 3.3V CODE = 3F H T = 25 C D 1 1k 1k 1M 1M FREQUENCY Hz Figure 15. I DD, I SS Supply Current vs. Clock Frequency C SUPPLY CURRENT m V DD / = 2.5V V = 2.5V V DD = 5.5V V = 5.5V V.1 = 2.7V INPUT LOGIC VOLTGE V Figure 18. Supply Current vs. Input Logic Voltage 1 9 T = 25 C SITCH RESISTNCE V DD / = 2.7V/V V DD / = 2.7V V DD / = 5.5V/V V = 2.7V V = V V 2mV/DIV 2V/DIV COMMON Volts Figure 16. Incremental iper Contact Resistance vs. V DD / Figure 19. Midscale Transition 3F H to 4 H 1 LOGIC = V OR V DD SUPPLY CURRENT m.1.1 V DD = 5.5V OR V DD / = 2.7V V = 2.7V V = V V V 2mV/DIV 2V/DIV TEMPERTURE C Figure 17. Supply Current vs. Temperature Figure 2. Stereo Step Transition, Mode = 6 REV.

8 Parametric Test Circuits D5222 V+ V+ = V DD 1LS = V+/128 V MS V IN +5V OP V V OUT Figure 21. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) Figure 25. Inverting Programmable Gain Test Circuit +5V NO CONNECT I V IN OP279 5V V OUT V MS Figure 22. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 26. Noninverting Programmable Gain Test Circuit V MS2 I = V DD /R NOMINL V V IN +15V OP42 V OUT V MS1 R = [V MS1 V MS2 ]/I 15V Figure 23. iper Resistance Test Circuit Figure 27. Gain vs. Frequency Test Circuit V+ ~ V V DD V MS V+ = V DD ± 1% V MS PSRR (d) = 2 LOG ( ) V DD V MS % PSS (%/%) = V DD % I S R S =.1V I S CODE = H.1V TO V DD Figure 24. Power Supply Sensitivity Test Circuit (PSS, PSRR) Figure 28. Incremental ON Resistance Test Circuit REV. 7

9 D5222 OPERTION The D5222 provides a 128-position, digitally-controlled, variable resistor (VR) device. Changing the VR settings is accomplished by pulsing the pin while CS is active low. The (UP/ DON) control input pin controls the direction of the increment. hen the wiper hits the end of the resistor (Terminal or ) additional pulses no longer change the wiper setting. The wiper position is immediately decoded by the wiper decode logic changing the wiper resistance. ppropriate debounce circuitry is required when push-button switches are used to control the count sequence and direction of count. The exact timing requirements are shown in Figure 2. The D5222 powers ON in a centered wiper position, exhibiting nearly equal resistances of R and R. DCSEL CS RDC 1 RDC 2 V DD CS DCSEL GND D5222 POR DC SELECT ND ENLE UP/DON UP/DON DECODE DECODE Figure 29. lock Diagram DIGITL INTERFCING OPERTION The D5222 contains a push-button controllable interface. The active inputs are clock (), CS and up/down (). hile the, and DCSEL pins control common updates or individual updates. The negative-edge sensitive input requires clean transitions to avoid clocking multiple pulses into the internal UP/DON counter register, Figure 3. Standard logic families work well. If mechanical switches are used for product evaluation a flip-flop or other suitable means should debounce them. hen CS is taken active low, the clock begins to increment or decrement the internal up/down counter, dependent upon the state of the control pin. The UP/DON counter value (D) starts at 4 H at system power ON. Each new pulse will increment the value of the internal counter by 1 LS until the full-scale value of 7F H is reached, as long as the pin is logic high. If the pin is taken to logic low, the counter will count down, stopping at code H (zero-scale). dditional clock pulses on the pin are ignored when the wiper is at either the H position or the 7F H position. The detailed digital logic interface circuitry is shown in Figure Figure 3. Detailed Digital Logic Interface Circuit ll digital inputs (CS,,,, DCSEL) are protected with a series input resistor and parallel Zener ESD structure shown in Figure 31. ll potentiometer terminal pins (,, ) are protected from ESD as shown in Figure 32. 1k LOGIC Figure 31. Equivalent ESD Protection Digital Pins,, 2 Figure 32. Equivalent ESD Protection nalog Pins D D1 D2 D3 D4 D5 D6 RDC UP/DON CNTR & DECODE R S R S R S R S R S = R NOMINL /128 Figure 33. D5222 Equivalent RDC Circuit 8 REV.

10 D5222 PROGRMMING THE VRILE RESISTOR Rheostat Operation The nominal resistance of the RDC between Terminals and are available with values of 1 kω, 5 kω, 1 kω, and 1 MΩ The final three characters of the part number determine the nominal resistance value, e.g., 1 kω = 1; 5 kω = 5; 1 kω = 1; 1 MΩ = 1M. The nominal resistance (R ) of the VR has 128 contact points accessed by the wiper terminal, plus the terminal contact. t power ON, the resistance from the wiper to either end Terminal or is approximately equal. Pulsing the pin will increase the resistance from the wiper to Terminal by one unit of R S resistance, see Figure 33. The resistance R is determined by the number of pulses applied to the clock pin. Each segment of the internal resistor string has a nominal resistance value of R S = R /128, which becomes 78 Ω in the case of the 1 kω D5222R1 product. Care should be taken to limit the current flow between and in the direct contact state (R code = ) to a maximum value of 2 m to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDC replaces, it is totally symmetrical (see Figure 3). The resistance between the wiper and Terminal also produces a digitally controlled resistance R. hen these terminals are used the -terminal should be tied to the wiper. The typical part-to-part distribution of R is process-lotdependent having a ± 3% variation. The change in R with temperature has a 35 ppm/ C temperature coefficient. The R temperature coefficient increases as the wiper is programmed near the -terminal due to the larger percentage contribution of the wiper contact switch resistance, which has a.5%/ C temperature coefficient. Figures 9 and 1 show the effect of the wiper contact resistance as a function of code setting. PROGRMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting -terminal to 5 V and -terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LS less than 5 V. Each LS of voltage is equal to the voltage applied across Terminals divided by the 128-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to Terminals is: V (D) = D/128 V + V (1) D represents the current contents of the internal up/down counter. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors not the absolute value, therefore, the drift improves to 2 ppm/ C. REV. 9

11 D5222 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Narrow ody SOIC (R-14) 14-Lead TSSOP (RU-14).1574 (4.).1497 (3.8) PIN (8.75).3367 (8.55).5 (1.27) SC (6.2).2284 (5.8).688 (1.75).532 (1.35).196 (.5) (.25) (5.1).193 (4.9) (4.5).169 (4.3).256 (6.5).246 (6.25) C /99.98 (.25).4 (.1).192 (.49).138 (.35) SETING PLNE.99 (.25).75 (.19) 8.5 (1.27).16 (.41) PIN 1.6 (.15).2 (.5).433 (1.1) MX SETING PLNE.256 (.65) SC.118 (.3).75 (.19) 8.79 (.2).35 (.9).28 (.7).2 (.5) PRINTED IN U.S.. 1 REV.