Improved Switching Characteristics Obtained by Using High-k Dielectric Layers in 4H-SiC IGBT: Physics-Based Simulation

Transcription

1 Improved Switching Characteristics Obtained by Using High-k Dielectric Layers in 4H-SiC IGBT: Physics-Based Simulation by vidya.naidu, Sivaprasad Kotamraju in European Conference on Silicon Carbide and Related Materials (ECSCRM-2016) Report No: IIIT/TR/2016/-1 Centre for VLSI and Embeded Systems Technology International Institute of Information Technology Hyderabad , INDIA September 2016

2 Materials Science Forum Submitted: ISSN: , Vol. 897, pp Revised: doi: / Accepted: Trans Tech Publications, Switzerland Online: Improved Switching Characteristics Obtained by Using High-k Dielectric Layers in 4H-SiC IGBT: Physics-Based Simulation Vidya Naidu 1,a and Sivaprasad Kotamraju 2,b* 1 International Institute of Information Technology, Hyderabad, India 2 Indian Institute of Information Technology, SriCity, Chittoor district, India a g.vidya.naidu@gmail.com, b siva.k@iiits.in Keywords: High-k dielectrics, Power dissipation trend, Switching characteristics, Tail current Abstract. Silicon Carbide (SiC) based MOS devices are one of the promising devices for high temperature, high switching frequency and high power applications. In this paper, the static and dynamic characteristics of an asymmetric trench gate SiC IGBT with high-k dielectrics- HfO 2 and ZrO 2 are investigated. SiC IGBT with HfO 2 and ZrO 2 exhibited higher forward transconductance ratio and lower threshold voltage compared to conventionally used SiO 2. In addition, lower switching power losses have been observed in the case of high-k dielectrics due to reduced tail current duration. Introduction The wider bandgap, higher thermal conductivity, and larger critical electric field allow SiC devices to offer several compelling advantages high operating temperatures, higher-operating electric field and lower losses than Si power devices[1]. However, SiC MOS structures have the disadvantage of lower channel mobility, SiC-SiO 2 interface compatibility and the inability in handling higher electric fields at the interface. The choice of gate dielectric in SiC MOS device plays important role in the device performance. High-k dielectrics such as HfO 2 & ZrO 2 have been incorporated in the SiC IGBT, as these dielectrics have dielectric constant of about 25 and have the ability to sustain much higher electric fields than SiO 2. Attributing to high dielectric constant, HfO 2 has very high breakdown voltage, supporting the high electric field endurance of SiC in power devices [2,3]. On the other hand, high-k dielectrics have lower band offsets at SiC interface, that could lead to high leakage currents. Low band offsets at the high-k/sic interface were addressed earlier by introducing an ultrathin SiO 2 interfacial layer in between dielectric and SiC layer [4,5]. In this paper, sentaurus TCAD device simulations are performed to study static and dynamic behavior of SiC IGBT with HfO 2 & ZrO 2 as gate dielectrics. In addition, switching characteristics of the IGBT is investigated by considering the drive circuit similar to the one given in reference [6]. Fig.1. Half cell structure of an asymmetric trench gate SiC IGBT generated by Sentaurus structure editor. Non-uniform scale has been used for thickness markings. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (# /04/17,19:03:27)

3 572 Silicon Carbide and Related Materials 2016 Device Simulation Setup The half cell structure of SiC trench gate IGBT considered for simulations is shown in Fig.1. Physics based models such as drift-diffusion transport model, bandgap narrowing, Auger & Shockley-Read-Hall (SRH) recombination, doping and temperature dependent field mobility [7] are taken into account. For gate leakage current through the dielectrics, Fowler-Nordheim tunneling model & non-local tunneling model [7] are considered. While the trench gate devices provide low on state voltage drop, it is challenging to fabricate deep trench structures in SiC. Simulation results of 10 KV trench gate SiC IGBT with gate trench depth of 6µm and 5µm thick p-type conduction layer has been reported earlier [8]. There has been evidence of stripe Fig.2. Collector current versus gate voltage(transfer characteristics) for different dielectrics. Inset: Collector current versus collector voltage(output characteristics) for different dielectrics of 20nm thickness. trenches of 4µm deep and 3µm wide fabricated using ICP dry etching [9]. This paper is focussed more towards the influence of high-k dielectrics on the IGBT switching characteristics. Static and dynamic characteristics of the IGBT are obtained for 20nm HfO 2, ZrO 2 and SiO 2 gate dielectrics individually placed on top of the SiC substrate. The simulations are repeated by sandwiching 1nm SiO 2 between SiC and high-k dielectric layers. To obtain dynamic characteristics of the IGBT, the device is embedded in an external gate drive circuit with the inductive load of 100 µh at the collector terminal, which is connected to a DC voltage source. A voltage pulse(vgg) from 0V to 15V with period of 1μs is applied to gate terminal. The drive resistor to the input of the gate terminal is fixed at 470 Ω. Mixed mode device simulation has been used in TCAD to obtain the switching characteristics of the device. A fixed trap concentration of 1E12cm -2 is considered for all simulations. Turn ON delay(td(on)) is calculated as the time period from 10% of applied rising gate voltage to 10% of maximum collector current. Rise time(tr) is calculated as time period taken by collector current to rise from 10% to 90% of its maximum value. Turn OFF delay(td(off)) is calculated as the time period from 90% of applied falling gate voltage to 90% of maximum collector current. Fall time(tf) is calculated Fig.3. Gate Leakage Current for diff-erent dielectrics of thickness 20nm at 300 K. as time period taken by collector current to drop from 90% to 10% of its maximum value. Tail current is specific to the IGBT and is approximately the time period from sudden change in dic/dt to the point where collector current almost becomes zero.

4 Materials Science Forum Vol Results and Discussions The transfer characteristics (collector current(ic) Vs. gate voltage(vg)) of the device is obtained at a constant collector voltage(vc) of 5V. Fig. 2 illustrates the static characteristics of IGBT for different dielectrics of 20nm thickness. The slope of the transfer characteristic gives the measure of the transconductance of the device. From the direct inspection of the transfer characteristics, it can be seen that the high-k dielectrics have a higher forward transconductance ratio as compared to SiO 2. Table 1. Approximate time values extracted from device collector current transient characteristics. All numbers are in nano-seconds. Dielectric Rise time (tr) Td (ON) Td (OFF) Fall Time(tf) A high transconductance ratio is desirable to obtain good current handling capability with low gate drive voltage. The threshold voltage values for HfO 2 & ZrO 2 are found to be much lower than SiO 2. Also, from the inset of Fig.2, high-k dielectrics exhibit much higher Ic for any given Vc which could be beneficial from the device point of view leading to lower ON resistance during conduction mode. In Fig.3 the gate leakage current with respect to applied gate voltage is plotted. The leakage current for high-k dielectrics is observed to be much higher as compared to SiO 2. This could be as a result of low band offset at the oxide/sic interface. In order to reduce the leakage current, a thin layer of SiO 2 (1nm) is inserted between SiC and 20nm high-k dielectrics. Insertion of 1nm SiO 2 reduced the leakage current drastically to a value lower than the leakage current of the 20nm SiO 2 curve. Table 1 lists switching times for the different dielectrics obtained by dynamic simulations. Fig 4 shows the collector current high-low transition for a fixed dielectric thickness of 20nm. A clean break is observed during the turn off process indicating the inception of tail current. The tail current is a common phenomenon observed in IGBTs due to the minority carrier holes that are trapped in the base region, which slowly recombine with electrons causing a delay in the turn off process. For applied pulse voltage at gate, SiO 2 has the longest OFF time duration. From Fig.4 it can be observed that the tail current is much lower for HfO 2 and ZrO 2 as compared to SiO 2. This reduction in tail current duration reflects in the total turn OFF duration. The tail current for HfO 2 /ZrO 2 is approximately 380 nano-secs whereas for SiO 2 it is 1070 nano-secs. Even with a thin layer of SiO 2 between SiC and high-k dielectric, the OFF time observed for high-k dielectrics is much lower than SiO 2. This improvement in turn OFF time for high-k dielectrics could enhance the switching frequency and hence Tail Current (tail) HfO ZrO SiO HfO 2 +1nm SiO ZrO 2 +1nm SiO T (OFF)=Td(OFF)+tf+tail Fig.4. OFF state characteristics of the device for different dielectrics. The thickness of the dielectrics is 20nm with all other parameters related to device kept same. reduces the switching power dissipation. The inclusion of high-k dielectrics in the device might have eventually led to the reduction of minority carrier lifetime in the base region. However, it

5 574 Silicon Carbide and Related Materials 2016 needs to be further investigated as a part of future work. Reduced OFF time values indicate lower power dissipation. Power dissipation curves were plotted for temperature range of K. At 300K, the power dissipation curves for SiO 2 and high-k dielectrics were almost overlapping [Fig.5]. At 400K, the power dissipation for HfO 2 /ZrO 2 was visibly lower than SiO 2, but at 600K the power dissipation for SiO 2 was almost 10 Watts higher than HfO 2 /ZrO 2. Along with other advantages, high-k dielectrics exhibited superior performance as far as turn off losses and power dissipation are concerned. Summary The static and switching characteristics of SiC trench gate IGBT have been analyzed using ZrO 2 and HfO 2 gate dielectrics and compared with conventionally used SiO 2. While no significant difference has been observed individually between ZrO 2 and HfO 2, high- K dielectrics exhibited favorable static characteristics as compared to SiO 2. From the device turn OFF characteristics, improved OFF time values have been observed due to reduced tail current duration for high-k dielectrics. The obtained results confirm the critical role of high-k dielectrics for future SiC power devices. References Fig.5. Power dissipation as a function of time when the applied pulse (shown in dotted line) is high. At any temperature, the power dissipation of IGBT with high-k dielectric is lower than SiO 2. [1] Stephen E. Saddow and Anant K. Agarwal, Advances in Silicon Carbide Processing and Applications, Artech House Publishers(2004), Chapter 1, ISBN [2] M. Nawaz, On the evaluation of gate dielectrics for 4H-SiC based power MOSFETs, Hindawi publishing corporation, Active and Passive Electronic Components(2015), Article ID [3] A. Taube, S. Gierałtowskac, T. Gutta, T. Małachowskia, I. Pasternaka, T. Wojciechowskic, W. Rzodkiewicza, M. Sawickic and A. Piotrowskaa, Electronic properties of thin HfO 2 films fabricated by ALD on 4H-SiC, Acta Physica Polonica A(2011), , Vol.119. [4] K. Y Cheong, J.H. Moon, T. J. Park, J. H.Kim, C. S. Hwang, H. Joon K., W. Bahng and N.K. Kim, Improved electronic performance of HfO 2 /SiO 2 stacking gate dielectric on 4H-SiC, IEEE Transactions on Electron Devices(2007), , Vol. 54, No.12. [5] Mahapatra, R., Chakraborty, Amit. K., Horsfall, A. B., Wright, N. G., Beamson, G. and Coleman, Karl. S., Energy-band alignment of HfO 2 /SiO 2 /SiC gate dielectric stack, Applied Physics Letter(2008), 92, [6] X. Kang, A. Caiafa, E. Santi, J. L. Hudgins and P. R. Palmer, Characterization and modeling of high-voltage field-stop IGBTs, IEEE Transactions on Industry Applications(2003), , Vol. 39, No. 4. [7] Synopsys Inc. Sentaurus device user manual, Ver K [8] Q. C. J. Zhang, S. H. Ryu, C. Jonas, A. K. Agarwal, J. W. Palmour, Simulations of 10 kv Trench Gate IGBTs on 4H-SiC, Materials Science Forum(2006), Vols , pp [9] Y. Takeuchi, M. Kataoka, T. Kimoto, H. Matsunami, R. K. Malhan, SiC Migration Enhanced Embedded Epitaxial (ME 3 ) Growth Technology, Materials Science Forum(2006), Vols , pp