Frequency Synthesizers
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1 Phase-Locked Loops Frequency Synthesizers Ching-Yuan Yang National Chung-Hsing University epartment of Electrical Engineering
2 One-port oscillators ecaying impulse response of a tank Adding of negative resistor to cancel loss in R P Use of an active circuit to provide negative resistance 10-1 Ching-Yuan Yang / EE, NCHU
3 Oscillator using negative input resistance Oscillator using negative input resistance of a source follower with positive feedback. For oscillation build-up,. If the small-signal resistance presented by M 1 and M 2 to the tank is less negative than, then the circuit experiences large swings such that each transistor is near off for part of the period, thereby yielding an average resistance of. ifferential version 10-2 Ching-Yuan Yang / EE, NCHU
4 Calculation of Intrinsic Phase Noise in Oscillators Noise sources in oscillators are put in two categories Noise due to tank loss Noise due to active negative resistance We want to determine how these noise sources influence the phase noise of the oscillator Ching-Yuan Yang / EE, NCHU
5 Separation into Amplitude and Phase Noise Equipartition theorem (see Tom Lee, p 659) states that noise impact splits evenly between amplitude and phase for V sig being a sine wave Amplitude variations suppressed by feedback in oscillator (single -sided) 10-4 Ching-Yuan Yang / EE, NCHU
6 Output Phase Noise Spectrum (Leeson s Formula) Spectral density of noise Power of carrier All power calculations are referenced to the tank loss resistance, R p 10-5 Ching-Yuan Yang / EE, NCHU
7 Example: Active Noise Same as Tank Noise Noise factor for oscillator in this case is Resulting phase noise 10-6 Ching-Yuan Yang / EE, NCHU
8 Phase noise in oscillators 10 log 2FkT P sig Measured in db below carrier per unit bandwidth. Phase noise: Note: Leeson assumed that F(f) was constant over frequency. Hajimiri, IEEE JSSC, Mar Ching-Yuan Yang / EE, NCHU
9 Phase Noise of A Practical Oscillator Phase noise drops at -20 db/decade over a wide frequency range, but deviates from this at: Low frequencies slope increases (often -30 db/decade) High frequencies slope flattens out (oscillator tank does not filter all noise sources) Frequency breakpoints and magnitude scaling are not readily predicted by the analysis approach taken so far Ching-Yuan Yang / EE, NCHU
10 Phase noise contributions from LC tank V L R p C p C p R p L V out I T V max Phase noise L(f) where V max is below saturated voltage. I T iscussion: Phase noise contributions from tail current = channel noise factor If V max is constant (saturated), I T Phase noise L(f). Phase noise contributions from differential pair If V max is constant, g m (or W/L) Phase noise L(f). J. Rael and A. Abidi, IEEE CICC, Ching-Yuan Yang / EE, NCHU
11 General Transceiver Block iagram LNA Baseband RxRF 1st IF 2nd IF To e-modulator Baseband I LO 1 Frequency Synthesizer LO 2 Frequency Synthesizer 90 o TxRF PA Buffer TxIF Baseband I From Modulator Baseband Ching-Yuan Yang / EE, NCHU
12 Classical PLL Block iagram Phase etector Loop Filter VCO F X R F R F VCO TCXO F VCO N TCXO: Temperature Compensated Crystal Oscillator VCO: Voltage Controlled Oscillator N Frequency Tuning In the locked state: F VCO = N F R, N F VCO / N = F X / R = F R The TCXO provides a reference frequency to the synthesizer circuit so that it may accurately produce a wide range of signals that are stable and relatively low in phase noise. By changing the value N, the output frequency F VCO can be tuned across the frequency band of interest. The only constraint to the frequency output of the system is that the minimum frequency resolution, or minimum channel spacing, is equal to F R. Channel spacing = F VCO / N = F R Ching-Yuan Yang / EE, NCHU
13 PLL Frequency Synthesizer Employing a Prescaler Phase etector Loop Filter VCO F X R F R F VCO TCXO F VCO NV Low-Speed ivider High-Speed ivider N V Frequency Tuning Prescaler In the locked state: F VCO = N V F R = N (VF R ) N, V Channel spacing = F VCO / N = VF R Ching-Yuan Yang / EE, NCHU
14 PLL Frequency Synthesizer Employing a ual-modulus Prescaler Ching-Yuan Yang / EE, NCHU
15 High-Speed ual-modulus ividers High-speed ivide-by-4/5 counter Mode SW FF1 FF2 FF3 fin CLK CLK MC CLK fout CLK CLK CLK CLK CLK SW Mode fout fin/128 fin/129 fin/64 fin/65 ivide-by-32 counter Ching-Yuan Yang / EE, NCHU
16 ivide-by-4/5 divider ivide-by-4/5 counter FF1 FF2 FF3 fin CLK CLK CLK MC fin 1 MC = MC = Ching-Yuan Yang / EE, NCHU
17 Two Kinds of ivider Structure Analog: Regenerative (ynamic) Regenerative Frequency ivider Mixer LPF AMP Proposed by Miller, 1939 igital: Flip-Flop Based (Static and ynamic) Ching-Yuan Yang / EE, NCHU
18 Toggle Flip-Flop Based Frequency ivider Latch Latch Ching-Yuan Yang / EE, NCHU
19 All Kinds of Latches can be used Ching-Yuan Yang / EE, NCHU
20 ynamic TSPC CMOS FFs TSPC FF proposed by Yuan and Svensson An improved TSPC FF. Huang, IEEE JSSC, Mar Ching-Yuan Yang / EE, NCHU
21 High-Speed ifferential FFs ECL, CML, SCFL(SCL): Very High Speed igital Circuits ECL: Emitter Coupled Logic CML: Current Mode Logic SCFL: Source Coupled FET Logic All uses Current Switches Basic Structure of SCFL(SCL), ECL, CML Ching-Yuan Yang / EE, NCHU
22 Advantages of SCFL(SCL), ECL, CML Low logic swing High Speed ifferential Structure High sensitivity, easy interface Easy Combinational Logic embedded Basic structure of a latch Ching-Yuan Yang / EE, NCHU
23 An Conventional ECL Mater-Slave elay Flip-Flop Edge trigger FF in V out in V out -latch without source followers Ching-Yuan Yang / EE, NCHU
24 - ivide-by-2 circuit OUT Ching-Yuan Yang / EE, NCHU
25 State-of-the-art Synchronous Pipeline Stage The critical cycle time of the synchronous building block is composed of: the propagation delay of the combination logic block (t pdl ) the set-up time (t sus ) and the propagation delay (t pds ) of the storage element The maximum operating frequency f max t 1 ( t In order to increase the maximum operating frequency, two concerns would be discussed. How to reduce the insertion delay of the storage element (t sus + t pds ). How to reduce the delay of the logic block (t pdl ). pdl sus t pds ) Ching-Yuan Yang / EE, NCHU
26 High-Speed Logic Flipflops (LFFs) ivide-by-4/5 prescaler NOR-FF FF NOR-FF NOR-FF MC A B V REF Ching-Yuan Yang / EE, NCHU
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