Application of Level Shifted Modulation Strategies for Switching of Stacked Multicell Converter (SMC)

Transcription

1 Applictio of Level hifted Modultio trtegies for witchig of tcked Multicell Coverter (MC) Ritesh C. Ujwe, Prg G. hewe, Asst. Professor, Deprtmet of Electricl Egieerig, Dr.Bbsheb Ambedkr College of Egieerig Ad Reserch, R.T.M. Ngpur Uiversity, Ngpur, Idi Abstrct- Multilevel Iverters re very importt i the field of medium d high voltge pplictios. This pper presets the tcked Multicell Coverter which is derived topology of the covetiol Flyig Cpcitor Multilevel Iverter topology. The Level hifted Multicrrier iusoidl Pulse Width Modultio techique is used for the geertio of firig sigls for tcked Multicell Coverter (MC). The tcked Multicell Coverter topology of Multilevel Iverter cuses icrese i the umber of output voltge levels with less THD, turl self blcig of flyig cpcitors voltge, icrese redudcy to obtied desired voltge level, reductio i the voltge rtigs of cpcitors d semicoductor losses. The proposed topology is simulted usig MATLAB oftwre pckge d simultio results re preseted to vlidte the effectiveess d dvtges of the proposed tcked Multicell Coverter (MC) topology. Idex Terms- Multilevel Iverter topologies, tcked Multicell Coverter (MC), Multicrrier iusoidl Pulse Width Modultio (PWM). I. INTRODUCTION The Multilevel Voltge ource coverter topologies re best suited for the medium d high voltge pplictios i the idustries. The term multilevel iverter strts from the three levels [3]. The mi purpose of usig Multilevel Iverter is to sythesize erly siusoidl voltge. Multilevel iverters hve the cpbility to hdle the voltge i the rge of KV d Megwtts with medium voltge semicoductors []. Multilevel iverter icludes rry of power semicoductors d cpcitor voltge sources, the output of which geerte voltges with stepped wveforms. The commuttio of the switches permits the dditio of the cpcitor voltges, which rech the high voltge t the output, while the power semicoductors must withstds oly reduced voltges [4]. This pper presets the MC topology of multilevel iverter which is derived from covetiol FCMLI topology. The multicrrier siusoidl pulse width modultio techique for MC is give. The three covetiol topologies d tcked Multicell Coverter topology performces is compred o the bsis of output voltge THD d their fudmetl output voltges. II. MULTILEVEL INVERTER TOPOLOGIE Bsiclly there re three covetiol topologies of Multilevel Iverter s follows; ) Diode clmped or Neutrl poit clmped Multilevel (NPC) Iverter. b) Cpcitor clmped or Flyig cpcitor Multilevel (FCM) Iverter. c) Cscded coverter (CC). A. Neutrl Poit Clmped (NPC) Multilevel Iverter A m-level diode clmped coverter typiclly cosists of m- cpcitors o the dc bus d produces m levels of the phse voltge. Fig. shows the three level diode clmped multilevel iverter i which the dc bus cosist of two cpcitors, C, C. For dc bus voltge Vdc, the voltge cross ech cpcitor is Vdc/, d ech device voltge stress will be limited to oe cpcitor voltge level, Vdc/, through clmpig diodes. V dc V dc V dc C C D D,, o IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE REEARCH IN TECHNOLOGY 49

2 Fig. Three-level-Diode Clmped Multilevel Iverter Advtges of diode clmped Multilevel Iverter is s follows. Whe the umbers of output voltge level is high, hrmoic distortio will be less. Efficiecy is high becuse ll semicoductor devices re operted t the fudmetl frequecy. Rective power flow c be cotrolled. The cotrol strtegy is simple for bck-to-bck itertie system. Disdvtges: Number of clmpig diodes is more whe the umber of output voltge levels is high. Complictios i rel power flow cotrol for the idividul coverter. B. Flyig Cpcitor Multilevel Iverter (FCM) Fig. illustrtes the fudmetl buildig block of sigle phse full-bridge flyig cpcitor bsed three level iverter. Ech phse-leg hs ideticl structure. The voltge level defied i the flyigcpcitor coverter is similr to tht of eutrl-poit clmped iverter. The phse voltge of m-level coverter hs m levels icludig the referece level, d the lie voltge hs (m-) levels. Assumig tht ech cpcitor hs the sme voltge rtig s the switchig device, the dc bus eeds (m-) cpcitors for m-level coverter. V Vdc dc C C Whe the umber of levels is high, hrmoic cotet will be low to void the eed for filters. Both rel d rective power flow c be cotrolled. Disdvtges: Lrge umber of storge cpcitors is required whe the umber of coverter levels is high. The iverter cotrol will be very complicted, d the switchig frequecy d switchig losses will be high for rel power trsmissio. C. Cscded coverters The cscded coverter c void extr clmpig diodes or voltge blcig cpcitors. Fig.3 shows five level cscded H-bridge coverters with seprte dc source. The c termil voltge of differet level iverters is coected i series. Ech H-bridge iverter geertes three level outputs, +Vdc, 0, d Vdc. This is mde possible by coectig the dc sources sequetilly to the c side vi the four gtetur-off devices. Miimum hrmoic distortio c be obtied by cotrollig the coductig gles t differet iverter levels. c c s s 3 s 4 s s 5 s 7 Vdc C Fig. Three-level-Cpcitor Clmped Multilevel Iverter Advtges of Flyig Cpcitor Multilevel Iverter re s follows. Cpcitor voltges provides extr ride through cpbilities durig power filure. Redudcy (witchig combitio) for blcig differet voltge levels. 0 s 8 s 6 Fig. 3 Five-level- Cscded Full H-Bridge Coverter Advtges of Cscded Coverters re s follows; Lest umbers of compoets required, compre to ll multilevel topologies to chieve the sme umber of voltge levels. Modulrized circuit lyout d pckgig is possible becuse ech level hs the sme structure, d there re o extr clmpig diodes or voltge blcig cpcitors. oft switchig c be used i this topology. IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE REEARCH IN TECHNOLOGY 50

3 Disdvtges: eprte dc sources re required for rel power coversios, d thus limittios i pplictio of this topology. III. TACKED MULTICELL CONVERTER (MC) A MC is iverter (DC-AC Coverter) for high voltge pplictios. The topology of this iverter is mde up of by m rry of cells, see Fig.4. this cofigurtio llows to shre the totl voltge d curret stresses mog the switches. The it is possible to use covetiol semicoductors to hdle high output power. The pplictio re for MC c be foud i pplictios such s UP, witchig Power upplies, DTATCOM, etc. CELL 3 CELL CELL 3 E/3 E/3 3 CELL CELL E/3 E/3 CELL Fig.4 3- cell- 7 level tcked Multicell Coverter tcked Multi-cell Coverter is proposed to icrese the o. of output voltge levels d s result, reduced the output voltge THD with reduced rtigs d losses of flyig cpcitors d semicoductors [][6]. A 3-Cell-7-level sigle phse stcked multicell coverter is show i figure bove where, m = o. of stcks (rows) d = o. of colums (stge). MC is bsed o ssocitios of bsic switchig cells coected i series. Ech oe of these switchig cells is built with two switches. The bsic switchig cells hve complemetry sttes. It mes, tht oly oe switch is coductig t give time. The ssocitio of these switchig cells llows the voltge to be distributed mog the switches, givig better output wveforms i terms of the umber of levels used. To esure its fuctiolity, MC used cpcitors like itermedite voltge sources. This is due to the fct tht switchig cells oly work if they re beig powered by flyig voltge sources without verge power. The MC of bove figure uses m =6 switchig cells d (-) m = 4 flyig cpcitors. The voltge cross ech cpcitor is equl to; V=i E/m Where, E is the totl iput voltge of the coverter. The No. of cofigurtio sttes i MC is equl to: N cofig = (+) m For 3 MC, sixtee sttes c be obtied; this mes tht ech sttes geertes differet voltge levels t the output. However, eve sixtee sttes re possible; some of them hve the sme output voltge. These sttes c or ot be used depedig o the cotrol strtegy. For m MC the mximum umber of output voltge level is give by: N level = (m )+ For MC structure the complexity of cotrol is bsed o PWM strtegy. The blockig voltge for ech switchig device is: V switch =E/m IV. MULTICARRIER INUOIDAL PULE WIDTH MODULATION (LEVEL HIFTED PWM) The multicrrier siusoidl pulse width modultio techique hs three very simple dispositios tht seem the most iterestig: ) All the crriers re ltertively i oppositio (APODPWM) s show i Fig. 5, with this method the most sigifict hrmoics re cetred s side bds roud the crriers. Fig. 5 Alterte Phse Oppositio Dispositio PWM )All the crriers bove zero vlue referece re i phse mog them but i oppositio with those below (PODPWM) s show i Fig. 6, the sigifict hrmoics re locted roud the crrier frequecy, for both phse d lie-to-lie voltge wveform. IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE REEARCH IN TECHNOLOGY 5

4 Fig. 6 Phse Oppositio Dispositio PWM 3) All the crriers re i phse (PDPWM), for this techique, sigifict hormoic eergy is cocetrted t the crrier frequecy, but sice it is the co-phsel compoet, it does ot pper i the lie-to-lie voltge, PDPWM is s show i Fig. 7, Topology Fudmetl RM Output Phse Voltge i Volts THD (Three Level) Neutrl-Poit 53.9 Clmped 84.8 Flyig Cpcitor Cscded tcked Multicell Fig. 8 Output Phse Voltge of Three-level-Neutrl- Poit Clmped Multilevel Iverter Fig. 7 Phse Dispositio PWM V.IMULATION REULT kh z I this sectio, i order to verify the good performce of proposed topology cofigurtio, computer simultio is provided. The topologies re simulted usig MATLAB softwre. The prmeters used i simultio re give i tble I. The simultio results re preseted for covetiol topologies of Multilevel Iverters d proposed tcked Multicell Coverter (MC). Tble shows the performce compriso of differet topologies of Multilevel iverter o the bsis of fudmetl output voltge d THD. TABLE I PARAMETER UED FOR IMULATION Prmeters vlues DC voltge 00 V Fudmetl switchig frequecy 50H z Resistive- Iductive lod Ω, mh witchig frequecy of coverter (f switchig) TABLE II UMMARY OF IMULATION REULT FOR DIFFERENT MULTILEVEL INVERTER TOPOLOGIE Fig. 9 Output Phse Voltge of Three-level-Cpcitor Clmped Multilevel Iverter Fig. 0 Output Phse Voltge of Three-level Cscded Multilevel Iverter Fig. Output Phse Voltge of 3-7- level tcked Multicell Iverter IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE REEARCH IN TECHNOLOGY 5

5 VI.CONCLUION The performce of the covetiol Multilevel Iverter topologies like Neutrl-Poit clmped Multilevel Iverter, Flyig Cpcitor Multilevel Iverter, Cscded Multilevel Iverter hve bee checked with crrier bsed siusoidl pulse width modultio. The exteded versio of flyig cpcitor Multilevel Iverter the tcked Multicell Coverter hve lso bee exmied to the crrier bsed siusoidl pulse width modultio. The qulity of the spectrum performce of the output wveform is checked by THD d utiliztio of the iput DC voltge is checked by fudmetl vlues of the output AC voltge. I level shifted modultio techiques tht is PD, POD, d APOD the THD for out of three, the THD is foud to be lest with PDPWM. The fudmetl vlue of phse voltge is foud mximum i tcked Multicell Coverter Cofigurtio. Itertiol coferece o Electroics, Commuictio d computers, 004. [7] Georgios. Kosttiou d Vssilios G. Agelidis, Performce Evlutio of Hlf- Bridge Cscded Multilevel Coverters Operted with Multicrrier iusoidl PWM Techiques IEEE, ICIEA 009. REFERENCE [] Meism deghi, Ami Nzrllo, yed Hosseii, Ebrhim Bbei, A New DTATCOM Topology Bsed o tcked Multicell Coverter, IEEE d Power Electroics, Drives ystems d Techologies Coferece, pp.05-0, 0. [] Pblo Lez, Jose Rodriguez, Mixed Multicell Cscded Multilevel Iverter, IEEE, pp , 007. [3] Jose Rodriguez, Jih-heg Li d Fg Zheg, Multilevel Iverters: A urvey of Topologies, Cotrols, d pplictios, IEEE Trs. Idustril Electroics, vol. 49, o. 4, pp , August 00. [4] J.. Ll, F.Z. Peg, Multilevel coverters - A ew breed of power coverters, IEEE Trs. Idustril Electroics, vol. 44, o. 3,pp , Ju [5] Giuseppe Crrr, imoe Grdell,Mrio Mrchesoi,Member, A New Multilevel PWM Method: A Theoreticl Alysis IEEE Trs. O power electroics, vol. 7, o.3, pp , July 99. [6] Jose Mrio Ferdez Nv, Pedro Buelos chez, tcked Multicell Coverter Cotrolled by DP Proceedigs of the 4th IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE REEARCH IN TECHNOLOGY 53