Multi-gigabit signaling with CMOS

Transcription

1 Multi-gigabit signaling with CMOS William J. Dally - Massachusetts Institute of Technology John Poulton - University of North Chapel Hill Steve Tell - University of North Chapel Hill This work supported under DARPA Contract No. DABT63-96-C May 12, 1997

2 Outline Intro -- The Bandwidth Gap Improved CMOS Signaling Systems Fundamental Limits & Possible Solutions Experimental 4Gb/s Signaling System Results and Conculsion 2 May 12, 1997

3 µprocessor I/O Bandwidth (Gates: 50%/year) X (Clk Speed: 20%/year) = 80%/year (Chip Edge Dim. 6%/year) X (Pin Density: 6%/year) X (I/O Speed: 14%/year) = 28%/year Gates MHz B 8080 B 8086 B B 386 B 486 DEC B B B P5 P6 Pins MHz B 8086 B 386 B B 486 B B B P B DEC P6 Connection between two graphs: Rent's Rule Pins = K (Gates) α = 7 (Gates) 0.2 for Microprocessors 3 May 12, 1997

4 Bandwidth Gap I/O Demand for ASICs Pins = 4 (Gates) 0.6 Problem: Large & Growing Bandwidth Gap Pins MHz I/O bandwidth (current trend) Opportunity: Run I/O's at 5-x Internal Clock Rates 4 May 12, 1997

5 Bandwidth Gap Current I/O signaling anomolous (I/O slower than internal clock) Does it really take longer to send a bit from one chip to another than to do a 64-bit add?? Hostage to obsolete, poorly conceived signaling standards Voltage-mode signals referenced to power supplies Considerable recent progress: Standards: RAMBUS, IEEE1596/LVDS, IEEE1394, etc. Special and Experimental systems: Bull Serial Link (1992, 0.5µCMOS, 1Gb/sec) Yang & Horowitz (1996 ISSCC, 0.8µCMOS, 2.5Gb/sec) Fiedler, et.al. (1997 ISSCC, 0.5µCMOS, 1.06Gb/sec) Chen & Baker (1997 ISSCC, 0.5µCMOS, 1.25Gb/sec) 5 May 12, 1997

6 Characteristics of 'Good' CMOS Signaling Systems 'motherhood' Differential Rejects external noise, most external sources common-mode Avoids reference-generation problem (bundled or local) Lemma: A differential signal pair can always be driven faster than two single-ended paths. Current-Mode Twin benefits: Decouples signals from power supply noise; avoids generating self-induced noise Controlled Edge Rates Edge time should never be shorter than half bit-cell time; Reduce reflections from impedance discontinuities On-Chip Termination A 'must' to avoid reflections from unterminated stubs Per-pin Timing (Receiver Clock) Recovery Avoids bundled clocking and difficult skew control problems controversial Best Advantage from Available Devices CMOS NFETs good switches, accurate current sources PFETs poor switches, poor current sources, good resistors Argues for unipolar differential signaling bias 6 May 12, 1997

7 How Fast can CMOS Go? 0.5µ CMOS has FO4 inverter delay of about 180psec Can switch current onto a differential wire pair at 4Gb/sec fairly easily Recovering the data is harder! T bit T jitter T aperture T bit > T jitter + T aperture Critical circuit design issue: Generating precise, jitter-free multi-phase clocks Gb/sec at 0.25µ?? 7 May 12, 1997

8 Performance Limitations Proposed Solutions Transmitter Speed Timing Uncertainty Receiver Bandwidth Reflections and Mismatches N-way multiplexed transmitter operates at 1/N bit rate Replica-biased differential timing elements (simulated jitter ~ 40psec in 0.5µ CMOS) Multiplexed receivers Oversampling Tracking (50psec aperture) Closed-loop timing recovery cancels skew & low-frequency jitter Packaging design issue; on-chip terminations adjustable to a few %. Frequency-Dependent Attenuation (Skin Effect) Transmitter equalization 8 May 12, 1997

9 Skin Effect Frequency-dependent Resistance K= 1.31X-8 Ωs 1/2 (round conductors) K = 4.12X-8 Ωs 1/2 (thin strips) 1M #24 twisted pair, Z 0 (diff)=0ω 1M 5-mil stripguide Z 0 (diff)=0ω 1 R(f) = Kf1/2 d (Ω/M) conductor dimension (width, radius) Frequency-dependent Attenuation Attenuation A(f,x) = exp R(f) Z 0 x Frequency (MHz) More attenuation from dielectric loss, radiation, package parasitics, lumped capacitance at load... 9 May 12, 1997

10 Intersymbol Interference The 'Lone Pulse' Problem: 1 2A-1 A Attenuation Jitter Equalization attenuates low frequencies at transmitter by A using (FIR) filter that complements line characteristics A May 12, 1997

11 Transmitter Equalization Without Equalization With Equalization Near Far These are simulated results with a 5-tap FIR filter Our implementation is a 5-tap transition filter: Easier to implement and very nearly as effective 11 May 12, 1997

12 Multiplexed Transmitter Out+ Out- (4Gb/sec) 5 Filter 6 DAC φ 0 D 0-9 (400MHz) Retiming & Distribution 5 5 Filter Filter 6 6 DAC DAC φ 3 φ 1 φ 2 DLL Clock Generator Clock (400MHz) 5 Filter 6 DAC φ 9 φ 0 D May 12, 1997

13 Transmitter Equalization Filter & DAC 5 Filter 6 φ n DAC φ n+1 D n H 0-2 L 0-2 H 0 L 0 H 1 L 1 X1 Driver X2 Driver φ n ("On" Clk) D n-1 D n-2 D n-3 D n-4 Find-first-one Logic 5x3-bit RAM H 2 L 2 φ n+1 ("Off" Clk) H k X4 Driver Out+ φ n+1 ("Off" Clk) Out- L k φ n ("On" Clk) 13 May 12, 1997

14 Receiver with Tracking Clock Recovery Adjustable Terminator In+ In- Demultiplexing Receiver D 0-9 Retiming & Framing Latches E 0-9 Clock Control 20 R 0-19 Funnel Shifter Out Clock (400 MHz) 20-Phase Clock Generator 14 May 12, 1997

15 Demultiplexer φ 0 D -1 E 0 φ In+ φ φ Out+ In- Out- In+ In- + - φ 1 φ 2 D 0 φ + - φ 3 E 1 In{+,-} φ 0 φ 1 φ E 9 φ 3 φ 4 φ D 9 250psec φ May 12, 1997

16 20-Phase Tracking Clock Generator D -1 Clock Control Tran Up 0 Common-Mode VoltageAdj. D 0 E 0 D 8 Late Dn 0 Up 9 Analog Summer Up 0 Dn 0 Dn 0 φ 2 φ 2 φ 2 φ 2 D 9 Dn 9 Up 0 E 9 P{+,-} φ 0 φ 1 φ 2 φ MHz P+ P- Phase Shifter DLL PD 20-Phase Clock Generator 16 May 12, 1997

17 Clock Generator Details P+ P- φ 0 φ 1 φ 11 φ 2 φ 12 φ φ 20 x Buffer Buffer Buffer Buffer Clk+ δ δ δ δ δ Interp Clkδ δ δ δ δ x x δ Phase Det & Filter Rep Bias Phase Shifter Delay-Locked Loop 17 May 12, 1997

18 Test Chip #1 Serial Scan Path Framer ROM RAM LFSR Latches F F F DAC DAC DAC Clk Gen Demux LFSR Chkr On-Chip Samplers Error Serial Scan Path On-Chip Samplers 400MHz PECL Clock Gen 18 May 12, 1997

19 Test Chip Waveforms Equalization Turned OFF Equalization ON Near Far Eye Diagram 19 May 12, 1997

20 Conclusions Scaling of Gates (50%/year) much faster than I/O pins (12%/year) Can afford to spend 00s of transistors for each off-chip signal Can & should clock off-chip signals faster than on-chip clock (not slower!) Today, relatively easy to signal at 1Gb/sec Differential Current-mode On-chip termination Per-signal clock recovery Use all those transistors to attack fundamental problems Inter-symbol interference due to skin-effect frequency-dependent attenuation Echo cancellation? Simultaneous bi-directional signaling? > 1 bit / clock? 20 May 12, 1997

21 Future Work New test chip Fall 1997 N-way muxing transmitters with lower N Simpler transition filters (5 elements probably more than needed) Compare oversampling with tracking clock recovery Alternative timing circuits Coding and error correction strategies Exportable 1Gb/sec version in 0.5µ CMOS 21 May 12, 1997

22 In what year, and why, will optical interconnect become the dominant technology in high performance digital systems for lengths > cm? Interconnect Length > M : Already the dominant technolgy Interconnect Length 1-M : Electrical and Optical Signaling Both Contenders Launch Cost Cable Cost Isolation Optical High Low Easy Power/Area High Electrical Low High Difficult Low Current work rapidly reducing optical signal launch costs, so may become the dominant inter-cabinet signaling technology soon May 12, 1997

23 Distances < 1M?? Today's 2nd-level packaging paradigm: board delivers power, provides signal interconnect; heat removed above board Signal scaling properties: Power Heat Chip-to-chip signaling Signal pins/chip Signaling speed Power per signal Signal width/pitch Length for Attn=0.5 (Aggressive) 1997 Scaling (pairs) 1.12/year 0Mb/sec 1Gb/sec 1.14/year 50mW 0.8/year 5mW 125/250µ 40/0µ 0.94/year (pairs) 400Mb/sec 4Gb/sec 60/120µ 20/50µ ~ 1M ~ 0.2M Conventional Aggressive

24 Distances < 1M?? To replace electrical signaling with optical will require: Optical Signals? Power? Heat Electrical Signals? Graceful way to deliver electrical power and (legacy) electrical signals to the top of composite chips (combine with SEEDs processing?) and get heat out the bottom. Build entirely new design-flow infrastructure, replacing well-established infrastructure for electrical signaling: Mixed-technology design Simulation Test Develop some way to emulate PC-board wiring in the optical domain (this may be an opportunity--processing in the optical domain??)

25 Distances < 1M?? Optical 'Backplanes' Daughter-card/Backplane paradigm provides interconnection density that scales only linearly Connector pin density scaling even more slowly than board signals Long routs to edge of card, then back; impedance discontinuities; expense; reliability; etc., etc. (litany of connector woes) Optical interconnect provides another dimension to rout in Energetically very favorable; potentially very high signal density Don't have to solve all of the optical interconnect problems at once! Could become an important technology within years??

26 Recent Progress Transmitter Pre-Emphasis 1.06Gb/sec) - LSI Logic Fiedler, A., R. Mactaggart, J. Welch, and S. Krishnan, "A Gbps Transceiver with 2x-Oversampling and Trasnmit Signal Pre-Emphasis", ISSCC97, pp Gbps Signalling - Yang & Horowitz, Stanford Univ Private correspondence Tracking Clock Recover - Symbios Logic, Inc. Chen, D-L, and M. Baker, "A 1.25Gb/s 460mW CMOS Transceiver for Serial Data Communications," ISSCC97, pp May 12, 1997