Abstract. High-Speed Transceiver Design in CMOS using Multilevel (4-PAM) Signaling.

Transcription

1 Abstract JOSEPH, BALU High-Speed Transceiver Design in CMOS using Multilevel (4-PAM) Signaling. (Under the direction of Dr. Wentai Liu) The design of a 4 Gbps serial link transceiver in 0.35µm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming mw of power from a 3.3 V supply.

2 HIGH-SPEED TRANSCEIVER DESIGN IN CMOS USING MULTI-LEVEL (4-PAM) SIGNALING by BALU JOSEPH A thesis submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the Degree of Master of Science ELECTRICAL ENGINEERING Raleigh 2002 APPROVED BY: Dr. Gianluca Lazzi Dr. Rhett Davis Dr. Wentai Liu, Chair of Advisory Committee

3 Biography Balu Joseph was born in Trivandrum, India, in He graduated with a Bachelor of Technology (B.Tech.) degree in Electronics and Communication Engineering from the Regional Engineering College (REC), Calicut, India, in July After graduation, he worked as a Senior VLSI/System Design Engineer with Wipro Technologies, Bangalore, India, from July 1998 to July He then joined the masters program in Electrical Engineering at North Carolina State University, Raleigh, NC, in August 2000 and worked on his thesis under the guidance of Dr. Wentai Liu. Since May 2001, he has also been working with the Analog & Mixed-Signal Design group of IBM Microelectronics, RTP, NC, on high-speed transceiver design. ii

4 Acknowledgements This work would not have been possible without the support and encouragement of several people. First and foremost, I would like to express my sincere gratitude to my advisor Dr. Wentai Liu for introducing me into the area of high-speed transceiver design and for his guidance, support and constant encouragement. I like to thank him for the confidence he had in me and for giving me the opportunity to work independently. I am also grateful to the other members of my advisory committee, Dr. Gianluca Lazzi and Dr. Rhett Davis, for reviewing my thesis, and for their valuable comments and suggestions. My association with the Analog & Mixed-Signal Design group of IBM Microelectronics has played a significant role in defining my work. I would like to thank Terry Sawyers, Brian Schuh and Clay Cranford for giving me the opportunity to work along with some of the best people in the field. My thanks are also to Mark Clements and Kasin Vichienchom, for taking time out of their busy schedules helping me and clearing my many doubts. I also like to thank all the members of ICAT for their support and encouragement. It is one of the best groups that I have worked with and it was really wonderful working with all of you. My thanks are also to Sandy Bronson for taking care of all my requests, especially during the thesis defense time. Finally, I would like to thank my parents, Celine and Joseph, for their unconditional love and constant support and my sister Teena for inspiring me to work hard. iii

5 Table of Contents LIST OF TABLES... VI LIST OF FIGURES...VII 1 INTRODUCTION Motivation and Contributions Organization of Thesis SIGNALING TECHNIQUES AND SYSTEM ARCHITECTURE Limiting Factors Band-limited Transmission Channel DC Attenuation Traveling Wave (AC) Attenuation Skin Effect Frequency-Dependent Dielectric Losses Electronic Limitations Signaling Techniques Full-swing Voltage-mode Signaling Low-swing Current-mode Incident-wave Signaling Modulation Scheme level Pulse Amplitude Modulation (4-PAM) Transmission Symbol Waveform Gray Coding Parallel I/O Architecture Channel Equalization TRANSCEIVER DESIGN Transmitter Multiplexing Driver Two-bit Digital-to-Analog Converter (DAC) Three-tap Pre-emphasis FIR Filter Receiver Receive Sampler Two-bit Analog-to-Digital Converter (ADC)...51 iv

6 Data Recovery Phase Tracking vs. Over-sampling Data Recovery x Over-sampling Data Recovery Architecture MULTI-PHASE CLOCK GENERATION Charge Pump PLL Phase Noise in PLL s PLL Building Blocks Stage Differential Voltage Controlled Ring Oscillator Differential Symmetric Buffer Stage Replica-feedback Current Source Bias Circuit Phase-Frequency Detector (PFD) Zero-Offset Differential Charge Pump Self-Biased Phase-Locked Loop Duty-Cycle Corrector SIMULATION RESULTS Cable and Package Models Transceiver Simulation Results PLL Simulation Results Performance Summary CONCLUSION AND FUTURE BIBLIOGRAPHY APPENDIX v

7 List of Tables Table 5.1: Transceiver Power Dissipation Distribution...95 Table 5.2: PLL Power Dissipation Distribution Table 5.3: Performance Summary vi

8 List of Figures Figure 2.1: Lumped RLCG model of a Transmission line... 5 Figure 2.2: Response of a lossy line to a unit step as a function of distance... 7 Figure 2.3: Pulse response of a band-limited co-axial cable Figure 2.4: Eye-diagram illustrating timing budget Figure 2.5: Received-voltage waveform for CMOS transmission system Figure 2.6: A point-to-point, low-swing, incident-wave system Figure 2.7: A 4-PAM eye-diagram with finite transition times Figure 2.8: Linear vs. Gray-code mapping of levels Figure 2.9: An N:1 multiplexing and 1:N de-multiplexing scheme Figure 2.10: Frequency response of a band-limited transmission channel Figure 2.11: High-Frequency attenuation effect on an isolated pulse Figure 2.12: Block-Diagram of an Equalized Line Figure 2.13: Frequency Response of an Equalized line Figure 2.14: Transmitted and Received Waveforms without Equalization and with Equalization Figure 3.1: Top-level Architecture of the Transceiver Figure 3.2: Top-level Architecture of the Transmitter Figure 3.3: Timing Diagram of the Retiming Block Figure 3.4: A simple 6:1 Multiplexer Figure 3.5: High-Speed Multiplexing structure Figure 3.6: Pre-charged AND gate implementation Figure 3.7: High-speed 6:1 Multiplexer Figure 3.8: 2-bit Digital-to-Analog Converter (DAC) structure Figure 3.9: Transient pulse-response of a band-limited channel Figure 3.10: Full Transmit Driver module with 3-tap FIR Pre-emphasis Filtering Figure 3.11: Timing Diagram of Transmit Driver with 3-tap FIR pre-emphasis filtering.. 42 Figure 3.12: Top-level Architecture of the Receiver Figure 3.13: Receive Data Sampling Timing Diagram Figure 3.14: Eye-diagram showing Time and Voltage Offset and Resolution Figure 3.15: Clock Feed-through in a Sampling circuit Figure 3.16: Charge-injection and Clock feed-through suppression through Dummy Switch addition Figure 3.17: High-speed Differential Sampler with Charge-injection and Clock feed-through suppression Figure 3.18: 2-bit Analog-to-Digital Converter Figure 3.19: 3-stage Comparator setup Figure 3.20: Gate-isolated Regenerative Amplifier Figure 3.21: Thermometer-to-binary Decoder Figure 3.22: Timing Jitter Figure 3.23: Data Recovery Architectures: (a) Over-sampling (b) Phase-tracking PLL vii

9 Figure 3.24: Different transition types with Differential 4-PAM signaling Figure 3.25: Transition Detection Logic Figure 3.26: Data Selection Algorithm Figure 3.27: Data Selection Logic Figure 3.28: Full Receive Data Path Figure 4.1: Charge-pump PLL Figure 4.2: Addition of a Zero to a Charge-pump Figure 4.3: Addition of Zero by means of Feed-forward Figure 4.4: Block diagram of a PLL with Noise sources Figure 4.5: Differential Buffer Delay stage with Symmetric loads Figure 4.6: Replica-feedback Current-source Bias circuit Figure 4.7: 9-stage Differential VCO with Symmetric loads and Replica- biasing Figure 4.8: I-V Characteristics of the Symmetric Load Figure 4.9: Composite Linear Transfer Characteristic of a Symmetric Load Figure 4.10: Phase-Frequency Detector Figure 4.11: Offset-cancelled Charge-pump with Symmetric Loads Figure 4.12: Transformation of the Loop-filter for the integration of the Loop-filter Resistor Figure 4.13: Complete Block Diagram of the Self-biased PLL Figure 4.14: Duty-Cycle Corrector Figure 5.1: Frequency Response of the 1-meter GETEK Backplane model Figure 5.2: Package Model Figure 5.3: Transmit and Receive Waveforms without Equalization Figure 5.4: Receiver Data Eye-Diagram without Equalization Figure 5.5: Transmit and Receive Waveforms with Equalization Figure 5.6: Receiver Data Eye-Diagram with Equalization Figure 5.7: VCO Characterization Figure 5.8: Bode-plot of PLL Open-loop response Figure 5.9: VCO Control Voltage Figure 5.10: PFD Input-frequencies when PLL is Locked Figure 5.11: PLL Clock Jitter ps (p-p) viii

10 1 Introduction 1.1. Motivation and Contributions With the exponential growth in speed and integration levels of integrated circuits (ICs), the inter-connection bandwidth between chips is becoming the major performancelimiting factor with modern digital systems. Applications such as computer-to-computer or computer-to-peripheral interconnections are requiring gigabit-per-second data rates over different distance ranges [5]. Traditionally, system designers addressed this issue by increasing the number of high-speed signaling lines, resulting in increased system cost and complexity. But to maintain a balanced system, the per-pin interconnection bandwidth must scale with the speed and integration levels of IC s [18]. Most digital systems today use full-swing, unterminated signaling methods that are unsuited for data rates over several hundred Mbps. Even good current-mode signaling methods with matched terminations and carefully controlled line and connector impedance are limited to about 1 Gbps by the frequency-dependent attenuation of copper lines [3]. These factors necessitate the need for new approaches to high-speed signaling for achieving multi-gbps data rates. 1

11 There are two distinct communication channels for high-speed point-to-point communication channels: optical fibers and copper cables. While optical fibers provide a large communication bandwidth over very long distance, the fiber, necessary optical components and terminal electronics makes this approach costly and area-inefficient. On the other hand, copper cables suffer from a very limited data bandwidth that decreases with length. But since it s a much cheaper solution, they are an attractive solution for short distance applications. High-speed links in the Gbps ranges have been traditionally implemented in GaAs or bipolar technologies. The primary advantage provided by these technologies is a faster intrinsic device speed (higher f T ), but they achieve only limited levels of integration. On the other hand CMOS, despite its slower device speed, is becoming the target technology of choice for high-speed integrated systems due to its widespread availability and higher integration levels possible. Also, the speed of CMOS technology is improving faster than the speed of other technologies, because of the extensive investment and momentum in CMOS technology developments [18]. These factors make high-speed links built in CMOS very attractive for large-volume applications. This thesis explores various signaling techniques and circuit architectures for a lowcost high-speed serial link in CMOS technology with the objective of maximizing the operating bandwidth and transmission distance. This work demonstrates the possibility of building a high-speed serial link transceiver in 0.35-µm CMOS technology, achieving 4Gbps data transmission rates over a band limited channel, with a 3-dB bandwidth of 275 MHz (Figure 5.1). 2

12 1.2. Organization of Thesis Chapter 2 discusses the signaling techniques and system architecture for achieving Gbps data rates with CMOS technology. The circuit design of the transmitter and receiver as well as data recovery is covered in Chapter 3. Chapter 4 looks into the low-jitter multiphase clock generation circuits. The simulation results are presented in Chapter 5. Chapter 6 summarizes the thesis and proposes future work. 3

13 2 Signaling Techniques and System Architecture The factors limiting the maximum data rate of a signaling system are the electronics used to generate and receive the signal and the medium over which the signal propagates. The speed limitations are set by the maximum operating frequencies intrinsic to the transistors and the bandwidth limitations of the transmission channel. The on-chip signaling rates improve with process technologies, thereby following the Moore s law curve. But the transmission channel bandwidth improves at a much slower pace, thus becoming the main bottleneck for the improvement in signaling speed. To overcome these limitations, this thesis looks at two areas: (1) dealing with the impact of the band limited transmission channel, and (2) transmission of more complex symbols (4-PAM), to increase the number of bits per symbol Limiting Factors The two factors limiting the maximum data rate in a signaling system are the bandwidth limitation of the transmission medium and the limitations of the electronics used to transmit and receive the data signals. 4

14 Band-limited Transmission Channel Figure 2.1: Lumped RLCG model of a Transmission line PC board traces, coaxial, twisted-pair and similar band-limited mediums behave as transmission lines that store and propagate signal energy. These lines can be modeled by a series of lumped RLCG elements as shown in Figure 2.1 [2]. The transmission loss is primarily due to the series resistive component of the conducting channel (R) and parallel conductive component of the dielectric (G). The resistance in conductors and the conduction in dielectrics attenuate the traveling wave and give a response that is a hybrid of the traveling wave of the LC line with the diffusive response of an RC line. Further, the skin effect causes the series resistance of the line to vary with frequency and dielectric absorption causes the conductance of the line to vary with frequency, both effects resulting in increased attenuation at higher frequencies and inter-symbol interference, thereby reducing noise and timing margins [2] DC Attenuation The dc loss depends primarily on two factors: the resistivity of the conductor and the total area in which the current is flowing. At dc, the current flows through the entire cross 5

15 section of the conductor, and the resistive loss can be found using the equation: ρl R = Ω [2.1] A where R is the total resistance of the line, ρ the resistivity of the conductor material in ohm-meters, and A the cross-sectional area of the signal conductor [24]. Since the dielectric materials used in the transmission channels are not perfect insulators, there is a dc loss associated with the resistive drop across the dielectric material between the signal conductor and the reference plane. The dielectric losses at dc for conventional substrates, however, are usually negligible and can be ignored Traveling Wave (AC) Attenuation Above a cutoff frequency, f 0 = R 2πL, the amplitude of a traveling wave, V i (x) at any point x along a transmission line with characteristic impedance, Z 0, is given by: Vi( x) Vi(0) = exp [-(α R + α D ) x] [2.2] where α R = R and αd = 2Z 0 GZ 0 2. Thus, the amplitude of a traveling wave is reduced exponentially with distance along the line with attenuation factors α R and α D, due to conductor resistance and dielectric loss respectively, and the line looks like an LC line with a fixed resistive attenuation per unit length, independent of frequency. However, below the cutoff frequency, f 0, the line looks like an RC line with a low-pass frequency response that rolls off linearly with frequency. 6

16 Figure 2.2: Response of a lossy line to a unit step as a function of distance The response of a lossy line to a unit step as a function of distance x, is given in Figure 2.2 [2]. At each point x, along the line, the response is a step to an amplitude of, exp [-(α R + α D ) x] [2.3] the amplitude of the traveling wave at point x, followed by a diffusive relaxation to the steady-state value at point x. This dispersive relaxation has a time constant that is proportional to the square of the distance x, along the line and is due to the low-pass frequency response of the line at frequencies below the cutoff frequency, f 0. The difference between the AC (traveling wave) attenuation and the DC attenuation, along with the long tails of the response due to the diffusive relaxation, results in significant inter-symbol interference. The situation is made worse by the frequency-dependent nature of wire resistance and dielectric absorption of the channel medium. 7

17 Skin Effect At high frequencies, the current flowing in a conductor will migrate toward the periphery or skin of the conductor, the phenomena being called skin effect. Skin effect manifests itself primarily as resistance and inductance variations. At low frequencies, the resistance and inductance assume dc values, but as frequency increases, the crosssectional current distribution in the transmission line becomes non-uniform and moves to the exterior of the conductor. The changing current distribution causes the resistance to increase with the square root of frequency and the total inductance to fall asymptotically toward a static value called the external inductance, the inductance value calculated when it is assumed that all the current is flowing on the exterior of the conductor [24]. High-frequency current primarily flows on the surface of a conductor with current density falling off exponentially with depth into the conductor. The current density at a depth d inside the conductor is given by, J = exp (- δ d ) [2.4] where, δ, is the skin depth, the depth where the current has fallen off to exp (-1) of its normal value. The skin depth is given by, 1 δ = [2.5] πfµσ where σ = ρ 1 is the conductivity of the material, and f is the frequency of the signal. The skin effect does not affect a conductor unless the frequency of the signal is above a 8

18 frequency, f s, given by: f ρ s = 2 πµr [2.6] where the skin depth is equal to the radius of the conductor, r. Below this frequency, all of the area of the conductor is carrying current, and the wire has a constant DC resistance, R DC. Above this frequency, the resistance increases with the square root of frequency. The resistance at a freq, f, above f s, is given by: R (f) = R DC 2 f f s [2.7] The frequency-dependent attenuation due to skin effect low-passes the traveling wave above the frequency, f s, giving a step response with an increased rise time and a tail that extends to 1, where f 1 is the unity-gain frequency. This dispersion of the waveform f 1 leads to inter-symbol interference as the tails of the responses to past symbols on the line interfere with new symbols placed on the line, thus affecting timing margins Frequency-Dependent Dielectric Losses With some insulating materials, dielectric absorption also causes frequency dependent attenuation. This loss can be modeled as a conductance G between the signal wire and ground. Dielectric losses for printed circuit board materials are generally much higher than for cables. Dielectric loss for materials are usually expressed in terms of the loss tangent, tan δ D, defined as [2]: 9

19 G tan δ D = ωc [2.8] where C is the capacitance per unit length as shown in Figure 2.1. This quantity is approximately constant with frequency, therefore the dielectric loss, G, typically increases linearly with frequency. The attenuation factor, α D, due to dielectric loss can be written as, α D = πf tan δ D LC [2.9] Figure 2.3: Pulse response of a band-limited co-axial cable Figure 2.3 shows the time-domain response of a band-limited channel to an ideal square pulse. The pulse suffers more attenuation of its high-frequency components, transitions, than its low-frequency components. The attenuation above the signal frequency causes the output amplitude to be severely attenuated. The attenuation of the lower frequency components, result in the long settling tail. The long settling tail causes inter-symbol interference, corrupting future transmitted symbols, resulting in reduced 10

20 timing and noise margins. Because of this effect, transmission without equalization is usually limited to frequencies with attenuation of 2dB or less. Thus, un-equalized transmission requires extremely high quality cables, resulting in increased system cost Electronic Limitations Figure 2.4: Eye-diagram illustrating timing budget Figure 2.4 shows an eye-diagram, illustrating the limits of bit time for a transmission module [2]. The three waveforms represent the typical, best-case and worst-case scenarios. The signaling limits arises from three major components, timing uncertainty (timing-jitter), t jt, the time difference between the early and late waveforms, aperture (sample) time, t ap, the time it takes for the receiver to sample the signal while it is stable, and the transition time, t tr, the time required for the signal to switch states. The symbol time, t sym, must be large enough to account for uncertainty, aperture, and transition time, as expressed by: 11

21 t sym t jt + t ap + t tr [2.10] The aperture time of receiver circuits can be made quite small by employing clocked amplifiers like gate-isolated sense amplifier [2]. The timing-jitter is caused by jitter in the sampling clock, jitter in the receiver clock, and delay variations in the signal path. Although factors such as inherent device noise (e.g. thermal and flicker noise) sets the lower limit of jitter, in most practical systems, the jitter is primarily due to power-supply modulation of delay, and cross-talk induced delay variations. However, both these factors scale with delay and hence with minimum process gate-length. In a low-swing currentmode signaling scheme, Figure 2.6, the transition time, t r, is determined by the time it takes to turn on and off a current source completely. Typically, the RC time constant of the terminated line, driver combination ~[(50Ω 50Ω) 1pF] is smaller than the signal transition time, thus effectively not limiting the minimum transition time. Therefore, the signal transition time still scales up with process improvements. In addition, the maximum data rate has a practical limit set by the maximum on-chip clock period, which in turn is determined by the bandwidth of the clock buffer chain. Due to the limited bandwidth of the clock buffers, propagating a clock with frequencies above the bandwidth causes the clock amplitude to reduce, thus imposing a limit on the maximum possible clock frequency. However, a parallel multi-phase I/O architecture, as described in Section2.4, can generate and sample multiple bits in one clock period, thereby relaxing the clock frequency constraint on the link bit rate. 12

22 2.2. Signaling Techniques This section describes two different approaches to high-speed signaling in digital systems. The first method is conventional supply-referenced, voltage-mode, full-swing signaling, such as TTL or CMOS transmission system. This conventional method has been inherently limited to maximum frequencies of ~100MHz and these frequencies have not scaled with improving process technology. As the speeds in modern digital systems increases, this conventional method of signaling is therefore becoming a major bandwidth bottleneck. The second method is, low-swing, current-mode, point-to-point, incidentwave signaling. This does not suffer from the inherent limitations of the conventional method, and thus its data rate can scale with process technology Full-swing Voltage-mode Signaling Traditional full-swing voltage-mode signaling systems are limited to data rates of about 100Mbps per wire and dissipate large amounts of energy per bit transmitted. In conventional CMOS systems, a CMOS inverter is used both as the driver and the receiver. The transmission medium typically has a characteristic impedance of 50Ω to 100Ω. The driver uses the two supply voltages to represent a 1 and a 0, respectively, and has an output impedance of ~200Ω and the line is unterminated at the receiver. The receiver is a CMOS inverter that compares the received voltage with a power-supplyderived reference. 13

23 A traditional full-swing, 3.3-V, CMOS system is power hungry, dissipating 1nJ or more signal energy per bit, because its line is not terminated or clamped to some intermediate voltage and is using rail-to-rail signal swings for transmission. Also, the CMOS driver, because of its high output impedance (~200Ω), is unable to drive its full output swing onto the line in one step as a single incident wave, but has to wait several round-trip times for the line to ring up to the full voltage as shown in Figure 2.5 [2]. Figure 2.5: Received-voltage waveform for CMOS transmission system This effect causes the maximum allowable length of the interconnections to decrease linearly as the data rate increases, even in a lossless wire. In addition to increasing delay, this ringing up of the line also seriously degrades the noise immunity of the CMOS system for two reasons. First, transient noise may cause spurious multiple transitions across the detection threshold while the line is at an intermediate voltage. This increases power dissipation and causes logical errors on edge-sensitive lines such as clocks. 14

24 Second, because the line is unterminated, continuing reflections of one transition interfere with subsequent bits on the same line. Further, since the receiver uses noisy powersupply derived reference threshold voltages, a large input signal swing is required to overcome the large reference noise Low-swing Current-mode Incident-wave Signaling Good signaling performance requires incident-wave switching [2]. The first wave arriving at the receiver after a signal transition must be of sufficient amplitude to be detected reliably, and there should be no significant reflections or oscillations. This gives a wire delay equal to the time-of-flight over the wire. To achieve incident-wave switching requires control of the signal transition and matched terminations to eliminate reflections. Figure 2.6: A point-to-point, low-swing, incident-wave system A low-swing point-to-point incident wave signaling system is shown in Figure 2.6. A current-source transmitter drives the line with currents, typically of the order of a few milli-amperes, resulting in a voltage swing range of 100mV to about 1V. The line is terminated at both ends in its characteristic impedance. The receiver termination absorbs 15

25 the incident wave, preventing any reflections. The source termination makes the system more tolerant to cross-talk and impedance discontinuities by absorbing any reflected waves. A clocked, differential regenerative receive amplifier, which possess both low offset ~(30-60mV) and high gain, is used to sense the voltage across the termination resistor. The signal and the signal return are both isolated from the power-supply noise, making any supply noise common-mode to the differential receiver. Thus although the signal levels are less, thus resulting in lower noise-margins, it has better noise immunity Again, since the low-swing current-mode system uses signal levels with much lesser energy, it dissipates lesser power. Finally, since a low-swing system switches the receiver with the first wave that traverses the transmission line, thereby achieving incident-wave switching, it can operate at data rates independent of the line length. A new symbol can be driven onto the line before the previous symbol arrives at the receiver. This results in a system whose data rate, scales linearly with process improvements 2.3. Modulation Scheme A higher transmission rate is possible through a band-limited transmission channel by using complex symbols, representing multiple bits during each symbol-time. Although many modulation schemes can be used, multi-level pulse amplitude modulation (M- PAM) scheme is used in this work due to its simplicity, and higher bits/hz compared to 2-PAM (binary). As signaling frequency approaches the bandwidth of the transmission medium and circuitry, M-PAM signaling becomes more relevant, since it has smaller 16

26 signal bandwidth and larger symbol period than binary signaling for the same data rate. The larger symbol period results in an improved timing margin and reduced signal attenuation level Pulse Amplitude Modulation (4-PAM) Figure 2.7: A 4-PAM eye-diagram with finite transition times The channel bandwidth required for a given bit rate can be reduced by transmitting multiple bits in each symbol time. In an M-PAM signaling scheme, each symbol conveys log 2 (M) bits of information. For a given data rate, M-PAM modulation reduces the effective symbol-rate by a factor of log 2 (M) compared to a binary signaling system. The reduced symbol rate results in reduced inter-symbol interference in the channel and reduced on-chip frequency requirements. However, the more complex transitions to multiple levels, together with finite signal transition times, prevent the data eye-width from scaling by log 2 (M). Figure 2.7 illustrates this condition [18]. At the same time, the 17

27 eye-height for 4-PAM signaling is effectively reduced only by a factor of two, instead of being reduced by a factor of three (as there are three eyes), since there is less attenuation in the channel for the lower frequency 4-PAM signal than for the higher frequency 2- PAM signal. The signaling scheme used here is differential 4-level PAM, which reduces the symbol rate by a factor of two compared to binary signaling. For a fixed transmitter signal swing budget, the spacing between adjacent levels decreases with increased number of signaling levels. For an M-level PAM system, the signal spacing between adjacent levels is given by: Signal Level Spacing = TransmitterSwingBudget M 1 [2.11] The smaller the spacing between signal levels, the more vulnerable the signal will be to noise and cross-talk from other high-speed signals in the system. Again, reflection interference of large signals due to imperfect terminations and line discontinuities can overwhelm subsequently transmitted low-level signals. Hence 4-PAM signaling is used here, to avoid the low-amplitude symbols that result from a higher order PAM system, which can significantly increase the bit error rate. Further, the differential nature of the signaling improves the system performance by eliminating common-mode noise and increasing the total signal swing by a factor of two, when compared to single-ended signaling. 18

28 Transmission Symbol Waveform The transmission waveform used in this work is the simple trapezoidal pulse, with a period equal to the inverse of the symbol rate. Although using a trapezoidal pulse results in severe inter-symbol interference, thereby limiting the maximum data rate possible, it can be generated and detected with modest complexity using symbol-to-symbol detection. In this scheme, the inter-symbol interference effects are reduced through the use of multi-level signaling (Section2.3.1), and channel equalization (Section2.5). For optimal detection of these trapezoidal pulses, matched filters [1] should be used. Matched filters integrate the energy of each symbol over its duration, and therefore results in maximum signal-to-noise ratio. But, matched filter detection does not improve the system performance considerably, unless the received signal levels are very small (<1mV), while significantly increasing system complexity. As a result, to reduce the complexity of the design, hard detectors are used to sample the data pulses in the receiver, without matched filtering of the waveforms Gray Coding Since 4-PAM hard decision decoding is used in the receiver, a fixed one-to-one mapping of every two input bits to a constellation point must be chosen. Six distinct mapping exists for 4-PAM. However, only a Gray-code mapping, Figure 2.8, guarantees that every nearest symbol error results in only one bit of error. Thus, the bit error rate is reduced compared to the linear mapping [5]. Another advantage with gray coding is the ease of communication in 2-PAM mode. If the LSB is set to zero in the transmitter, and 19

29 the LSB is ignored by the receiver, the signaling levels become 2-PAM. This feature allows for convenient communication with 2-PAM devices at lower bandwidth [12]. Figure 2.8: Linear vs. Gray-code mapping of levels 2.4. Parallel I/O Architecture The on-chip clock frequency limitations, generally restricts the maximum attainable data transmission rate. One way of overcoming the on-chip frequency limitations to achieve higher data transmission rate, is to transmit more than one bit per clock cycle. The simplest way of doing this is to use a half-rate design. The transmitter in such a system, do a 2:1 multiplexing, sending two bits per clock cycle, one on each clock edge. The receiver do a 1:2 de-multiplexing on the received serial data stream, so that the digital logic following the receiver front-end stage need to operate only at half-rate. The bandwidth limitations of the multiplexer, minimum cycle time of the receive sampler, and the duty cycle accuracy of the clocks, generally set the upper limit on such a system. A duty cycle difference in the transmitter clock will result in the odd and even bits being of unequal width. Similarly a duty cycle error in the receiver clock will result in the adjacent 20

30 bits not being sampled at the middle of the data-eye. Figure 2.9: An N:1 multiplexing and 1:N de-multiplexing scheme A higher degree of parallelism can be achieved by using an N:1 multiplexer in the transmitter and a 1:N de-multiplexer in the receiver, as shown in Figure 2.9. This helps in achieving a data transmission rate of N times the on-chip clock frequency [15]. The higher level of parallelism is achieved by making use of multi-phase clocks. Each input in the transmit multiplexer is selected by consecutive phases of the low-frequency clock. Similarly in the receiver, adjacent phases of the low-frequency clock samples the higher frequency data bits, each phase sampling a different data bit. Because of the longer clock periods, the minimum cycle time constraint on the receive sampler is relaxed. 21

31 However there are three factors that limit the arbitrary increase in parallelism. The increased capacitance at the multiplexer and de-multiplexer nodes start limiting the data bandwidth after a certain stage. The width of the select signals of the multiplexer need to be of the order of the transmission data bit width. Finally, the multi-phase clocks have to be precisely spaced to reduce jitter. All these requirements become increasingly difficult as the amount of parallelism is increased. The multiplexing ratio used in this design is six. Therefore, in each clock cycle six symbols are transmitted. Further, since 4-PAM signaling is used, each symbol carries two bits of information. Thus, effectively twelve bits of data are transmitted during each clock period Channel Equalization Figure 2.10: Frequency response of a band-limited transmission channel 22

32 As discussed in Section 2.1.1, factors like skin effect and dielectric losses causes the attenuation of a transmission channel to increase with frequency. The resulting frequency-dependent attenuation results in inter-symbol interference, as unattenuated low-frequency signal components overwhelm the attenuated high frequency components [3]. This interference degrades the noise margin and reduces the maximum frequency at which the system can operate. Figure 2.10 shows transmit and receive waveforms through a lossy channel [2]. The top trace shows the transmitted bit pattern while the bottom trace shows the received waveform. The unattenuated low-frequency component of the signal causes the isolated high-frequency pulse to barely reach the midpoint of the signal swing, giving no eyeopening and very little probability of correct detection. It s not the magnitude of attenuation, but the interference caused by the frequency-dependent nature of attenuation that s causing the problem. Although the high-frequency pulse has sufficient amplitude at the receiver for proper detection, the offset of the pulse from the receiver threshold due to low-frequency interference closes the data eye-opening. The problem is most severe with of an isolated pulse [2]. Figure 2.11 (a) shows that a high-frequency attenuation factor of A reduces the eye-opening height to 2A-1, with the eye completely disappearing at A 0.5. Again, since the waveforms cross the receiver threshold at an offset from the center of the signal swing, the width of the eye is also reduced. As illustrated in Figure 2.11Figure 2.11 (b), although the leading edge of the attenuated pulse crosses the threshold at the normal time, the trailing edge advances by t j = (1-A).t f, where, t f, is the signal fall time for the full amplitude. This data dependent 23

33 jitter, t j, causes greater sensitivity to skew and jitter in the signal or sampling clock and may introduce noise into the timing loop. Because the line does not reach a steady state after each bit, the residual history of previous bits affects the response of the line to the current bit. Figure 2.11: High-Frequency attenuation effect on an isolated pulse Frequency-dependent attenuation can be canceled by equalization. A block diagram of an equalized line is shown in Figure An equalizing filter in the transmitter has a transfer function, G(s), that approximates the inverse of the line transfer function, H(s). The concatenation of the equalizer and the line thus has a transfer function, G(s).H(s), 24

34 that approximates unity. Figure 2.12: Block-Diagram of an Equalized Line Figure 2.13: Frequency Response of an Equalized line 25

35 Figure 2.14: Transmitted and Received Waveforms without Equalization and with Equalization The frequency response of an equalized line [2] is shown in Figure The top curve shows the frequency response of the equalizer, G(s), the middle curve shows the 26

36 frequency response of the line, H(s), and the bottom curve shows the frequency response of the equalized line, G(s).H(s). This shows that across the frequency range from 100 MHz to 2GHz, the frequency response of the equalized line is flat to within a few percent. The effect of equalization in the time domain [2] is illustrated in Figure The curves on top show the waveforms without equalization while the curves on bottom show the waveforms with equalization. By pre-emphasizing the high-frequency components of the transmitted waveform, the frequency dependent attenuation of the lossy channel is canceled, resulting in a clean received waveform. In contrast to the original waveform, the lone pulses of the equalized waveform crosses the receiver threshold at nearly their midpoint, resulting in a large eye-opening and little data-dependent jitter. The channel equalization can be done at either the transmitter or at the receiver or as a combination of both. Its easier to do equalization at the transmitter since to do receiver-equalization, high-resolution analog-to-digital converters (ADC s) operating at the high data rate is required, which is a difficult design challenge with CMOS technology. Transmitter equalization can be done easily using symbol-spaced finite impulse response (FIR) filters integrated into the driver. The pre-shaped output waveform of such a filter is given by the equation: V o (N) = V i (N) - α.v i (N-1) - β.v i (N-2) - γ.v i (N-3) -.. [2.12] where α, β, γ represent the filter tap weights, V i (N) is the current input and V i (N-i) s are the previous inputs. The number of filter taps required depends on the number of past symbols that affect the current symbol. The filter co-efficients are determined by 27

37 characterizing the channel frequency response. The filter co-efficients can be either positive or negative based on the channel frequency response. The pre-shaped output of the filter is thus the sum of the present symbol with the weighted values of previous symbols, which are already available to the transmitter. In the simplest sense, the FIR filter effectively suppresses the power of low-frequency components by gradually reducing the amplitude of continuous strings of identical symbols, while keeping the power of the high-frequency components constant by increasing the signal amplitude during transitions. This chapter gave an overview of the limitations with conventional CMOS links and the bandwidth limitations of the transmission medium. It then discussed the different techniques to overcome these limitations, to achieve a higher data transmission rate. The implementation details of the transmitter and receiver are covered in the next chapter. 28

38 3 Transceiver Design This chapter deals with the architecture and circuit implementation of the transmitter and receiver portions of the transceiver. The transmitter uses a 6:1 multiplexing architecture to generate a 2Gsym/s stream from a MHz clock. The multiplexing driver has the 2-bit DAC s and 3-tap FIR pre-emphasis filter integrated into it. The receiver, similarly perform a 1:6 de-multiplexing at its front-end. Data recovery is done through over-sampling the data. Each symbol is sampled three times, with clocks spaced apart by one-third the symbol time. The multi-phase clock generation portion of the transceiver is covered in the next chapter. The top-level architecture of the transceiver is given in Figure Transmitter Figure 3.2 shows the top-level architecture of the transmitter. The transmitter uses a 6:1 multiplexing scheme to reduce the on-chip frequencies. Twelve bits of data are parallely clocked into the transmitter at MHz. The twelve bits of data are first latched at the input and then given to a retiming block. The retiming block divides the twelve bits of data into six groups of two bits each. Further, the six groups of data are 29

39 Figure 3.1: Top-level Architecture of the Transceiver 30

40 delayed appropriately by the retiming block, before being given to the multiplexing driver block. The timing of the six data pairs are adjusted by the retiming block to ensure enough set-up and hold time, with respect to the corresponding driving clock of the 6:1 multiplexing driver. The timing diagram of the retiming block is given in Figure 3.3 [18]. Figure 3.2: Top-level Architecture of the Transmitter 31

41 Figure 3.3: Timing Diagram of the Retiming Block Multiplexing Driver The multiplexing driver complex consists of six segments. Each segment has a main symbol driver and a 3-tap pre-emphasis FIR filter associated with it [5]. The 3-tap FIR filter is covered in Section The low-speed data present at each of the segment inputs is driven onto the output lines by the multiplexer successively, resulting in a high-speed stream. The basic structure of a 6:1 multiplexer is shown in Figure 3.4. In its simplest implementation, the width of the select signals of the multiplexer determines the maximum data output rate that can be achieved. The data-select signals have to be very sharp and narrow compared to the input data rate, of the order of the output symbol 32

42 width. Again the output node capacitance of the multiplexer increases with the fan-in. Thus these two factors generally limit the multiplexer bandwidth, by generating intersymbol interference at the output node. Figure 3.4: A simple 6:1 Multiplexer [25] explain that, a high-speed narrow pulse can be generated from two low-speed pulses, if the phase difference between the low-speed pulses is used to generate the narrow pulse. The pulse width is now determined by the phase-difference between the pulses, rather than their absolute value. Thus the select signal can be generated from two low-frequency clocks that are out-of-phase by the output symbol period, thereby avoiding high on-chip clock frequencies. The multi-phase clocks from the PLL (Section4) can be used for this purpose. 33

43 The output node capacitance of the multiplexer can be minimized by using an NMOS gate at the output stage, directly driving the output lines [3]. Because of the low output capacitance of the NMOS gate and the low impedance of the terminated line, this multiplexing structure can be very fast. The NMOS transistors should always remain in saturation to act as high-impedance current sources. So the transistors should be made large enough to support the required current with the minimum overdrive voltage. A high-speed multiplexing structure incorporating these two concepts is shown in Figure 3.5. The structure consists of a stacked set of NMOS gates, qualified by two clocks, clka and clkb. The rising edge of clka and the falling edge of clkb are out-ofphase by the output symbol period. The output symbol is generated for the time during which both the clocks are high, i.e., for the duration from the rising edge of clka to the falling edge of clkb. For a stacked set of gates, the critical signal, i.e., the signal that assumes a stable value last, clka, should be connected to the top set of gates in the stacked setup, since they are closer to the output [26]. The input to both the upper NMOS gates, D and D_ (the output of the two upper AND gates), are zero when clka is low, but when clka goes high, their value depends on the differential data signals, D in and D in _. The retiming block ensures that the data inputs, D in and D in _, are stable during the symbol formation. The rising edge of clkb, discharges the node, src, but current does not start flowing through the NMOS gate stack until the rising edge of clka. When clka goes high, one of the data inputs to the upper NMOS gates, D or D_, turns high and current for the symbol starts flowing through that branch until clkb goes low, after a symbol period, when the bottom NMOS gate is turned off. The differential output symbol, D out and D out _, 34

44 Figure 3.5: High-Speed Multiplexing structure are formed when this current flows through the termination resistance pairs, R T. An identical AND gate, with one of its input tied to the high supply voltage, is added to the bottom NMOS gate input to maintain the phase alignment between the data and the clocks. 35

45 Figure 3.6: Pre-charged AND gate implementation The output symbol boundaries are determined by the phase spacing between the clocks and the slew-rate of the signal inputs to the NMOS gates. Hence the main source of jitter and phase error in the transmitter are the clock and data signal paths. The PLL, which generates the clock phases (Section4), is designed to minimize jitter with supply and noise variations. To minimize the jitter and delay in the AND gates, they are implemented using pre-charged NAND gates [5] with its output buffered up using CMOS inverter stages, as shown in Figure 3.6. When compared to a regular NAND gate, a precharged structure has lesser output node capacitance, and its output transition is due to pull-down by the stronger NMOS devices. This results in sharper transition edges and minimum buffering delay, thus reducing jitter. 36

46 Figure 3.7: High-speed 6:1 Multiplexer Figure 3.7 shows the implementation of a 6:1 multiplexer, from the multiplexing structure described in Figure 3.5. The retiming block (Figure 3.3) provides the properly phased data inputs. The multi-phase clocks required are obtained from the PLL (Section4). Six successive data symbols are given to the six multiplexing blocks, with each block getting a different symbol. Each multiplexing block then drive the output lines successively with their corresponding symbols, thus generating the high-speed data at the output lines Two-bit Digital-to-Analog Converter (DAC) For the current-mode driver, the best choice for a fast, 2-bit digital-to-analog converter is a current summing architecture [5]. The DAC module consists of two differential driving legs, X1 leg and X2 leg, that are binary weighed, with the second leg, X2 leg, sized at double the size of the first leg, X1 leg. Each individual driving leg uses the same multiplexing driving structure shown in Figure 3.5, with each leg acting as a 37

47 current source. The DAC module has two input data bits, D1 and D2, both differential signals, with D1 going as input to the first leg and D2 to the other leg. The output current from each leg depends on its input data bit. The currents from the two legs are finally summed at the output to generate four current levels, based on the data inputs, D1 and D2. Figure 3.8 shows the structure of the 2-bit DAC. Figure 3.8: 2-bit Digital-to-Analog Converter (DAC) structure 38

48 Since the eye-opening height for a 4-PAM driver is reduced to one-third the value for a binary driver, care should be taken to minimize the factors causing mismatch and nonlinearity. For the 2-bit current summing DAC, the second leg of the DAC driver has to have double the current driving strength as the first leg. One way of implementing this is to double the transistor sizes in the second leg, with the inverter buffers following the pre-charged AND gates (Figure 3.6) correspondingly sized up. But this size difference causes mismatch between the two legs. The mismatch can be minimized by implementing the second leg as two copies of the first leg, with their inputs and outputs tied together (Figure 3.8). Further it should be ensured that the transistor current sources always operate in the saturation region, staying well out of the resistive region of operation. Otherwise they act as poor current sources, resulting in increased non-linearity Three-tap Pre-emphasis FIR Filter Figure 3.9: Transient pulse-response of a band-limited channel 39

49 The design of the transmit pre-emphasis filter is covered in this section. As discussed in Section2.1.1, due to the band-limited nature of the transmission channel, narrow pulses sent through the channel experiences long tails that extends into subsequently transmitted symbols, resulting in inter-symbol interference. Figure 3.9 illustrates this phenomenon [16]. The transient output response of the channel does not decay to zero at time t = 2T. The ratios α,β,γ define the ratio of the output signal amplitudes at times 2T, 3T, 4T respectively, to the output signal amplitude at time T. These extended signal responses causes ISI by superposition, i.e., by adding α times the value at time t = T to the value at time t = 2T, β times the value at time t = T to the value at time t = 3T, γ times the value at time t = T to the value at time t = 4T and so on. To minimize ISI, α times the value at time t = T should be subtracted from the value at t = 2T, β times the value at time t = T should be subtracted from the value at t = 3T, γ times the value at time t = T should be subtracted from the value at t = 4T and so on. The easiest way to achieve this ISI suppression is by using a symbol spaced multi-tap FIR filter, which significantly reduces the extended tail amplitudes. Since the tail amplitudes after 3 symbol times are insignificant, a 3-tap symbol spaced FIR filter is used for the pre-emphasis filtering in this design. Since a digital implementation of the FIR filter requires high-resolution digital-toanalog converters, multipliers and adders, an analog technique is used to realize the FIR filter. The 3-tap FIR filter is realized using the same DAC s and multiplexing structure discussed in Section3.1.2 and Section3.1.1 respectively. The structure of the full driver module with the 3-tap FIR filters is given in Figure Each one of the six driver 40

50 Figure 3.10: Full Transmit Driver module with 3-tap FIR Pre-emphasis Filtering sections now has three filter modules (DAC-Fi) in addition to the main module (DAC- M). The same data is given to the main module and the three filter modules. But they are turned on consecutively, symbol times apart, one at a time, using adjacent clock phases from the PLL (Section4) that are spaced apart by symbol times. 41

51 Figure 3.11: Timing Diagram of Transmit Driver with 3-tap FIR pre-emphasis filtering The differential output currents of the main module and the three filter modules are summed at the output, with the filter outputs connected with opposite polarity. The currents through the filter modules are controlled by a current mirror setup, setting the currents through the three filter modules to α,β and γ times the current through the main 42