OF the wide band gap (WBG) materials that are currently

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1 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 27, NO. 3, AUGUST Improved Performance of 4H-SiC PiN Diodes Using a Novel Combined High Temperature Oxidation and Annealing Process Craig A. Fisher, Michael R. Jennings, Yogesh K. Sharma, Dean P. Hamilton, Peter M. Gammon, Amador Pérez-Tomás, Stephen M. Thomas, Susan E. Burrows, and Philip A. Mawby, Senior Member, IEEE Abstract In this paper, the application of a novel combined high temperature thermal oxidation and annealing process to mesa-isolated epitaxial-anode 4H-SiC PiN diodes with thick (110 μm) drift regions is presented, the aim of which was to increase the carrier lifetime in the 4H-SiC. Diodes were fabricated using 4H-SiC material having undergone this process, which consisted of a thermal oxidation in dry pure O 2 at 1550 C followed by an argon anneal at the same temperature. Forward current-voltage characterization showed that the oxidised/annealed samples typically showed around 15% lower forward voltage drop and around 40% lower differential onresistance (at 100 A/cm 2 and 25 C) compared to control sample PiN diodes, whilst reverse recovery tests indicated a carrier lifetime increase also of around 40%. These findings illustrate that the use of this process is a highly effective and efficient way of improving the electrical characteristics of high voltage 4H-SiC bipolar devices. Index Terms 4H-SiC, PiN diode, high temperature oxidation, carrier lifetime. I. INTRODUCTION OF the wide band gap (WBG) materials that are currently being investigated for power electronics applications, 4H-silicon carbide (SiC) technology is the most advanced; this is a result of extensive research over the past twenty five years. However, in recent years, the WBG material gallium nitride (GaN) has seen great improvements in material quality and is a serious contender for future power electronics devices. Although 4H-SiC has a narrower band gap when compared to GaN, its thermal conductivity is vastly superior, making it more suitable for high power density applications, such as high voltage direct current (HVDC) power transmission. Furthermore, because GaN is typically grown on a substrate of Manuscript received January 24, 2014; revised May 8, 2014; accepted July 4, Date of publication July 16, 2014; date of current version July 30, This work was supported by the University of Warwick EPSRC Grant EP/I013636/1 and Grant EP/K035304/1, and has used cleanroom facilities funded by Advantage West Midlands and the European Regional Development Fund through the Science City Energy Efficiency project. C. A. Fisher, M. R. Jennings, Y. K. Sharma, D. P. Hamilton, P. M. Gammon, S. M. Thomas, and P. A. Mawby are with the School of Engineering, University of Warwick, Coventry CV4 7AL, U.K. ( craig.fisher@warwick.ac.uk). A. Pérez-Tomás is with the Institut Català de Nanociència i Nanotecnologia, Barcelona 08193, Spain. S. E. Burrows is with the Department of Physics, University of Warwick, Coventry CV4 7AL, U.K. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TSM different material (such as silicon (Si), sapphire or SiC), only lateral power devices are feasible. This effectively rules out the use of GaN power devices for applications above several kv in voltage, which require the use of vertical device structures with a thick epitaxial blocking layer. Finally, the direct band gap of GaN means it has a very short carrier lifetime, meaning GaN bipolar devices are infeasible. As such, 4H-SiC is widely tipped to be the successor to Si for high voltage power electronics [1]. For high voltage applications, the use of bipolar power devices, such as PiN diodes and Insulated Gate Bipolar Transistors (IGBTs), offer much-reduced on-state power losses when compared to their unipolar counterparts, Schottky diodes and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). This is due to the conductivity modulation effect, which serves to reduce the resistance of the thick, lowly-doped drift region that is required for blocking high voltages. This is achieved by the injection of carriers from adjacent device regions. However, the degree to which conductivity modulation reduces the resistance of the drift region, and hence the overall on-state power losses of the device, is heavily dependent on the carrier lifetime of the material. As an example, a device designed to block 10 kv requires a carrier lifetime of approximately 5 μs to ensure optimum conductivity modulation for minimum on-state losses [2]. Unfortunately, the carrier lifetime of as-grown 4H-SiC is considerably lower than this, with values less than 1 μs being typical [3]. As such, it is evident that a post-growth process to increase the carrier lifetime is required for these high voltage 4H-SiC devices. It is widely accepted that the carrier lifetime in as-grown 4H-SiC is predominantly limited by the presence of the carbon vacancy-related Z 1/2 defect center in the bulk material [4]. However, by employing a thermal oxidation process, the carrier lifetime of 4H-SiC has been found to be dramatically increased. This is due to the generation of carbon interstitials near the oxidising surface, which diffuse into the semiconductor bulk and effectively repair the carbon vacancy defects, thus increasing the carrier lifetime of the material [5]. Though this is an effective method of increasing the carrier lifetime of 4H-SiC, the use of conventional dry oxidation processes require very long oxidation times to eliminate the Z 1/2 defect center in the thick epitaxial layers needed for high voltage 4H-SiC devices, thus resulting in a significant increase in both the overall device processing duration and cost. For instance, c 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 444 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 27, NO. 3, AUGUST 2014 when performing the oxidation at 1300 C, the process takes over 50 hours when applied to a 100 μm thick epitaxial layer [6]. Furthermore, the thermal oxidation process is typically followed by a separate argon (Ar) anneal at 1550 Cfor 30 minutes to eliminate the HK0 defect center that is generated during the oxidation [7], adding further processing complexity and cost. It has been demonstrated that by performing the thermal oxidation at 1400 C, the rate at which the Z 1/2 defect center is eliminated in the semiconductor bulk is significantly increased, and was shown to correspond to an increased oxidation rate [6]. However, the oxidation times required were still fairly long, with 16.5 hours being required to eliminate the Z 1/2 defect center to a depth of 100 μm. Moreover, this was a material study and the process was not applied to a 4H-SiC semiconductor device. Nakayama et al. [8] compared the performance of thermal oxidation and carbon implantation [9] for carrier lifetime enhancement against standard processed 4H-SiC PiN diodes with 120 μm-thick n-type drift regions, and observed a considerable improvement in the forward characteristics of the lifetime-enhanced devices. However, the thermal oxidation process applied here was performed for 5 hours at 1300 C twice, thus adding considerable time to the overall fabrication process. By employing temperatures higher than 1400 C, the oxidation rate has been shown to increase significantly, meaning that oxidation times can be dramatically reduced [10]. The application of high temperature (up to 1600 C) thermal oxidation for improving the on-state performance of 4H-SiC PiN diodes has previously been investigated by the authors [11], and was found to improve the differential on-resistance (R on,diff )by around 25% compared to diodes fabricated without the thermal oxidation process. However, this work only focussed on the use of thermal oxidation for very short durations (up to 5 minutes), and without a subsequent Ar anneal process. An advantage of performing the thermal oxidation at 1550 Cis that it is possible to also perform an in situ Ar anneal for eliminating the HK0 defect center immediately after the thermal oxidation, simply by controlling the gas flow to the furnace tube. The use of this combined oxidation and annealing process not only reduces the process time required, but also minimizes the number of separate process steps involved, thus meaning that the overall cost and duration of the device manufacturing process is significantly reduced. In this paper, the application of this novel combined oxidation/annealing process on 4H-SiC PiN diodes with 110 μm thick drift regions is presented. The aim of this study is to investigate the electrical performance benefit that can be achieved by using this novel fabrication process by comparing against conventional PiN diodes fabricated using as-grown 4H-SiC material. To the best of the authors knowledge, this is the first time such a process has been applied to 4H-SiC PiN diodes. II. EXPERIMENT DETAILS A. Device Fabrication The substrates employed for PiN diode fabrication in this work were n-type Si-face 4 off-axis 4H-SiC. Substrates were 350 μm (±25 μm) thick, and had a resistivity of m -cm. An n-type buffer layer (0.5 μm at cm 3 doping concentration) was grown first, followed by the n-type drift region (110 μm at cm 3 ) and p-type anode (1 μm at> cm 3 ). A high anode doping concentration was used to facilitate thermionic field emission at the metal-semiconductor interface, in order to reduce the anode ohmic contact resistance. Epitaxial layers were grown in a continuous growth run to minimize the effects of interface recombination on the overall carrier lifetime of the devices [8]. Based on the drift region thickness and doping concentration, a parallel plane breakdown voltage of 17.1 kv was calculated based on the analytical solutions presented in [12]. After the epitaxial growth process, the epiwafer was laser-cut into mm dies for device fabrication. After laser-cutting, the dies underwent a solvent-based cleaning process consisting of acetone, isopropanol and methanol, each in an ultrasonic bath for five minutes. This was followed by an acid-based cleaning process consisting of 5% hydrofluoric acid (HF), Radio Corporation of America (RCA) standard clean 1 (SC1), 5% HF, RCA SC2, Piranha then a final 5% HF. The dies were rinsed in 18 M deionized (DI) water between each step and after the final step, then dried using nitrogen gas (N 2 ). After the cleaning process, half of the dies underwent the combined thermal oxidation/ar annealing process. In this process, the dies were ramped up to the oxidation temperature of 1550 Catarateof8 C/mininanAr atmosphere (5 l/min) where they were held for 15 minutes. The dies were then oxidised in dry pure oxygen (O 2 ) for 15 minutes at 1550 C, under an O 2 flow rate of 0.5 l/min. After the oxidation, the Ar flow was reinstated at 5 l/min, and the dies were held for an additional 30 minutes. After the Ar anneal hold, the dies were ramped down in temperature, again at 8 C/min, to 600 C, still in an Ar atmosphere. The thermallygrown SiO 2 was then removed in dilute HF solution and the dies rinsed in DI water. The next fabrication process was to define the active areas of the PiN diodes and isolate the individual anodes (mesa etch). In order to achieve good sidewall morphology, inductivelycoupled plasma (ICP) etching based on a SF 6 +O 2 chemistry has been employed [13]. For the mesa etch, masking layers of 1 μm tetraethyl orthosilicate (TEOS) SiO 2 and 250 nm nickel vanadium (NiV) were deposited by chemical vapor deposition (CVD) and sputtering respectively, then photolithography based on S1818 photoresist was used to define the mesa features. It was necessary to use both TEOS SiO 2 and NiV for the mesa etch mask to withstand the aggressive ICP etch whilst preventing micro-masking of the 4H-SiC surface which can arise from directly depositing metal onto the 4H-SiC [14]. The NiV was patterned in dilute Aqua Regia solution, then the photoresist was removed in acetone. The TEOS SiO 2 was then patterned using ICP etching, then the 4H-SiC was etched to a depth of 1.4 μm. Using an ICP power of 1000 W, the etch rate for 4H-SiC was around 700 nm/min, and the NiV layer provided a selectivity factor of around 20. After the etch, the remaining NiV and TEOS SiO 2 was removed in Aqua Regia and HF solution respectively. The active areas of the fabricated PiN diodes ranged from to cm 2.

3 FISHER et al.: IMPROVED PERFORMANCE OF 4H-SiC PiN DIODES 445 Fig. 1. Cross-sectional schematic of fabricated 4H-SiC PiN diodes. Fig. 2. Photograph of DCB-mounted 4H-SiC PiN diode die. Once the mesas were defined, a 1.5 μm thick layer of TEOS SiO 2 was deposited onto the dies. Using photolithography, windows for the anode ohmic contacts were defined, and the TEOS SiO 2 was etched to a depth of 1.2 μm using reactive ion etching (RIE), then the TEOS SiO 2 was etched down to the 4H-SiC surface using 10:1 buffered oxide etch (BOE) solution. For the anode ohmic contacts, a titanium (Ti)/aluminum (Al) (30/100 nm) metal scheme was evaporated onto the dies [15]. The unwanted metal was then removed using an acetone lift-off process. Prior to the backside (cathode) metallization, an SiO 2 ICP etch was performed to remove any residual SiO 2. A metal scheme consisting of Ti/Ni (30/80 nm) was then evaporated onto the backside of the dies. The dies were then annealed in a rapid thermal anneal (RTA) furnace at 1000 C for 2 minutes. After the contact anneal, a 1 μm thick layer of Al and a 500 nm thick layer of silver (Ag) were evaporated onto the front and backside of the dies, respectively. The frontside Al was patterned using photoresist and the unwanted Al removed in Al etch solution. A cross-sectional schematic of the fabricated PiN diodes is shown in Fig. 1. B. Device Packaging After completion of device fabrication and on-die probe testing, each die has been soldered onto a direct copper bond (DCB) substrate using an Ag solder. Connection tabs to each device anode have also been soldered onto the DCB. Wire bonding from the Al anode contact pads to the connection tabs has been performed using an ultrasonic wire bonder with 25 μm Al wire. In order to minimize the effects of wire bond resistance and inductance, up to 10 bonds were wired in parallel for each diode, depending on the device active area. A photograph of a DCB-mounted PiN diode die is shown in Fig. 2. Each die contains four PiN diodes of varying active areas, in addition to conventional transfer length method (TLM) and circular TLM structures for extracting the p-type anode ohmic contact resistance [16]. C. Test Setup 1) Forward I-V Characterisation: For on-die testing of forward current-voltage (I-V) characteristics of the fabricated Chopper cell circuit used for PiN diode reverse recovery characteri- Fig. 3. zation. PiN diodes, a Keithley 4200-SCS semiconductor parameter analyser system has been used in conjunction with a heated chuck and probe station. The use of a heated chuck has enabled device characteristics at temperatures ranging from 25 Cto 300 C to be obtained. Packaged devices have been tested using a Tektronix 371B high power curve tracer. In order to minimize device self-heating effects during testing, pulsed measurement mode has been used in both measurement setups. 2) Reverse I-V Characterisation: On-die reverse leakage current measurements (up to 100 V reverse bias) of the fabricated PiN diodes have been obtained under low-noise, dark conditions using an Agilent B1500A semiconductor parameter analyser in conjunction with a probe station. Reverse breakdown measurements were performed on DCB-mounted devices using a Tektronix 371B high power curve tracer. 3) Reverse Recovery Characterisation: In order to characterize the reverse recovery performance of the fabricated PiN diodes, a custom-built clamped inductive switching test rig has been employed. Characteristics at temperatures up to 125 C have been obtained by heating an inert fluid in which the devices under test are submerged. The test rig is based on a chopper cell circuit, shown schematically in Fig. 3 and pictorially in Fig. 4. This circuit is operated in double-pulse mode which operates as follows: the gate of the IGBT is first

4 446 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 27, NO. 3, AUGUST 2014 Fig. 5. Typical forward J-V characteristics for control sample (bottom) and thermally oxidised/annealed sample (top) PiN diodes. Fig. 4. Photograph of clamped inductive switching test rig used for PiN diode reverse recovery characterization. pulsed on for a duration T, allowing the inductor current to build up to the desired level. Once this current level is reached, the IGBT is turned off, forcing the inductor current to flow through the diode, turning it on, and allowing the IGBT to support a voltage across the collector-emitter junction (V CE ). After a short duration t off, the gate of the IGBT is pulsed on for a second time; due to the removal of stored charge in the PiN diode a reverse recovery current flows through the diode until it can support the reverse voltage. In this test setup, the DC bus voltage V DC has been supplied by a 12 kv/125 ma capacitor charger power supply, which charges a bank of capacitors totalling 94 μf. This capacitor bank then supplies the circuit current whilst providing a constant DC voltage source. The diode voltage V AK, V CE, and the IGBT gate-emitter voltage V GE have all been instrumented using a Tektronix TDS5054B digital oscilloscope. The diode current I A has been measured using a current monitor which was also instrumented using the digital oscilloscope. Finally, a HCPL-3020 optocoupler has been used to drive the gate of the IGBT, itself driven by a Tektronix AFG3022C function generator. III. RESULTS AND DISCUSSION A. Forward I-V Characteristics The typical forward I(J)-V characteristics of fabricated PiN diodes measured across the temperature range 25 C and 300 C are shown in Fig. 5. It is evident that the devices exhibit a negative temperature coefficient and thus have a lower forward voltage drop with increasing temperature, which is beneficial for high temperature operation. This improvement in the forward characteristics is expected, as the dopant activation in the p-type anode is improved, the carrier lifetime in the drift region is increased, and the resistance of the ohmic contacts is reduced. These three effects combine Fig. 6. Forward logj-v characteristics for control sample and thermally oxidised/annealed sample PiN diodes at 25 C. The inset graph shows the point of turn-on. to overcome the reduced carrier mobility at higher temperatures. It can also be seen from Fig. 5 that the forward characteristics of the samples having undergone the thermal oxidation/annealing process are superior to the characteristics of the control samples; a reduction in the forward voltage drop of the diodes of around 15% was measured at 100 A/cm 2 and at 25 C. The logj-v forward characteristics of the fabricated PiN diodes are shown in Fig. 6. Also shown inset is the point of turn-on, which is around 2.6 V and corresponds to the intrinsic carrier concentration in the semiconductor [17]. In the low-level injection regime a value η = 2 has been extracted, indicating current transport is dominated by recombinationgeneration. Beyond the point of turn-on, the ideality factor decreases to a value η = 1.5; this is slightly higher than the theoretically ideal value of η = 1. As proposed by Evstrapov et al.[18], this is indicative of the presence of defect levels within the semiconductor, in which the ideality factor is related to the number of deep defect levels, d, and the number of shallow defect levels, s, where η = 2d + s (1) d + s

5 FISHER et al.: IMPROVED PERFORMANCE OF 4H-SiC PiN DIODES 447 Fig. 7. Differential on-resistance as a function of current density for control sample (bottom) and thermally oxidised/annealed sample (top) PiN diodes. The extracted value of η = 1.5 is close to the model proposed in [18] if it is assumed that one dominant deep level and one dominant shallow level exist in the semiconductor energy band gap. At higher values of forward current density the ideality factor quickly increases, as the J-V characteristics become dominated by the series resistance of the diode. A comparison of the typical R on,diff as a function of forward current density of the fabricated PiN diodes is shown in Fig. 7, calculated from R on,diff = dv (2) dj F It is evident from these results that in both device characteristics the R on,diff is initially high and rapidly decreases with increasing forward bias, illustrating the effectiveness of conductivity modulation in reducing the on-state losses of the PiN diodes. Though at high current densities R on,diff is lower at elevated temperatures, it is found that at low current density the decreased mobility at higher temperatures results in a higher initial R on,diff. It can also be seen in both device characteristics that at 25 C, R on,diff continues to decrease with increasing current density, suggesting that the carrier lifetime could be further improved to fully modulate the drift region at lower current density [19]. As with the forward voltage drop of the thermally oxidised/annealed PiN diodes, the R on,diff is significantly lower than for the control sample PiN diodes, dropping from around 11.0 m -cm 2 to 6.2 m -cm 2 at 100 A/cm 2 and 25 C, a reduction of over 40%. Finally, Fig. 8 shows histograms for the R on,diff data for both the control sample and thermally oxidised/annealed sample (top) PiN diodes. It is evident from this statistical data that the batch of PiN diodes that underwent the oxidation/annealing process (eight devices total) have better overall forward characteristics than the batch of control sample PiN diodes (also eight devices total), with minimum and maximum R on,diff values of 3.0 m -cm 2 and 7.1 m -cm 2 (at 100 A/cm 2 and 25 C) respectively, for the oxidised/annealed PiN diodes, and minimum and maximum R on,diff values of 5.3 m -cm 2 and 13.9 m -cm 2 respectively, for the control sample PiN diodes. This data further highlights the significant on-state performance benefits gained from Fig. 8. Histogram showing the differential on-resistance data for control sample (bottom) and thermally oxidised/annealed sample (top) PiN diodes. the thermal oxidation/annealing process. It is also noted, for completeness, that the anode ohmic contact resistance was measured (via TLM structures) to be around cm 2, which is a fraction of the overall on-resistance of the PiN diodes. B. Reverse I-V Characteristics In a PiN diode, the total leakage current under reverse bias (prior to avalanche) is dominated by the generation current in the depletion region, which is described by [12] J G = qn iw d 2τ g (3) where q is electronic charge, n i is the intrinsic carrier concentration, W d is the depletion layer width and τ g is the generation lifetime. It is clearly evident from this equation that the leakage current of the device is inversely proportional to the generation lifetime. Assuming an intrinsic carrier concentration of cm 3 [1], an arbitrary generation lifetime of 1 μs and calculating the depletion layer width from ( ) 2εSiC V 0.5 d W d = (4) qn D where ε SiC is the dielectric constant of 4H-SiC, V d is the voltage across the depletion layer (which can be assumed to be equal to the reverse voltage applied across the diode) and N D is the doping concentration in the n-type drift region of the PiN diode, a generation current value of A/cm 2 has been

6 448 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 27, NO. 3, AUGUST 2014 Fig. 9. Reverse leakage currents of thermally oxidised/annealed and control sample PiN diodes. Both small- and large-area device characteristics are shown. calculated, based on an applied reverse voltage of 100 V. When comparing this to reverse leakage current values obtained experimentally, shown in Fig. 9, it is evident that this theoretical value is many orders of magnitude lower. Although the test setup used for reverse leakage current measurements is unable to measure down to this theoretical leakage current value, it is expected that surface generation forms a significant part of the total leakage current in the PiN diode. This can be represented by adding a surface generation term to the generation lifetime, described by J G = qn iw d 2 [ 1 τ d + s P A where τ d is the generation lifetime in the depletion region, s is the surface generation velocity, P is the perimeter of the depletion width edge on the surface of the device and A is the area of the depleted surface. On inspection of Fig. 9, it can be seen that the small-area devices (with an active area of cm 2 ) have higher leakage currents than the large-area devices (active area of cm 2 ), though for both device sizes the difference in reverse leakage currents between the thermally oxidised/annealed and the control sample PiN diodes is negligible in comparison. It has long been reported that the surface generation component has a significant effect on the reverse leakage characteristics of 4H-SiC PiN diodes [20], which highlights the need for an effective surface passivation solution. It should be noted that breakdown voltage tests have not been properly performed on the fabricated PiN diodes, but preliminary measurements showed that the devices blocked a reverse voltage well in excess of 1 kv. C. Reverse Recovery Characteristics Fig. 10 shows the typical reverse recovery characteristics of the control sample and the thermally oxidised/annealed sample PiN diodes (both with active areas of cm 2 ) between 25 C and 125 C. Because the devices were fabricated with no edge termination, a DC bus voltage of 100 V has been used. Although this DC bus voltage is relatively low when compared to the theoretical blocking voltage of the fabricated PiN diodes, it still allows a quantitative comparison of the switching characteristics of the two types of device. The diode ] (5) Fig. 10. Reverse recovery characteristics for control sample (bottom) and thermally oxidised/annealed sample (top) PiN diodes at 25 C, 75 C and 125 C. forward current density (J F )wassetat60a/cm 2, sufficient to ensure the devices under test were being operated under highlevel injection conditions, and the di/dt was fixed at 40 A/μs. It can be seen that both the peak reverse current density (J RP ) and the reverse recovery time (t rr ) are greater for the thermally oxidised/annealed sample PiN diode than the control sample device. As outlined in [12], the carrier lifetime of the PiN diode under high-level injection conditions (τ HL ) can be calculated from the reverse recovery characteristics from τ HL = 2 IRP t rr (6) I F Although this is a relatively simple approach for carrier lifetime extraction for reverse recovery characteristics, this technique has been recently used elsewhere for the analysis of carrier lifetime in 4H-SiC PiN diodes [8], and also does not suffer from the limitation whereby the ramp time between J = J F and J = J RP needs to be greater than the lifetime τ, as in the methods presented by Tien and Hu [21] and, more recently, Dhariwal and Sharma [22]. Using Eq. 6, the highlevel lifetime for the thermally oxidised/annealed PiN diode showninfig.10 was calculated to be 1.23 μs whilst a value of 756 ns was calculated for the control sample PiN diode, equating to an increase of around 40%. On observation, it can be seen that this improvement in carrier lifetime is approximately the same as the improvement in R on,diff. If the first order approximation relating the forward current density to the carrier lifetime in the drift region is rearranged for the (assumed to be uniform) carrier distribution p in the drift region [12] p = J Fτ HL (7) 2qd and the calculated value of p is fed into the equation for drift region resistivity, given by ρ D = W D (8) qμ n p where W D is the drift region width and μ n is the carrier mobility in the drift region, it can be seen that there is a linear proportional relationship between τ HL and ρ D. Although this is a simplification of a complex conduction mechanism

7 FISHER et al.: IMPROVED PERFORMANCE OF 4H-SiC PiN DIODES 449 Fig. 11. Power and energy dissipation over turn-on and turn-off switching transitions of thermally oxidised/annealed sample PiN diode at 25 C. described in [12], it can be used to qualitatively assess the performance of the PiN diodes and thus explain the similarity in improvement of τ HL and R on,diff. The magnitude of improvement in the carrier lifetime was found to be representative of the fabricated PiN diodes across the range of device active areas, though it was observed that the smaller area devices with a larger perimeter to area (P/A) ratio had correspondingly lower carrier lifetimes. It can be inferred from this that recombination at the mesa sidewall has a large effect on the overall carrier lifetime of the 4H-SiC PiN diodes; this is one fabrication issue that would benefit from further investigation. It is also noted that although a significant improvement in carrier lifetime has been achieved by the relatively short thermal oxidation/annealing process (15 minutes thermal oxidation and 30 minutes annealing time), it is likely that there is scope for further increasing of the carrier lifetime by extending the thermal oxidation time. Fig. 11 shows the typical power and energy dissipation of the thermally oxidised/annealed sample PiN diode. As expected, the instantaneous turn-on power dissipation of the diode is insignificant compared to that for the turn-off switching event, with the instantaneous power dissipation reaching nearly 85 W. This is in comparison to that for the control sample PiN diode (not shown), which reached the lower value of 70 W. In terms of energy dissipated, this corresponds to a turn-off energy of 4.5 μj for the thermally oxidised/annealed sample PiN diode and 3 μj for the control sample PiN diode. It is evident from Fig. 11 that the total energy dissipated over the duration of the switching events is dominated by the conduction losses of the PiN diodes and the associated wiring, illustrating the insignificance in the slightly worse transient characteristics of the thermally oxidised/annealed devices. Moreover, the high voltage power electronics applications in which the PiN diodes fabricated in this paper are intended for typically switch at several hundred Hz, meaning that conduction losses will dominate the overall power losses of the circuit. IV. CONCLUSION In this paper, a novel combined thermal oxidation/annealing process performed at 1550 C for enhancing the carrier lifetime of 4H-SiC has been applied to PiN diodes with n-type epitaxial drift regions of 110 μm thickness, and the forward and reverse recovery characteristics of these devices have been investigated. The PiN diodes fabricated with the thermal oxidation/annealing process showed a forward voltage drop of around 3.8 V, which was considerably lower than the control sample PiN diodes. The differential on-resistance of the fabricated devices showed a similar trend in performance, with the thermally oxidised/annealed PiN diodes exhibiting a R on,diff of around 4.5 m -cm 2 ; this compared to around 9.2 m -cm 2 for the control sample devices. Though the drift region is slightly thinner in this work, the results presented here compare favourably to those published elsewhere [8]. From analysis of the reverse recovery characteristics, it was found that the PiN diodes having undergone the thermal oxidation/annealing process have a slightly larger I RP and t rr than the control sample PiN diodes. This equated to a turn-off energy loss around 50% higher for the thermally oxidised/annealed sample PiN diodes. The carrier lifetime of the thermally oxidised/annealed PiN diodes was calculated to be around 1.2 μs, which was a significant increase on the value calculated for the control sample PiN diodes. It was found that the carrier lifetime was shorter for devices with a larger P/A ratio, suggesting that recombination at the mesa sidewall dominates the carrier lifetime value. The reverse leakage current of the fabricated PiN diodes was also found to be strongly dependent on the active area, with the devices with a larger P/A ratio exhibiting higher leakage currents as a result of enhanced surface generation. Further work to investigate increasing the thermal oxidation duration at high temperatures is proposed to further enhance the carrier lifetime and improve the onstate characteristics of 4H-SiC PiN diodes; this is currently underway. ACKNOWLEDGMENT The authors would like to thank Power Electronics Centre and High Voltage Microelectronics and Sensors group at the University of Cambridge, for use of their electrical characterization facilities. They would also like to thank Dr. M. Crouch and the cleanroom staff for support during device fabrication, and G. Canham for photography. REFERENCES [1] T. P. Chow, Progress in high voltage SiC and GaN power switching devices, Mater. Sci. Forum, vol , pp , Feb [2] T. Kimoto, K. Danno, and J. Suda, Lifetime-killing defects in 4H-SiC epilayers and lifetime control by low-energy electron irradiation, Phys. Status Solidi B, vol. 245, no. 7, pp , [3] T. Hiyoshi and T. Kimoto, Reduction of deep levels and improvement of carrier lifetime in n-type 4H-SiC by thermal oxidation, Appl. Phys. Exp., vol. 2, no. 4, p , [4] P. B. Klein, Long carrier lifetimes in n-type 4H-SiC epilayers, Mater. Sci. Forum, vol , pp , Feb [5] K. Kawahara, J. Suda, and T. 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8 450 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 27, NO. 3, AUGUST 2014 [8] K. Nakayama et al., Characteristics of a 4H-SiC PiN diode with carbon implantation/thermal oxidation, IEEE Trans. Electron Devices, vol. 59, no. 4, pp , Apr [9] L. Storasta and H. Tsuchida, Reduction of traps and improvement of carrier lifetime in 4H-SiC epilayers by ion implantation, Appl. Phys. Lett., vol. 90, no. 6, p , [10] S. M. Thomas, M. R. Jennings, Y. K. Sharma, C. A. Fisher, and P. A. Mawby, Impact of oxidation temperature on the interface trap density in 4H-SiC MOS capacitors, Mater. Sci. Forum, vol , pp , Feb [11] C. A. Fisher et al., Enhanced forward bias operation of 4H-SiC PiN diodes using high temperature oxidation, in Proc. Mater. Res. Soc. (MRS) Spring Meeting, vol San Francisco, CA, USA, Apr [12] B. J. Baliga, Fundamentals of Power Semiconductor Devices. NewYork, NY, USA: Springer, [13] L. Jiang, R. Cheung, R. Brown, and A. Mount, Inductively coupled plasma etching of SiC in SF 6 /O 2 and etch-induced surface chemical bonding modifications, J. Appl. Phys., vol. 93, no. 3, pp , [14] P. Losee, Design, fabrication and characterization of high voltage 4H-SiC junction rectifiers for power switching applications, Ph.D. dissertation, Electr., Comput., Syst. Eng. Dept. Rensselaer Polytechnic Institute, Troy, NY, USA, Feb [15] M. R. Jennings et al., On the Ti 3 SiC 2 metallic phase formation for p-type 4H-SiC ohmic contacts, Mater. Sci. Forum, vol , pp , Feb [16] D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. Hoboken, NJ, USA: Wiley, [17] S. M. Sze, Physics of Semiconductor Devices. Hoboken, NJ, USA: Wiley, [18] V. V. Evstrapov, K. V. Kiselev, I. L. Petrovich, and B. V. Tsarenkov, Current due to recombination via multilevel centers in space charge layer of p-n structure, Soviet Phys. Semicond., vol. 18, no. 10, pp , [19] L. Cheng et al., 16 kv, 1 cm 2 4H-SiC PiN diodes for advanced high-power and high-temperature applications, Mater. Sci. Forum, vol , pp , Feb [20] T. Kimoto, N. Miyamoto, and H. Matsunami, Performance limiting surface defects in SiC epitaxial p-n junction diodes, IEEE Trans. Electron Devices, vol. 46, no. 3, pp , Mar [21] B. Tien and C. Hu, Determination of carrier lifetime from rectifier ramp recovery waveform, IEEE Electron Device Lett., vol. 9, no. 10, pp , Oct [22] S. R. Dhariwal and R. C. Sharma, Determination of carrier lifetime in p-i-n diodes by ramp recovery, IEEE Electron Device Lett., vol. 13, no. 2, pp , Feb Craig A. Fisher was born in Warwickshire, U.K., in He received the M.Sc. degree in advanced electronics engineering, and the Ph.D degree in the field of silicon carbide power electronics from the University of Warwick, Coventry, U.K., in 2010 and 2014, respectively. The Ph.D degree was funded by the EPSRC HubNet project (grant number EP/I013636/1), and was focused on three principle areas: novel edge termination solutions for high voltage power devices, carrier lifetime enhancement using high temperature processes, and the formation of robust ohmic contacts to p-type 4H-SiC. He is currently a Research Fellow with the School of Engineering, University of Warwick, on the EPSRC Underpinning Power Electronics project (grant number EP/K035304/1). His research interests include modeling of 4H-SiC power devices, and the fabrication and characterization of 4H-SiC devices for high voltage (>10 kv) and high temperature (>300 C) applications. Michael R. Jennings was born in Neath, Wales, in He received the B.Eng. degree in Electronics with Communications from the University of Wales, Swansea, U.K., in The B.Eng. degree incorporated a second year (exchange program) of study in the USA, where he studied at Union College, Schenectady, NY, USA. He then undertook the Ph.D. degree in power semiconductors from the University of Warwick, Coventry, U.K. During the Ph.D. degree, he has won travel scholarships from the IEE (Hudswell Bequest Fellowship) and Welsh Livery Guild for electrical engineering research purposes. The scholarships obtained allowed him to visit Rensselaer Polytechnic Institute, Troy, NY, USA, in In 2009, he was awarded a Science City Research Alliance Fellowship, sponsored by the European Regional Development Fund and Advantage West Midlands. The focus of his research within this remit was the development of Silicon carbide devices. His current research topics include high voltage bipolar devices (PiN diodes and Thyristors) in SiC, novel gate oxidation processes for FETs and 3C-SiC (cubic) growth above direct wafer bonded Si/SiC structures. He is also a Lecturer on the first year general engineering electronics course. Yogesh K. Sharma received the B.Sc. degree from India and his M.Sc (2010) and Ph.D. (2013) degrees from Auburn University, Auburn, AL, USA. He has been working on SiC and GaN WBG semiconductors for past six years. During the M.Sc degree, he worked on GaN Schottky diodes and AlGaN/GaN HEMTs for bio sensing applications but later on he focused on SiC devices. His Ph.D work was to improve the SiO 2 /4H-SiC interface, which is crucial for SiC MOS technology. He worked on two projects thin PSG and nitrogen plasma to improve the interface, and successful execution of these projects resulted in peer-reviewed journal papers and presentations at various international conferences. He is currently working as a Research Associate from the School of Engineering, University of Warwick, Coventry, U.K. His current projects involve the development of 600 V 1200 V power devices on 3C-SiC, and 10 kv MOSFETs on 4H-SiC. He has authored/co-authored over 20 technical/conference papers. He is the holder of one patent and acted as a reviewer for IEEE TRANSACTIONS ON POWER ELECTRONICS and the Materials Research Society. Dean P. Hamilton undertook the first degree and master s degree in systems engineering from the University of York, York, U.K. Following this he joined the Systems Design team at Marconi Communications, working on advanced high speed data switching systems. This included leading the development of an ADSL system and being a member of their next-generation developments team. He later received the Ph.D degree from the University of Warwick, Coventry, U.K., and has since worked as a Research Fellow with Power Electronics Research Group at the School of Engineering. He has previously worked as part of a team to develop a fast inverter simulator for Toyota, Japan, to model thermal cycling of IGBTs in their Prius converter, and then on a low carbon vehicle project to evaluate SiC MOSFETs and packaging. His current project and research interests are SiC inverters, device reliability, and high temperature power module packaging for electric vehicle powertrains. Peter M. Gammon received the M.Eng. degree in electronic engineering from the University of Warwick, Coventry, U.K., in 2006, where he received the Ph.D. degree, in The Ph.D. degree was on the topic of SiC-based heterojunction characterization. He is currently a Royal Academy of Engineering Senior Research Fellow with the University of Warwick, where he leads the NICHE project, in which a Si/SiC platform is being developed to compete with high temperature, harsh environment, and SOI technology.

9 FISHER et al.: IMPROVED PERFORMANCE OF 4H-SiC PiN DIODES 451 Amador Pérez-Tomás received the B.Sc. degree from the University of Barcelona, Barcelona, Spain, and the Ph.D. (Hons.) degree in physics from the Autonomous University of Barcelona, Barcelona, in From 1999 to 2001, he worked as Consultant with Financial Sector for EDS (now Hewlett Packard). He was a Research Fellow with the University of Warwick, Coventry, U.K., from 2006 to During this tenure he gained a prestigious RyC grant to develop his work at CNM, Barcelona, from 2008 to 2014 with an outstanding final review. In 2014, he joined the Severo Ochoa Excellence Centre Institut Catal de Nanocincia i Nanotecnologia. His current research activities are related to SiC and GaN devices, MOS interfaces, HEMT and solar cells fabrication, characterization, and modeling. He has authored (or co-authored) over 150 papers including journal and international conference papers. He has lead or participated in several European projects and industrial contracts, directed Ph.D. degree students and holds several patents. He is also an Associate of several spin-off initiatives based on the aforementioned patents. Stephen M. Thomas received the B.Eng. (Hons.) degree in electronic engineering from the University of Southampton, Southampton, U.K., and the M.Sc. and Ph.D. degrees in physics from the University of Warwick, Coventry, U.K. The Ph.D degree was on the electrical characterization of strained silicon finfets and novel Si MOSFETs. He is currently a Research Fellow with the School of Engineering at Warwick, his primary research area is silicon carbide device fabrication for high voltage applications. His focus is on the interface quality of oxide-based devices. Susan E. Burrows received the B.Sc. degree in textile chemistry from the University of Leeds, Leeds, U.K., in 1988, and the Ph.D. degree in materials physics from the University of Warwick, Coventry, U.K., in She is currently a Senior Research Fellow with the Condensed Matter Physics Group, University of Warwick, and has research interests in glass corrosion, ceramics, piezoelectrics, and ultrasound. Philip A. Mawby (S 85 M 86 SM 01) received the B.Sc. degree and then the Ph.D. degree in 1986 from the University of Leeds, U.K. His Ph.D. degree focussed on the development of GaAs/AlGaAs heterojunction bipolar transistors for high power radio frequency applications, in conjunction with co-workers at the GEC Hirst Research Centre, Wembley, U.K. Following this, he joined the University of Wales, Swansea, U.K., where he established the Power Electronics Design Centre, which carried work out in a whole range of areas relating to power electronics. The center focussed on interaction with SMEs in Wales as well as larger international companies. While he was in Swansea he also held the Royal Academy of Engineering Chair for Power Electronics. After 19 years at the University of Wales, he joined the University of Warwick, Coventry, U.K., where he founded the Power Electronics, Applications and Technology in Energy Research group. His main research interests are materials for new power devices, modeling of power devices and circuits, and power integrated circuits. He has also worked extensively on development of device simulation algorithms, as well as optoelectronic and quantum based device structures. He is on many international conference committees including ISPSD, EPE, BCTM, and ESSDERC. He is a Chartered Engineer, a fellow of the IET, and a fellow of the Institute Physics. He has published over 70 Journal papers and 100 conference papers, and is a Distinguished Lecturer for the IEEE Electron Devices Society.