IGBT Module Chip Improvements for Industrial Motor Drives

Transcription

1 IGBT Module Chip Improvements for Industrial Motor Drives John F. Donlon Powerex, Inc. 173 Pavilion Lane Youngwood, PA USA Katsumi Satoh Mitsubishi Electric Corporation Power Semiconductor Device Works Fukuoka JAPAN Abstract Since the introduction of the IGBT module, improvements in power loss have been achieved by applying new technologies. With the process improvements of the past few years in trench gate technology and light-punch-through vertical structures, it had been thought that the performance of the latest IGBT and pin diode silicon power devices had been brought as close to their theoretical limit as possible. In this paper, fine pattern processing technology is applied along with optimization of the low impurity profile of the buffer layer using thin wafer technology to further reduce the power loss. I. INTRODUCTION Planar insulated gate bipolar transistor (IGBT) modules were introduced to the industry application market in the latter half of 1980s, and in combination with free-wheel diode (FWD), have been one of the main power module products. The performance of IGBTs had been drastically improved during the following decade with the development of fine patterning process technology. In 1999, trench gate IGBT modules were launched in mass production, and currently are widely used in industrial applications. The trench gate IGBT exhibits superior electrical characteristics because of lower onresistance by avoiding the JFET resistance at the surface MOSFET portion. In order to further reduce the energy loss of IGBT modules, the optimization of the carrier distribution in the n- layer of injection enhanced gate bipolar transistor (IEGT) or carrier stored trench gate bipolar transistor (CSTBT TM ) technology was demonstrated. [1-3] Furthermore, thin wafer process technology has been developed to utilize FZ (float zone) wafers to control cost. A Figure of Merit (FOM) is commonly used as a performance index to assess the efficacy of the transition of new technologies in comparison to prior state-of-the-art. Here, the FOM is defined as the chip current density (J C ), divided by the product of the saturation voltage (V CE(sat), V) and the turnoff energy loss per pulse per unit current (Eoff, mj/pulse/a) in inductive switching, which are both obtained at 125 C operating junction temperature. As shown in Fig. 1, the FOM of the latest IGBT technology (i.e., the 5 th gen. CSTBT TM ) is one order of magnitude larger than that of the 1 st gen. Similarly, the energy losses of FWDs have been significantly reduced with the optimization of the impurity profile through the application of lifetime control techniques and thin wafer process technology. [5-7] Moreover, a considerable amount of attention has recently been applied to reduce module noise in response to various EMI/EMC regulations that have been instituted around the world. Consequently, accompanying the development of the new IGBT technologies, the performance was thought to be approaching the theoretical limit of silicon power devices. However, the present paper demonstrates the feasibility of improving the performance of IGBT modules even further by developing new fine pattern technology. By optimizing the design of the device structure, further reduction of the power loss of these devices is achieved without sacrificing safe operating area (SOA) or noise. Figure 1. Figure of Merit history for 1200V IGBT 1

2 II. PRESENT SITUATION A. IGBT Generally, there are two controlling trade-off relationships between the characteristics of IGBTs. One is related to the saturation voltage (V CE(sat) ) and turn-off energy loss (Eoff), and the other is between V CE(sat) and short-circuit safe operating area (SCSOA). In order to improve the first trade-off relationship, structure optimization involving the modulation of carrier distribution in the n- layer of CSTBT TM or IEGT has been proposed. The modification of the device structure not only induces the decrease of V CE(sat), but also increases turn-off dv/dt, which is one of the sources of module noise. Therefore, it is important to control the turn-off dv/dt with the gate resistance. In contrast, a great improvement of the second trade-off relationship has been achieved by the combination of thin wafer process technology, which handles IGBT wafers with a thickness less than 100 µm, and the concept of lightly doped n- buffer structure, which refers to the Light-Punch-Through (LPT), Field-Stop (FS), or Soft-Punch-Through (SPT) vertical structures. As the main current flows from the collector side at the back surface to the emitter side at the front surface patterned with the MOS structure, the on-resistance of an IGBT is almost fixed by the wafer thickness. Thin wafer process technology offers a good solution to enhance the device performance. In thin wafer process, the IGBT wafer is lapped or ground at the back surface to decrease the wafer thickness without sacrificing either voltage blocking capability or SCSOA. However, the grinding process can induce crystal damage, which results in a short carrier lifetime. It is thus necessary to accurately control the relevant process conditions. Key characteristics of the 1200V 5 th generation CSTBT TM IGBT chip are listed in Table 1. B. Diode The performance of a FWD should be improved in terms of V F -Erec trade-off and the mitigation of oscillation at reverse recovery operation. For FWD, the combination of the pin structure and lifetime control techniques, i.e., Pt diffusion and electron beam irradiation, has been adopted and provides significantly improved performance. On the one hand, local lifetime control techniques such as proton irradiation and He irradiation have recently been developed and demonstrate a better V F -Erec trade-off. On the other hand, the pin structured epi-diode has been proposed in which a n- layer as an intrinsic layer and a n+ buffer layer with heavy doping profile are grown on n++ Si substrate by epitaxial crystal growth. Heavy doping profile results in a small forward voltage drop (V F ), but often causes voltage oscillation at reverse recovery operation. This oscillation is another source of module noise. In high-voltage diodes with blocking voltage of more than 3.3kV, a diode having the oscillation free function to mitigate the noise has been realized. However, the diode structure with an oscillation free function is rather sensitive to controlling the parasitic transistor, and the corresponding manufacture cost is high. Consequently, current diode technology ranges from pn diode to epi diode with some sacrificing of the V F characteristic. Now the thin wafer process has been utilized to reduce V F as low as possible. Characteristics of 1200V diode chip utilizing thin wafer process is shown in Table 2. III. TECHNOLOGY FOR NEXT GENERATION MODULES Realizing a better trade-off relationship is one of the most important goals in the development of power devices. In this paper, fine pattern technology and a further optimized impurity profile design are proposed to overcome the dilemma that is currently present in power devices. A. Fine Pattern IGBT performance is dependent on fine pattern processing technology. Making full use of fine pattern processing leads to an increase in trench density. The trench gate functions as a MOS channel, and the capability of current conduction is thereby dramatically enhanced with respect to the high-density MOS channels. Fig. 2 depicts a cross-sectional view of a trench gate IGBT, where the cell pitch is defined as the distance between the centers of adjacent trenches. Fig. 3 displays the dependence of performance parameters of a 1200V IGBT on cell pitch. Figure. 3(a) shows the relation of saturation voltage, V CE(sat), at a current density of 150A/cm 2 at 125 C to cell pitch for the 4th generation trench gate IGBT and the 5 th generation CSTBT TM IGBT, respectively. As can be seen, the V CE(sat) of a CSTBT TM 2

3 decreases by 0.6 V for a 4.0 m-wide cell pitch. When the cell pitch decreases to 2.2 m, the improvement in V CE(sat) between the trench IGBT and CSTBT TM remains as large as 0.3 V. room for optimizing the device exists on a basis of LSI technology. Pursuit of fine patterning and uniformity of device performance are one of the effective methods for the future development of CSTBT TM. Figure 2. Cross-sectional view of IGBT at the emitter side Figure 3(b). Cell pitch dependence of J C(sat) Figure 3(a). Cell pitch dependence of V CE (sat) Fig. 3(b) shows the variation of saturation current density (J CE(sat) ) at 125 C with cell pitch for these same two IGBT chip technologies in Fig. 3(a). As shown in Fig. 3(b), the J CE(sat) of a CSTBT TM chip is increased by ~ 40 A/cm 2 compared to that of the standard trench IGBT technology. Therefore, the narrower the cell pitch, the lower the V CE(sat) and the larger the J CE(sat) that can be successfully obtained by adopting the CSTBT TM technology. Fig. 4 shows the schematic description of the relationship between V GE(th) to I C(sat) and short-circuit capability. It indicates that suppressing the distribution of V GE(th) leads to the improvement of SCSOA characteristics with respect to the satisfaction of the minimum collector current. [4] Therefore, in the case of bipolar devices such as IGBT and CSTBT TM, Figure 4. Relationship of V GE (th) to I C(sat) and SCSOA B. IGBT cell impurity profile CSTBT TM, which is developed here, is composed of a triple layered structure in the region of the trench gate, that is, N- Emitter/ P-Base/ CS layer. The final doping profile of the sandwiched P-base, which represents a channel doping profile of the vertical MOSFET portion of CSTBT TM, was formed as a result of the compensation between the doping processes of n-type CS layer and the P-base (as shown in Fig. 5(a)). The distribution of doping concentration in the channel of CSTBT TM is, therefore, relatively larger than that in a standard double layered Trench IGBT structure because of this extra compensation. Taking into account the effect of extra 3

4 compensation between P-base and CS layer, we modulate the doping profile of the CS layer into a retrograde profile, which prevents the influence of impurities from the CS layer due to the reduction of n-type impurities in the MOS channel region (Fig. 5(b)). As a result, the range of the distribution of the V GE(th) decreases, and thereby the SCSOA performance increases. Figure 6. Transconductance characteristics of new and conventional doping profiles Figure 5(a). Conventional doping profile of the vertical MOSFET portion C. Diode design Fig. 7 shows the doping profile as well as the carrier distribution in a FWD during forward conduction. It has been demonstrated that higher impurity concentration in the buffer layer generally causes larger concentration gradient in the region of the buffer layer near the intrinsic layer. This is one of the main causes of oscillation at reverse recovery operation. The use of the buffer layer with a higher doping carrier and the intrinsic layer with thinner thickness can decrease the V F, whereas the corresponding reverse recovery charge (Qrr) is also increased. Figure 5(b). New doping profile of the vertical MOSFET portion The behavior of the transconductance characteristics of the new doping profile of CSTBT TM is compared with that of a conventional device, as shown in Fig. 6. The threshold voltage of a CSTBT TM chip with the conventional doping profile varies about 0.85 V corresponding to the change of CS-layer dosage from 50% (half) to 100% (standard). On the other hand, the change of the threshold voltage of the CSTBT TM with a retrograde profile is limited to only 0.2V, even when the variation of CS-layer doping ranges from 50% to 200%(double). Consequently, the impact of MOS channel on V GE(th) becomes negligible, and the uniformity of the device performance is enhanced. Figure 7. Doping profile and carrier distribution during forward conduction A new 1200V FWD chip has been developed that optimizes the impurity profile of the buffer layer and the thicknesses of the intrinsic layer and buffer layer using thin wafer technology 4

5 and diffusion techniques. Through buffer structure optimization, the tail current at reverse recovery operation is reduced, and a better trade-off relationship between V F and Q rr is obtained. Fig. 8 shows the trade-off curves between V F (under the conditions of J F =250A/cm 2 and Tj=125 C) and Erec (under the conditions of Vcc=600V, J F =250A/cm 2, di/dt=2450a/cm 2 /µs, Tj=125 C) for various diodes with different wafer processes. The modulation of V F was controlled by the electron beam irradiation dose as a lifetime control technique. It is clearly evident that the diode proposed in this work exhibits lower reverse recovery energy loss in comparison to those fabricated in conventional process technologies, and therefore the trade-off relationship is dramatically improved by optimizing the impurity profile and buffer layer thickness. Figure 9. Photograph of the cross-sectional structure Figure 8. Trade-off relationship between V F and Erec IV. ELECTRICAL CHARACTERISTICS OF THE NEW CHIPS The 6 th generation IGBT (CSTBT TM ) is fabricated using LSI fine-pattern technology and thin wafer process technology for the purpose of improving the V CE(sat) -E OFF trade-off relationship. The effect of the CS layer can be enhanced by narrowing the trench pitch of the unit cell using fine pattern technology. A. IGBT Fig. 9 shows a photograph of the cross-sectional structure at the MOS surface of a CSTBT TM chip. The 6 th generation 1200V/13A IGBT(CSTBT TM ) with effective area of 8.3mm 2 possesses a high turn-off capability more than 600A/cm 2 under the conditions of Vclamp=1200V, V GE =+17V/-15V, Rg=30Ω and Tj=125 C. Fig. 10 displays the turn-off waveforms and indicates a sufficiently wide reverse bias safe operating area (RBSOA). Figure 10. Turn-off waveform of 6 th generation 1200V/13A CSTBT The new CSTBT TM proposed here with higher current density and lower V CE(sat) does not sacrifice wide SCSOA owing to the narrow and controllable distribution of V GE(th) (as shown in Fig. 4). Fig. 11 shows the waveforms at SCSOA test. The new CSTBT TM exhibits wide SCSOA with more than 10µs short circuit withstand time under the test conditions of Vcc=800V, Tj=125 C, and inductive load. B. Diode Thin wafer process and optimized design lead to the decrease of V F. In this work, the V F of the new diode is about 1.8V at J F =250A/cm 2, while the corresponding Erec is about mj/a/pulse which is about 30% lower than that of the 5

6 conventional one (wafer thickness of 115µm) as described in Fig. 8. More importantly, a lightly doped buffer layer can effectively inhibit oscillation during reverse recovery operation. The reverse recovery waveform is shown in Fig. 12, where the design investigated in this work is compared with the conventional diode. It is clear that the tail current of the new diode at reverse recovery operation is reduced, which contributes to a lower Erec and thus a better trade-off relationship (Fig. 8). Figure 13. FOM of 6 th generation CSTBT Figure 14. FOM of new diode Figure 11. Waveforms at SCSOA test C. Comparison of FOM For IGBT, the FOM of the newly developed fine pattern 6 th generation CSTBT TM is compared to the conventional 5 th generation IGBT, where the latter is normalized to 1 (as shown in Fig. 13). The FOM of new CSTBT TM indicates that it is 30% higher than that of the conventional 5 th generation CSTBT TM, which is associated with the reduction in total losses by applying fine pattern technology to increase trench density and by optimizing the doping profile to offer a stable trans-conductance characteristic For the diode, a similar comparison between FOMs with rated voltage of 1200V is shown in Fig. 14, where the conventional diode is used as a reference. The FOM is defined as the quantity of J C, divided by the product of V F and Erec. The FOM of new diode is about 30% higher than that of the conventional one. Figure 12. Reverse recovery waveform of new and conventional diodes V. CONCLUSION A new design concept of doping profile and fine pattern technology was proposed. The newly developed IGBT and diode chips demonstrated here will be introduced in the next generation IGBT Power Modules to improve performance with lower switching and conduction loss. The new technologies show great potential for improved efficiency in the industrial motor drive applications of power semiconductor electronics. 6

7 REFERENCES [1] G. Majumdar and T. Minato, PCC Nagoya, LS1-1-2 (2007) [2] H. Takahashi, H. Haruguchi, H. Hagino, and T.Yamada, Carrier Stored Trench-Gate Bipolar Transistor (CSTBT) - A Novel Power Divice For High Voltage Application," ISPSD 96, pp (1996) [3] K. Nakamura, S. Kusunoki, H. Nakamura, Y. Ishimura, Y. Tomomatsu, and T. Minato, Advanced Wide Cell Pitch CSTBTs Having Light-Punch-Through (LPT) Structure, ISPSD 02, pp (2002) [4] J. Yamashita, A. Uenishi, Y. Tomomarsu, H. Haruguchi, H. Takahashi, I. Takata, and H. Hagino, A Study on the Short Circuit Destruction of IGBTs, ISPSD 93, pp (1993) [5] A. Porst, F. Auerbach, H. Brunner, and G. Deboy, Improvement of the Diode Characteristics Using Emitter-Controlled Principles (EMcon-Diode), ISPSD 97, pp (1997) [6] K. Satoh, K. Morishita, Y. Yamaguchi, N. Hirano, H. Iwamoto, and A. Kawakami, A Newly Structured High Voltage Diode Highlighting Oscillation Free Function in Recovery Process, ISPSD 00, pp (2000) [7] F. Hille, M. Bassler, H. J. Shulze, E. Falck, H. P. Felsl, A. Schieber, and A. Mauder, Discrete and Half-Bridge Module Using GaN HFETs for High Temperature Applications more than 200 Deg. C, ISPSD 07, pp (2007) [8] T. Takahasi, Y. Tomomatsu, and K. Sato, CSTBT As the Next Generation IGBT, ISPSD 08, pp (2008) 7