DAC at 50: The Second 25 Years

Transcription

1 50 Years of DAC: Wat Lies Aead DAC at 50: Te Second 25 Years Rob A. Rutenbar University of Illinois at Urbana-Campaign Editor s notes: Tis paper is based on an invited talk presented at te 50t DAC. It provides an interesting analysis of te past 25 years of te EDA industry and te Design Automation Conference by dividing tis period into five distinct eras of tecnological advancements. VYervant Zorian, Synopsys one because of its active entrepreneurial ecosystem, engaged broadly across academia, startups, and larger establised EDA companies. But againvwo makes te list, and wo does not? HOW DOES ONE survey a quarter century of tecnical contributions at a world-class venue like te Design Automation Conference? Tis was te daunting callenge I faced wen asked to survey te second 25 years of DAC s istory at te 50t anniversary conference event in One can imagine several strategies, for example: Identify a set of greatest its tecnologies and metods. Tere were assuredly many suc breaktrougs across tese years. But ow to winnow te list to someting of manageable lengt, witout sligting an important idea or innovation? Identify a set of most important EDA tools from tese years. Te way we make impact is to deliver working software and flows to our friends in te design community. But tis underweigts te long and winding pat troug ideas and experiments publised at DAC, wose exploration necessarily precedes eac delivered tool. Identify a set of te most important EDA startups from tese years. Our industry as been a vital Digital Object Identifier /MDAT Date of publication: 25 Marc 2014; date of current version: 19 May Attempts to enumerate Best Of... lists seem destined to miss someting vital. I decided tis survey needed a better idea. DAC : A Big Data approac Today, everyone working in information-related fields is part of te Big Data revolution. Data as tese new scales dramatically canges te ways we interact wit tecnology, among oter tings. A central tenet of te data revolution is te idea of letting te data speak for itselfvtat is, diving deeply into tese raw information streams and pulling out te patterns we find tere. Tis suggests an approac for our survey task. Let us consider te source data as te set of all papers publised at DAC over tese second 25 years. Tis is DAC 1989 to DAC 2013 (toug, for expedience, I only surveyed up to 2012). Figure 1 sows te raw paper counts across tese years. I do not count te myriad special sessions at DAC, since tese are difficult to label in terms of teir tecnical focus. (For example, panel sessions often comprise a range of conflicting views on tecnical matters.) I looked at te papers in eac session, and ten categorized te entire session itself as being part of one specific tecnical area, e.g., syntesis, layout, power, codesign, nanometer effects, etc. I tracked paper counts across eac tecnical category, across all years. In tis way, I categorized every papervalmost /14 B 2014 IEEE Copublised by te IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC IEEE Design & Test

2 Figure 1. Count of tecnical papers publised at DAC from 1989 to suc papersvacross all tese years, by teir tecnical focus. Tese categories are, of necessity, te autor s coice, and so may exibit some unintentional biases. I tried very diligently to maintain a broad and balanced outlook across tese papers, and to use category labels tat were widely understood by te general DAC audience and EDA community. And, of course, any errors of counting are my responsibility. I believe te final results are extremely illuminating. My starting ypotesis was tat te broad tecnical areas of EDAVas measured by paper countsvwould tell te overall narrative of wat eac year was like in our community. Some years were calm, some were ecticveven panicked. Problems broke into te consciousness of te DAC community, and solutions arose to combat tem. Tecnical areas were born and grew, and dominated te scene for some number of years. But ten just as naturally, tey ebbed, as te core problem tey addressed was solved. Some areas effectively disappeared, but just as often, groups of related subareas merged into a new area wit a different, refresed focus. I believe te paper count data does a lovely job of telling te story of te second 25 years of DAC. To narrate tis story in a clear way, I ave broken te data into a set of five alf-decade acts (wit due apologies to Sakespeare), and sow te category/ count data by tecnical area for eac of tese fiveyear epocs. ACT I, DAC : Age of te core flow Figure 2 sows a first attempt to count and categorize our first five-year epoc. Te tecnical areas are, I tink, well understood: Design environments, RTL & languages, Hig-level syntesis, Logic syntesis and mapping, layout, etc. But wile te data migt naturally fall into finely partitioned categories (tere are 14 suc categories in tis Act), I quickly discovered tis was too muc detail from wic to pull out key trends driving te industry and community. Figure 3 sows my proposed solution: anoter round of categorizing, clustering, and counting, to reduce tis fine-grain data to a andful of macro trends. At tis level of detail, te big trends are clear and crisp. Tis is te age of te Core Flow, were te DAC community built te foundational syntesis and verification tecniques tat allow us today to pus a button, and turn 50,000 lines of Verilog into 1M gates of working, reliable logic. Tere are four big areas in tis act, as follows. Core Syntesis: Tis is work focused on databases and design environments, on RTL language issues, on beavioral syntesis, on logic syntesis and tec mapping. Core Verification: Tis is work focused on bot logical and electrical (circuit) simulation, on test, and on te real beginnings of formal metods. Trending Timing & Interconnect: Here, we clearly see te beginnings of growt in tis as an area of Marc/April

3 50 Years of DAC: Wat Lies Aead and analog and mixed-signal EDA tools as serious areas of inquiry for te community. Figure 2. ACT I, DAC Paper counts and categories. (We omit detailed paper counts in tis and subsequent figures, to focus on relative trends in eac area.) concern, as designs became larger, ran faster, and began to be realized in less friendly scaled tecnologies. Emerging FPGA & Analog: Here, we also clearly see te emergence of new non-asic areas of focus.tisactisterealstartofbotfpgas Figure 3. ACT I, DAC revisited: Age of te core flow. Tere were numerous important firsts in tis epoc. Tere were many new data structures and algoritms and work across all levels of te design ierarcy: gates, transistors, and sapes. Breaktrougs in formal metods involving Binary Decision Diagrams and model cecking. Te first moment metods to analyze te electrical delay of wires. Te first accurate probabilistic models of switcing for power estimation of logic. Te first descriptions of scripting-based languages designed to create complex design flows. From our vantage point twenty years later, it is quite satisfying to see ow many of tese early ideas actually got real in today s tools and flows. ACT II, DAC : Age of Deep Submicron (DSM) Figure 4 sows paper counts and categories for tis next act. To focus on te critical emerging trends, I cluster some separate areas from te previous epoc in tis new cart. So, syntesis and layout are now clustered as one very important areavindeed, te largest single area. But tis is also clearly an area tat was gradually srinking in tese years, a victim of its own stunning successes. Verification and test remain important, toug we note te rise of te term functional verification in tis era, empasizing tat te end goal is to make our systems function, and not just watc waveforms on transistors and gates. We also cannot ignore te emergence of formal verification as an area of sufficient substance to make it into our category list. FPGAs and analog continue to be areas of interest, but tey ave not yet broken out as bigger focus topics for DAC in tese years. Te new emergent area is embedded systems. We see in tese years te rise of embedded computing as a separate area, wit a range of modeling, optimization, estimation, 34 IEEE Design & Test

4 Figure 4. ACT II, DAC : Paper counts and categories. and codesign problems tat merit its own category in our count. But te real story ere is te focus on timing, interconnect, and power. Figure 5 tries to igligt tese key trends by focusing on just tese categories, and te related area of design case studies, labeling te paper counts by te targets of optimization: MHz, Watts, cost, complexity.tisisteageof Deep Submicron (DSM),teerawentecoreflowof te previous era stopped working. Tese were scary years for our readers wo did not live troug tem. Starting at around te 130-nm or 90-nm CMOS nodes, our cerised syntesis, layout, and timing/power closure solution began to fail. Previously, we could syntesize logic, ignoring te subsequent pysical layout, and te fact tat wires temselves ad complex sapes, and real delay. Simple expedients like overdesign, timing margins, a few extra buffers to fix recalcitrant critical pats, failed in te face of designs wit many more gates, on muc larger die, operating at muc greater clock speeds. Many ASICs could not be closed, tat is, tey could not be tweaked to meet timing. Even worse, wen tweaked, te resulting power was unsupportable. Many cips died an ignoble deat, moving troug respin after respin, casing a timing/power target tat was never to be. Many suc design teams simply ran out of funding before te cip ever reaced te market. Figure 5 sows clearly te emergence of te DSM closure crisis; by 1998, fully a tird of te entire DAC conference was focused on tese topics. Case study Figure 5. ACT II, DAC revisited: Age of Deep Submicron (DSM). Marc/April

5 50 Years of DAC: Wat Lies Aead Figure 6. ACT III, DAC : Paper counts and categories. sessions alone were ugely popular, as grizzled veterans of te DSM wars sared orror stories, news of ard-fougt battles, and tactical tecniques to avoid getting killed oneself. Te good news from tis rater dire narrative is, of course, tat we fougt te battle, and we won. Te DAC community marsaled its efforts, focused its immense talents on te problem, and progress was made. To cite just one example: we now understand wat a term like pysical syntesis means. Tat logic syntesis must take basic account of layout geometry, of likely wiring problems, and te overall pysical design. And layout design must be able to resyntesize and retime problematic blocks to meet difficult specification. And tat timing and especially power are metrics tat must be integrated into every step of te core flow. ACT III, DAC : Rise of systems & eterogeneity Figure 6 sows paper counts and categories for tis next act. As before, to focus on te key trends, I cluster areas from te previous epoc in tis new cart. Tus, syntesis, layout, verification and test are now clustered as one super area, accounting for fully a tird of te total DAC paper count. Tis is our new core flow for te new century, responsible for continued focus on te basic foundation of tecniques to build and validate te increasing complex designs of te era. Likewise, timing and interconnect ave been merged into a super-area called closure, to recognizeteimpactoftedsmcrisisonteentire EDA community. Te story beind te power area in Figure 6 is a bit nuanced. Te trend line suggests a diminution of interest; tis is empatically false. Wat actually appens ere is tat fewer DAC sessions are uniquely about power, wile more DAC papers simply embrace power as an essential topic tat must be included. To say it differently: almost all te papers start toucing on power issues, in some way. Te clear emerging area is around nanometer effects, wic appear in tis epoc for te first time, in a big way. In tese years, we stop saying deep submicron, and we start saying nanometers. Litograpy papers appear. Models of te statistical problems wit variable process parameters, especially tresold voltage, appear. Tere is te first tentative discussion of an end of roadmap scenario for CMOS and Moore s Law. Te clear breakout trend, owever, is te rise system design concerns, across a great range of eterogeneous platforms. Figure 7 igligts tese 36 IEEE Design & Test

6 areas, again labeling te trend counts wit te targets of tese many papers. We see in tese years a great blossoming of EDA for a new range of targets: not just ASICs but also ASIPs; not just digital but also analog and mixed-signal and RF; not just FPGAs but also a broader range of reconfigurable platform designs;andabroadandmature view of ardware versus software issues across all of tese platforms. To cite just one celebrated example, te very first work on Network-on-Cip arcitecture appeared at DAC in 2002, in te middle of tis explosion of eterogeneity. ACT IV, DAC : Age of uncertainty Figure 8 sows paper counts and categories for tis next act. As before, some super-areas appear as clusters of separate topics in tepriorera.tecoreflowsuper-areadominates rougly 40% of te conference, and now also includes topics in power and termal management, wic are spread widely among syntesis, layout, and verification topics. Te systems area is also substantial, and includes a broad array of work on embedded, SOC, multicore, reconfigurable, and analog platforms. An interesting new area arises: Communication. For te first time, tere are entire sessions about SOC-scale communications arcitectures, focusing on networking, busses, communication protocols, IP and te like, for ow to get information from one end of a uge cip to te oter. Nanometer effects also occupy a notable fraction of te conference, wit te addition of Figure 7. ACT III, DAC revisited: Rise of systems & eterogeneity. new focus on reliability and post-silicon debug as novel topics. We see te first papers on EDA issues working to ensure tat, after manufacturing test, designs do wat we expect tem to over teir Figure 8. ACT IV, DAC : Paper counts and categories. Marc/April

7 50 Years of DAC: Wat Lies Aead Figure 9. ACT IV, DAC : Age of uncertainty lifetime. Likewise, we see te first EDA tools to address issues in post-silicon debug and tuning, as cips increasingly require tweaks post-fab. Emerging tecnologiesveiter non-silicon or post- siliconvalso become more prominent as topics of real EDA concern in tis epoc. Tis is te era in wic te reality of an end to Moore s Law scaling was finally accepted as a fact of life. Figure 9 sows an attempt to capture te macro trends in tis area. Wen one looks carefully at te full range of publications, te one striking pattern is te rise of probability and statistics as te foundational mode of tinking about most EDA problems. Tus, I am tagging tis as te age of uncertainty. Foundry fabrication parameters are statistical and uncertain. Yield, timing and power are uncertain. Communications are uncertain. Cip reliability and post-debug performance is uncertain. Tis is te era of te demise of determinism, te era wen everyting interesting is a random variable, or a correlated smear of probability. Yet, even in tis new and callenging milieu, te EDA community made substantial progress. Design became uncertain, but we became proficient in building statistical models tat let us cope. Finally, one oter related uncertainty area rose to prominence in tis era: security. We saw te first papers on security issues as being topics of fundamental interest to EDA tools and platforms. And we saw te first steps toward addressing trust issues in semiconductor supply cains: if my cip is designer ere, and fabricated tere, and used yet elsewere, ow do I trust tat it was not tampered wit? Figure 10. ACT V, DAC : Paper counts and categories. ACT V, DAC : Age of applications & adjacencies Figure 10 sows paper counts and categories for tis final act. Two super-areas comprise rougly alf of te wole DAC universe: te core flow (syntesis, layout, verification, test), and te broad nanometer variability area (including reliability and debug). Tis comes as no surprise: te core flow is 38 IEEE Design & Test

8 always te target for some form of improvement, and in today s designs, it is te nanometer effects tat dominate. Trust and security, and 3D packaging also appear as an area of note. But te breakout areas in tis final act focus on applications, as sown in Figure 11. Tis is te age of applications and adjacencies. Applications ave always driven te design community, and as a consequence te EDA community. We focus on embedded power, for example, because of te explosion of mobile appliances. But looking in detail at te DAC papers from tis era, one sees a dizzying array of diverse new applications: mobility, computing, communications, security, energy, cloud, ealt, medicine, etc. And one sees attempts to wrestle wit te landscape of emerging tecnologies in bot te post-silicon and non-silicon worlds. We ave always focused our efforts on systems, but in tis area, it is largely te applications tat drive te system arcitectures, wic ten drive te EDA focus. Tis is also te age of adjacencies, by wic I meet te business opportunity of adjacent markets. Are tere design problems wit a similar level of complexity, cain of abstractions, interplay of ardware and software, requirements for fres design and desire for IP reuse? Migt we take wat we know of semiconductor oriented EDA and direct it toward tese adjacent opportunities? Te automotive industry is one key adjacency opportunity tat appears frequently in tese years. Medical appliances is anoter. Te striking takeaway from looking at DAC in tis most recent epoc is te combination of a mature tecnology basevte flagsip core flows we ave created, our growing mastery of nanometer unpleasantness at te end of Moore s LawVand te exciting, broad exploration of new domains and new industries were we migt be able to apply not just our tools, but our overall worldview for solving uge and difficult problems. I MUST ADMIT tat, wen I accepted te invitation to undertake tis survey, I did not plan on individually Figure 11. ACT V, DAC : Age of applications & adjacencies. perusing approximately 4000 separate DAC papers. Neverteless, I am appy wit te results of tis experiment. Te trend carts sown in Figs sow a vibrant community growing and adapting, wresting wit uge callenges, and surmounting tem. I am quite optimistic about te future of te next 50 (and more) years of te EDA discipline. Rob A. Rutenbar received te PD degree in 1984 from te University of Micigan, and spent te next 25 years on te faculty at Carnegie Mellon. At CMU, is group pioneered many tools for custom analog circuits. In 1998 e cofounded Neolinear. Inc., to commercialize tis work, and served as Cief Scientist until its acquisition by Cadence in He as also worked extensively on nanoscale silicon statistics. In 2010 e moved to te University of Illinois at Urbana-Campaign, were e is Bliss Professor and Head of Computer Science. He as won numerous awards in is career, including tree DAC Best Papers. He won te 2001 SRC Aristotle Award, acknowledging te impact of is students on te US Semiconductor industry. Most recently, e sared te 2013 Donald O. Pederson Best Paper Award for IEEE Transactions on CAD. He is a Fellow of te IEEE and te ACM. Direct questions and comments about tis article to Rob A. Rutenbar, University of Illinois at Urbana- Campaign. Marc/April