sketch a simplified small-signal equivalent circuit of a differential amplifier

Transcription

1 INTODUCTION Te large-signal analysis of te differential amplifr sowed tat, altoug te amplifr is essentially non-linear, it can be regarded as linear oer a limited operating range, tat is, for small signals. In tis lesson, we analyze te smallsignal beaiour of te amplifr using te -parameter model to determine ow component and parameter alues affect performance. It is also sown ow te properts of te current mirror can be used to improe te differential gain of a single-ended output differential amplifr. YOU AIMS On completing tis lesson, you sould be able to: sketc a simplifd small-signal equialent circuit of a differential amplifr derie te small-signal differential and common-mode gains of a differential amplifr from its equialent circuit analyze te effects of a single-ended output upon te differential and common-mode gains sow ow te performance of a differential amplifr can be improed by te use of current mirrors. Teesside Uniersity 202

2 2 STUDY ADVIC We are already familiar wit te equation I I I C s ev exp kt By differentiating tis equation wit respect to V B, we can obtain a relationsip between collector current and te dynamic base-emitter resistance of a transistor. B di dv B e ev Is kt exp kt B e kt I e kt I C dvb Now, di represents te base-emitter junction resistance of te transistor and we will denote tis parameter by r e. If we take te alue of kt/e at room temperature as 25 mv and measure te collector current in milliamperes, we get te ery useful relationsip: r e 25 I Ω C Tis is te junction resistance as seen from te emitter. If tis resistance is reflected into te base, were te current is about fe times smaller, we obtain, approximately, te ybrid parameter. To ace te conersion we multiply r e by fe to gie: r fe e Teesside Uniersity 202

3 3 (We ae multipld by fe so tat i b gies te same olt drop as i e r e, and so te two resistances ae te same effect, altoug tey appear in different parts of te circuit.) Te emitter resistance r e is a ery useful parameter as it is ery easy to ealuate, being determined by only two quantits, te collector current and te operating temperature. For example, a transistor aing a collector current of ma, a current gain of 00 and operating at room temperature will ae: r e 25 ( wit IC expressed in ma) I C Ω and fe e r Ω SMALL-SINAL ANALYSIS OF TH DIFFNTIAL AMPLIFI FIU sows a differential amplifr circuit, wile FIU 2 sows its simplifd, small-signal -parameter model. In drawing te equialent circuit, te usual assumption as been made tat, for a.c. signals, te power suppls can be regarded as sort circuits. Also, in te interests of conciseness, we ae labelled te input currents as simply i and i 2 rater tan i b and i b2. Teesside Uniersity 202

4 4 +V CC C C o T T 2 2 V FI. C o o o2 C 2 i fe i fe i 2 i 2 V FI. 2 Teesside Uniersity 202

5 5 Let's begin te analysis by establising some basic relationsips. Applying Kircoff's oltage law to te inputs gies te following two equations: ( + ) i + i + i2 fe... ( + ) i i i fe... 2 () Also, by Om's law, te collector oltages can be written in terms of te collector currents: o fe C i o2 fec i ( 4) From (3), making i te subject: i o fe C... ( 5) (a result we will use later) Subtracting (2) from () gies: 2 i i and making i 2 te subject: i i ( 7) Teesside Uniersity 202

6 6 To determine te double-ended differential oltage gain of te circuit Subtracting (4) from (3) gies: i i o o2 fe 2 C and, from (6), substituting for (i oltage gain as: i 2 ) gies te 'double-ended' differential o o2 fe C 2 Tat is: VD fec... 8a We can now apply te relationsip obtained in te study adice to express te differential gain in terms of te base-emitter junction resistance: VD C... 8b r e Determination of te single-ended differential oltage gain of te circuit stablising tis gain requires muc trickr algebra, as we must obtain an expression for just o (or o2 ) in terms of te input oltages. So take a deep breat and ere we go! Teesside Uniersity 202

7 7 Substituting (7) into () for i 2 : i + i + i 2 2 ( + fe ) 2 i + 2i fe ( + ) 2 ( + 2 ( + fe) ) + i ( ) fe Making i te subject: i + 2 ( + fe ) ( fe ) i ( ) ( + ) + 2 ( + ) + + fe 2 fe fe Now substituting for i from equation (5): o fe fe o C C ( ) ( + ) ( i e + 2( + fe) ) fe fe + ( + fe + 2 ( + ) ) 2 fe o + fe C 2 ( + ) + 2 ( + ) fe fe fe C... ( 9) Teesside Uniersity 202

8 8 From te point of w of differential gain, tis equation contains two terms : (i) Te differential term wic gies te differential gain is: ( 2) ( + ) + 2 ( + ) fe fe C fe If te oter term could be reduced to zero (we will see ow tis migt be done later), te equation would become: o 2 ( + ) + 2 ( + ) ( fe fe C fe ) wic gies a differential gain of: VD + o fe fe C ( + ) fe... ( 0) (ii) An error term: fe C fe C ( ( fe )) + + fe If, in equation (9), te two input oltages were equal, te differential term would disappear and we would be left wit: o fe C fe... Teesside Uniersity 202

9 9 We will ae more to say about tis error term sortly, but for te moment let us return our attention to te differential gain. By making a couple of reasonable approximations, muc can be done to simplify equation (0). To see ow tis migt be done, let's put some alues in. Calculate te differential gain, using equation (0), gien tat: kω, fe 00, 0 kω, C 20 kω. Teesside Uniersity 202

10 0 VD ( + fe ) fec ( ) ( ) ( + 00 ) fe Tis calculation as been deliberately carrd out in great detail in order to make te required approximations stand out. Simplify equation (0) by making te suitable approximations. Teesside Uniersity 202

11 Obiously we can say tat ( + fe ) fe wit only a % error or less. Also it is apparent from te calculation tat + 2 ( + fe ) 2 fe as << 2 ( + fe ). Terefore: VD ( + fe ) fec ( ) fe fefec 2 fe giing: VD fe 2 C Tus te differential oltage gain is approximated by: VD fec... 2a 2 VD C 2r e... 2b A differential amplifr uses transistors aing te parameters fe 200 and 000 Ω. If te collector load is 0 kω, calculate te differential oltage gain for bot double and single-ended outputs. Teesside Uniersity 202

12 2 For a double-ended output, VD fec For a single-ended output, te gain will be one alf of tis, i.e Te snag wit te single-ended output is tat we loose alf te gain. We sall inestigate sortly, toug, a cunning tecnique wic lets us ae our cake and eat it! Common-mode gain Te differential amplifr, to be of any alue, must ae a ig differential gain and as low as possible common-mode gain. First, let's consider te double-ended output. If te circuit is exactly symmetrical (i.e. all te corresponding components and parameters are equal), te common-mode output oltage ( o o2 ) will be zero. If te circuit is asymmetrical, as it as to be to some degree in practice, ten a common-mode output oltage will be produced. It can be sown tat te magnitude of tis oltage ( ocm ) is gien, to a good approximation, by ocm icm fe2 fe fe2 fe C2 C C... ( 3) Teesside Uniersity 202

13 3 were te number subscripts refer to eac alf of te circuit and icm is te common mode input oltage. It is immediately apparent tat te iger te alue of te less te common mode output offset. For a good CM, we need a ig alue of emitter resistor. Now let's consider te single-ended output. An output will obiously appear at te collector weneer te transistor conducts. Wat we are interested in at tis juncture is wat te output will be wen te input oltages are equal. For te circumstances under wic equation () as been deried, wat does te oltage ratio represent? o Teesside Uniersity 202

14 4 quation () was deried from equation (9) by setting te differential input oltage ( 2 ) to zero. As te two input oltages are equal, te oltage ratio must represent te common-mode gain. Tus, for a differential amplifr wit ideal components and an emitter resistor, te single ended output common-mode gain is: o icm fe C fe... 4 were icm 2. Making any reasonable assumptions, sow tat te single-ended, common-mode gain is approximately: VC C and ence sow tat te CM for te single-ended output of te differential amplifr of FIU 2 is: fe CM... 6a CM r e... ( 6b) Teesside Uniersity 202

15 5 Assuming tat << 2 ( + fe ), equation (4) becomes: o icm fec fe and as fe >> we can say tat: o fe 2 C fe and terefore: VC C 2 Now, te common-mode rejection ratio is gien by: CM V C VD and using equations (2a) and (5): fec 2 fe CM 2 C r e xpress in decibels te CM of a differential amplifr aing a single-ended output and perfectly matced transistors and collector resistors. ( C 0 kω 20 kω kω fe 200) If te quscent collector current was doubled in alue, wat would be te new CM? Teesside Uniersity 202

16 6 CM is VD fe C C V C 2 2 fe So, for tis example: CM is 4000 or 72 db. 03 If te quscent collector current was doubled, te alue of r e would be aled (r e 25 ). Tis would double te alue of te CM to 8000 or 78 db I C ( as CM r ). Small signal analysis using constant current generator in te tail Te last example again seres to sow tat a ig alue of gies a good CM. Tis requirement is best met by replacing te tail resistor by a constant current generator. FIU 3(a) sows te equialent circuit for suc a configuration. C o o o2 C i fe i fe i 2 i2 i i 2 I V FI. 3(a) Teesside Uniersity 202

17 7 i i 2 2 FI. 3(b) Te constant current generator passes a constant direct current I. Te ideal current generator represents an open circuit, suggested by te dotted lines in te equialent circuit, and so, applying Kircoff's current law to te junction of te emitters for te small signal currents, we obtain: i i + i + i fe 2 fe 2 0 so forcing te conclusion tat: i i Te use of te constant current generator in te tail gies te perfect smallsignal differential amplifr in tat one current will be diminised by exactly te same magnitude as te oter is increased. Wen an emitter resistor is used in te tail, tis relationsip is only approximate. Applying Kircoff's oltage law to te inputs of te circuit (re-drawn in FIU 3(b) ) gies: i + i Teesside Uniersity 202

18 8 so tat (using te relation of (7)): 2 i i2 2 i... 8 Determine te single-ended differential oltage gain of te circuit. Te potential at te collector of T is: i o C fe so tat (from (8)) te differential gain is: 2 2 o fe C In te aboe example, in contrast to te deriation of equation (2), we ae not ad to resort to making any approximations. Teesside Uniersity 202

19 9 If te same signal is appld to bot inputs, wat will be te single-ended output oltage? Hence comment on te CM. From equation (8), if 2 ten te input current must be zero. Tus, tere will be no small signal output oltage. Te common-mode gain will be zero, giing an infinite CM (te best possible). Tis is assuming, of course, perfect circuit symmetry and an ideal current generator (infinite output impedance). Teesside Uniersity 202

20 20 ACTIV LOADS AND TH SINL-NDD OUTPUT We ae seen tat a penalty paid for taking a single-ended output is te aling of gain. It is possible, toug, to replace te collector resistors by a current mirror, wic not only restores and een enances te gain but is also muc easr to implement in integrated circuit form. Te gain of te amplifr is proportional to te collector load resistance, te larger te resistance te greater te gain. But large alue resistors are expensie in terms of silicon 'real estate'; not only do transistors occupy a muc smaller area on te cip, tey are also easr to make. FIU 4 sows te necessary circuit amendments to replace te collector resistors by a current mirror. As transistors are actie deices (in contradiction to passie deices suc as resistors), te load is called an actie or dynamic load. In FIU 4, we ae also replaced te tail resistor by anoter current mirror. Teesside Uniersity 202

21 2 +V CC T 3 T 4 Current mirror: actie load Single-ended output I I 2 V T T 2 V 2 Differential amplifr: long-tailed pair Current mirror: Constant current generator V FI. 4 Wy are pnp transistors used in te actie load? Te transistors are pnp type because te mirror is required to source a current to te two amplifying transistors. Teesside Uniersity 202

22 22 CICUIT ACTION In order to appreciate te action of te circuit, we need to connect a singleended load to one of te collectors of te differential pair. Tis as been done in te incremental model of FIU 5, were te transistors ae been represented by current generators. Te current mirror forming te actie load is represented by current generators 3 and 4, te dotted line between tem intending to sow tat te current in 4 is controlled by tat in 3. Te model is 'incremental' in te sense tat only canges in current are considered, so tat te constant current generator in te tail represents an open circuit V CC I I L I I 2 V 2 V 2 L V L V FI. 5 Now allow te differential input oltage (V V 2 ) to te circuit to cange by V so as to produce a cange in current I from. Te current from 3 will also cange by I and since 3 forms te controlling alf of a current mirror, te current troug 4 will be forced to cange by I. Teesside Uniersity 202

23 23 State te relationsip between I and I 2. Hence, by applying Kircoff's current law to te collector junction of 2, determine te cange in load current in terms of I. Te circuit forms te ideal differential amplifr so tat te cange in current troug 2 will exactly counter tat troug. Tus I 2 I. Summing te cange in currents at te collector of 2 : I I 2 I L 0 and as I 2 I : I + I I L 0 so tat: I L 2 I Teesside Uniersity 202

24 24 Tus, te cange in load current is double te cange produced in (or 2 for tat matter). Consequently, te cange in output oltage V L will also be doubled. Te actie load as restored te oltage gain to tat of a doubleended output! Te actie load also confers oter adantages. Te oltage gain is proportional to te output load resistance L. Tis resistance comprises of te loading of te next stage, te output resistance of te amplifying transistor (T2 in tis example) and te internal resistance of te current generator 4. Tese tree loads will act in parallel to produce an effectie load of L. Te internal resistance of te current generator will be te output resistance of te transistor T4 and will be ery ig (megoms, in fact, for te ery low currents at wic te input stage of an op-amp operates). Te output resistance of T2 will be of a similar order. So, proiding te loading of te next stage is kept minimal, te differential amplifr can be made to delier a useful oltage gain (of te order of 500). We ae already commented upon te impracticability of producing igalued resistors in integrated circuits. Te actie load soles te problem of producing collector resistors by replacing tem wit a pair of transistors, wic are easr to produce and occupy muc less area on te cip. Stage loading on te output of te differential amplifr is minimized by making it drie an emitter follower, wic as a ery ig input resistance. But, before we can moe on to consider te next stage, we must look at some of te problems of coupling d.c. amplifrs. Tis forms te opening topic of te next lesson. Teesside Uniersity 202

25 25 NOTS Teesside Uniersity 202

26 26 SLF-ASSSSMNT QUSTIONS. FIU 6 sows a differential amplifr ariation wic uses just a single collector resistor. All te transistors can be assumed to be identical and te current mirror ideal. +V CC C A B 2 o ICONST V FI. 6 i) Sketc te amplifr's -parameter equialent circuit ii) Derie expressions for te amplifr's: (a) differential oltage gain (b) common-mode oltage gain iii) State wic input is te non-inerting input. 2. FIU 7 sows te small signal equialent circuit of a differential amplifr wit single-ended output. If it cannot be assumed tat te Teesside Uniersity 202

27 27 transistors and collector resistors are identical, sow tat te commonmode gain is approximately gien by VC fe + fe + C fe ( 9) C2 C i 2 2 fe2 i 2 fe i i 2 o FI Sow tat, wen symmetry is assumed, equation (9) aboe can be simplifd to equation (5), namely: VC C 4. Calculate te common-mode gain of a single-ended output differential amplifr using equation (9) and te component and parameter alues gien below. Teesside Uniersity 202

28 28 2 kω, fe fe2 200, 0 kω, C 20 kω Hence, sow tat te simplification of equation (5) is alid. 5. A useful skill to deelop is te ability to recognise particular circuit sapes in a circuit diagram. Tis question gies you a little practice in tis art! FIU 8 sows again our internal circuitry of an op-amp. See ow many current mirrors you can spot. Non-inerting input Inerting input Comp +V CC 34 Ω 39 kω 40 kω 34 Ω Output kω 50 kω kω 5 kω 50 kω 00 Ω Offset null Offset null/comp V CC FI. 8 Teesside Uniersity 202

29 29 6. In te circuit of FIU 9, all te transistors ae a current gain of at least 00 and a minimum output resistance of 20 kω. Also, assume teir base-emitter oltages to be 0.7 V. Te amplifr is to ae a minimum CM of 72 db and a differential gain of at least 400. Determine: (i) te tail current (ii) a suitable alue of F (iii) te alue of C to make te quscent output oltage 0 V (i) te differential gain for te alue of C calculated in (iii) () te quscent oltage at te collector of T3 wit bot inputs at 0 olts. +2V C o T T 2 2 F T 4 T 3 2V FI. 9 Teesside Uniersity 202

30 30 ANSWS TO SLF-ASSSSMNT QUSTIONS. (i) FIU 0 sows te equialent circuit (your labelling may well be different). Te oltage across C is sown negatie as it is in te opposite sense to te output oltage as sown in FIU 6. C o A fe i 2 fe i B 2 i 2 i FI. 0 (ii) (a) Applying Kircoff's oltage law to te inputs gies: i + i from wic: 2 i i Summing te currents at te emitter junction: i + i + i + i 2 2 fe 0 Teesside Uniersity 202

31 3 from wic: Substituting i for i 2 in (20), 2i 2 and, making i te subject, i ( 2) Now, te output oltage o is gien by: o feci and, substituting from (2) for i, 2 2 o fe C wic gies a differential oltage gain of: VD o fe C 2 2 (Te differential gain for tis circuit is exactly te same as for one aing bot collector resistors.) Teesside Uniersity 202

32 32 (b) Te assumption of an ideal current mirror gies te relation: i i 2 as already establised. But also, from equation (20), wen 2 ten: i i 2 Te only condition tat satisfs bot i 2 i and i 2 i is wen i 2 i 0. Tus tere will be no small signal commonmode output oltage and te common-mode gain is zero. (Note tat tere will be a quscent output oltage toug!) iii) Terminal A in FIU 6 is te non-inerting input. 2. Applying Kircoff's oltage law to te two input loops gies: i + i + i fe 2 fe2 i 2 ( + ( + )) ( + ( + )) + i + i 2 2 fe 2 fe2 As fe >> for bot transistors, we can make te approximation : i + i + i fe 2 fe i + ( i + i )... ( 23) fe 2 fe2 Teesside Uniersity 202

33 33 Under common-mode conditions, 2 icm, so tat equations (22) and (23) can be equated: + ( + fe2 ) i + i + i i i i fe 2 fe2 2 2 fe 2 and so i i 2 2 i 2 i Te output oltage ( o ) is gien by: o Cfei from wic: i o C fe... ( 25) (Te minus sign as ad to be included because of te way o as been defined.) Substituting equation (24) into equation (22) for i 2 : i + i + fe fe2i 2 icm for a common-mode input icm + fe + 2 fe2 i Teesside Uniersity 202

34 34 Now substituting for i from equation (25): icm + fe + 2 fe2 o C fe VC o icm C fe + fe + 2 fe2 3. quation (9) is: VC fe + fe + C fe2 2 and wen, and, ten: fe C V C + 2fe C C2 fe fe2 2 and, assuming << 2 fe, VC C 2, as required. 4. quation (9) is: VC fe + fe + C fe2 2 Teesside Uniersity 202

35 35 Substituting te alues gien, VC Using te simplification of equation (5), VC C Te simplification works because << 2 fe. 5. Tere are 5 current-mirrors in te circuit, as igligted in FIU. You migt not ae included te mirror in te bottom left and corner, as it is a modifd form. Tis circuit element in fact forms te actie load of te differential amplifr and te extra transistor as been added to improe still furter te performance of tis stage. Teesside Uniersity 202

36 36 Non-inerting input Inerting input Comp +V CC 34 Ω 39 kω 40 kω 34 Ω Output kω 50 kω kω 5 kω 50 kω 00 Ω Offset null Offset null/comp V CC FI. 6. (i) Te CM is gien by: CMM r Teesside Uniersity 202

37 37 In tis example te tail resistor is formed by te output resistance of T3. Tus > 20 kω. We can now find r e : r CMM Ω Te relationsip r e 25/I C enables te tail current to be calculated: I C 25 r ma (ii) Te current troug F fixes te tail current F Ω (iii) Te tail current splits into two to gie eac transistor a quscent collctor curent of 2.5 ma. For te output to be at zero olts, 2 olts will ae to be dropped across C. Tus, te required alue of C is: 2 C 48. kω (i) VD C 2r e Tis is comfortably aboe te minimum specifd. () Te quscent output oltage is 0 olts so te collector of T3 will be 0.7 olts below tis, i.e. 0.7 olts. Teesside Uniersity 202

38 38 SUMMAY For te differential amplifr wit double-ended output, te differential gain is gien by: VD fec... 8a C V D... 8b r e and, for te single-ended output amplifr: VD fec... 2a 2 VD C 2r e... 2b Te ideal double-ended output amplifr will ae zero common-mode gain. Te single-ended output amplifr will ae a common-mode gain of: VC C giing a common-mode rejection ratio of: fe CM... 6a or CM r e... 6b Teesside Uniersity 202

39 39 Current mirrors are used in te differential amplifr to: (a) proide a near constant tail current wic gies a muc improed CM. (b) proide an actie load, so restoring te gain of te single-ended output to its optimum alue. In integrated circuit tecnology, te use of current mirrors to replace large alue resistors not only improes performance but also makes manufacture easr and reduces te area of silicon required. Teesside Uniersity 202