Photomask. Etched multilayer EUV mask fabrication for sub-60 nm pattern based on effective mirror width N E W S. Take A Look Inside:

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1 Potomask BACUS Te international tecnical group of SPIE dedicated to te advancement of potomask tecnology. November 2016 Volume 32, Issue 11 Etced multilayer EUV mask fabrication for sub-60 nm pattern based on effective mirror widt Noriko Iida nee Sakurai, Kosuke Takai, and Takasi Kamo, Tosiba Corporation (Japan) Yasutaka Morikawa and Naoya Hayasi, Dai Nippon Printing Co., Ltd.(Japan) 1 Komukai Tosiba-co, Saiwai-ku, Kawasaki , Japan ABSTRACT Wit srinking pattern size, mask 3D effects are estimated to become stronger, suc as orizontal/ vertical sadowing, best focus sifts troug pitc and pattern sift troug focus. To reduce tese mask 3D effects, we ave proposed etced multilayer EUV mask structure and ave also reported on te fabrication process of etced multilayer EUV mask, in wic line and space mask patterning as been demonstrated. And by using etced multilayer EUV mask, te reduction of mask 3D effects is experimentally demonstrated. In our previous study, we ave sown etced multilayer EUV mask as enoug durability against cemical erosion in suitable cleaning process. In tis work, to meet te demands of different variation on pattern in etced multilayer mask, especially fabrication process for sub-60 nm pattern based on effective mirror widt in dark-field exposure is studied. 60 nm pillar pattern on mask is obtained using negative tone resist wit keeping resolution of line and space pattern. We also examined CD caracteristics 60 nm line and space pattern in consideration of effective mirror widt. Tis work represents tat etced multilayer EUV mask is ready for dark-field exposure of 15 nm pattern in wafer. Introduction Wit srinking pattern size at 0.33NA EUV litograpy systems, mask 3D effects are estimated to become stronger, suc as orizontal/vertical sadowing, best focus sifts troug pitc and pattern sift troug focus. [1] It was estimated tat etced multilayer EUV mask is effective in reducing mask 3D effects at 0.33NA wit litograpic simulation, and it was also experimentally demonstrated wit NXE3300 EUV litograpy system. [2] But it was also mentioned tat mask error enancement factor (MEEF) of etced multilayer EUV mask is unexpectedly larger tan conventional EUV mask. And tis implies tat effective mirror widt of etced multilayer pattern is smaller tan pysical pattern widt measured by CD-SEM. Take A Look Inside: Industry Briefs see page 6 Calendar For a list of meetings see page 7 Figure 1. Process Flow. PMJ

2 Editorial Can we win EUVL Olympics? Micael Watt, Sin-Etsu MicroSi Inc. Artur Balasinski, Cypress Semiconductor Corp. Te Olympics ave finised just a few monts ago in Rio and I enjoyed watcing many ours of great competition. A few weeks later wile on a trip to Japan and wit 14 ours to let my mind wander I began to tink; wat If we looked at te great semiconductor races for new tecnology introduction or market dominance from simple tasks to te future wit EUV manufacturing, mask and pellicle production. Te question, ow would some of tese races and callenges compare in te Olympic arena. Te introduction of EUV is one of te most talked about subjects at all semiconductor conferences and te anticipated start is similar to olding your breat before te start of te 100 meters, wen is te Usain Bolt moment tat everyone wants to see? Will it be faster tan we tougt possible, better tan before and dominate te scene for te foreseeable future? Maybe we are more like te Triatlon wit multiple tasks needing to be completed amongst fierce competition. How would te maraton compare, continually aving to look for someting to give you more energy after a very long slog in years rater tan ours. Te callenges of better power sources, mask development, pellicle design, software algoritms, uptime and availability, to name but a few. Tis must be te Decatlon of our business, continually aving to searc for more power te agility to cange direction and seer stamina to make it to te finis line. One ting really different between te Olympics and te semiconductor races is tat our disciplines do not wait for one moment of glory and, terefore, our races are by far less nerve-wrecking. Surely, we ave our dose of adrenalin, but we do not bank everyting on a performance lasting often less tan a minute in a four-year cycle. We do not train for years and years for tis one cance in a lifetime (OK, maybe two cances), to risk all tis training for a day of upset stomac or a sprained muscle wen tat critical minute arrives. We are free to make poor decisions, and even stick to tem for a long time, making a nice living all along. So, one result of tis juxtaposition of te Olympics and te semiconductor business is tat we are far more blessed. But wile people would probably never lose teir appetite to watc sports, making it a safe bet to compete in te Olympics (for tose wo are good enoug to ave tat glorious moment and ten deserve te everlasting glory), te patience to wait for te improved litograpy systems is running tin, and te fans can be soon relegated to te basement. Wen we read about 200 mm fabs staging teir comeback and te IoT products requiring more firmware tan silicon support, we know EUVL needs to urry, or it may not only not win, but even not make it to te finis line. BACUS News is publised montly by SPIE for BACUS, te international tecnical group of SPIE dedicated to te advancement of potomask tecnology. Managing Editor/Grapics Linda DeLano Advertising Melissa Farlow BACUS Tecnical Group Manager Pat Wigt 2016 BACUS Steering Committee President Paul W. Ackmann, GLOBALFOUNDRIES Inc. Vice-President Jim N. Wiley, ASML US, Inc. Secretary Larry S. Zurbrick, Keysigt Tecnologies, Inc. Newsletter Editor Artur Balasinski, Cypress Semiconductor Corp Annual Potomask Conference Cairs Peter D. Buck, Mentor Grapics Corp. Emily Gallager, IMEC International Cair Uwe F. W. Beringer, UBC Microelectronics Education Cair Frank E. Abboud, Intel Corp. Members at Large Paul C. Allen, Toppan Potomasks, Inc. Micael D. Arculetta, RAVE LLC Brian Ca, Samsung Electronics Co., Ltd. Jerry Cullins, HOYA Corp. USA Derren Dunn, IBM Corp. Tomas B. Faure, GLOBALFOUNDRIES Inc. Brian J. Grenon, Grenon Consulting Jon Haines, Micron Tecnology Inc. Naoya Hayasi, Dai Nippon Printing Co., Ltd. Bryan S. Kasprowicz, Potronics, Inc. Patrick M. Martin, Applied Materials, Inc. Sane Palmer, Nikon Researc Corp. of America Jan Hendrik Peters, Carl Zeiss SMT GmbH Mose Preil, KLA-Tencor Corp. Douglas J. Resnick, Canon Nanotecnologies, Inc. Tomas Struck, Infineon Tecnologies AG Bala Tumma, Synopsys, Inc. Micael Watt, Sin-Etsu MicroSi Inc. P.O. Box 10, Bellingam, WA USA Tel: Fax: elp@spie.org 2016 All rigts reserved.

3 Volume 32, Issue 11 Page 3 Figure 2. EUV reflectivity-based measurement. Figure 3. CD measurement form TEM image. We ave sowed cross-sectional TEM image of etced multilayer EUV mask pattern, and tere is silicon oxide film along te pattern sidewall as a passivation film. Tis is wat makes te difference between pysical pattern widt and effective mirror widt made up of Si/Mo multilayer widt. [3],[4] It is necessary to consider te effective mirror widt because our previous discussion of mask CD was based on pysical widt measured by SEM. In order to obtain te fidelity of pattern, we designed pattern based on effective mirror widt. Tat is, we apply mask bias equal to side wall film widt to writing data. We ave demonstrated dense pillar 72 nm or less collapsed using positive tone resist, but from te purpose of fabricating etced multilayer EUV mask for dark-field exposure, negative tone resist wic leads to smaller writing area is better coice. Because of smaller writing area, negative tone resist process as lower writing time and less scattering electrons, wic generate better pattern profile of resist. In tis work, we demonstrate a fabrication of 60 nm (15 nm on wafer) pattern in etced multilayer EUV mask using negative tone resist and evaluated etced multilayer EUV mask pattern based on effective mirror widt. 2. Experimental Setup and Condition 2.1 Process flow Fig.1 sows te process flow of etced multilayer mask. In order to fabricate fine multilayer pattern, ard-mask process is selected. 20-pair of Si/Mo multilayer, Ru-cap layer and ard-mask material are serially stacked on a substrate. Negative tone resist tat is cemical amplifier resist (N-CAR) in tis work on ard-mask is exposed by EB writer, and desired pattern of negative tone resist is generated after Post Exposure Bake (PEB) and pattern development process. Te pattern is transferred to ard-mask and Ru-cap layer and multilayer are serially etced using patterned ard-mask. Finally ard-mask is removed and mask cleaning process is carried out. 2.2 Measuring metods of effective mirror widt In tis work, we use two measuring metods of effective mirror widt, one is EUV reflectivity-based measurement metod and te oter is measurement from TEM image. Since TEM image is not able to measure wole mask pattern, we also us EUV reflectivity-based measurement to evaluate pattern distribution in wole mask. EUV reflectivity-based measurement is one of te model-based metod and te essences of tis metod are noted below; - Measuring EUV reflectivity of patterned area. - Fitting to simulation result. - Estimation of effective widt. EUV reflectivity is measuring metod of no patterned surface using EUV ligt generically. In tis work, multilayer lines at equal interval are patterned and EUV reflectivity of patterned area is measured. On te oter and, reflectivity simulation is carried out to obtain te relationsip between effective mirror widt and reflectivity of patterned area. By comparison of measured reflectivity and simulated relationsip, te effective mirror widt is estimated. A relationsip between estimated widt by tis metod and multilayer widt is illustrated in Fig.2. It as been sown tat estimated effective mirror widt is well matced as effective mirror widt from TEM imaging. [5] We also use TEM image to measure te effective mirror widt. Fig.3 sows our CD measurement from TEM image, and we defined tat effective mirror widt from TEM image is te average of 20 Mo layers widt. In tis TEM image, tere are gray and black layers in cross-sectional multilayer pattern. We detected gray layers is silicon and black layers is molybdenum. And tere is silicon oxide film along te pattern sidewall as a passivation film. 3. Results and Discussion 3.1 Pattern resolution results after cleaning Fig.4 sows te pattern resolution results after cleaning using positive tone resist and negative tone resist by top-view SEM observation. Blue box means pattern is resolved, and red box means pattern is not resolved perfectly. Te designed widt on mask is in te row, and eac item in te column indicates pattern categories; dense pillar, line and space, isolated line, and isolated space. Isolated line is designed tat te pattern widt ratio of line to neigboring line is 1:10. Isolated space is designed as inverted isolated line. Fig.5

4 Page 4 Volume 32, Issue 11 Figure 4. Pattern resolution results after cleaning. Figure 5. Top-view SEM images of pattern using negative tone resist after cleaning. sows top-view SEM images of pattern using negative tone resist after cleaning. 56 nm dense pillar pattern using negative tone resist is obtained wit zero mask bias even after cleaning. Tat is clear improvement in pillar pattern resolution comparing wit positive tone resist we previously evaluated keeping resolution of line and space pattern. 3.2 CD caracteristics based on effective mirror widt We examined CD caracteristics of etced multilayer EUV mask pattern in consideration of effective mirror widt. Fig.6 sows CD uniformity of etced multilayer EUV mask in wole area of 6 inc mask, and CD uniformity of p60 nm line and space in te effective mirror widt is 2.0 nm (3sigma) and effective mirror widt from EUV reflectivity is 58.2 nm. Tis CD uniformity is derived from simulation based EUV reflectivity. CD uniformity catces up te target at 2016 < 2.2 nm (from ITRS2013) also in effective mirror widt. 3.3 Etced multilayer EUV mask profile of 60 nm pattern Fig.6 sows te SEM images of 60 nm pillar pattern based on effective mirror widt. 60 nm pillar pattern is obtained witout collapse even after cleaning process. Effective mirror widt of tis 60 nm pillar pattern is 59.7 nm from TEM image. Summary 60 nm pillar pattern on mask is obtained using negative tone resist wit keeping resolution of line and space pattern. We examined CD caracteristics of etced multilayer EUV mask pattern in consideration of effective mirror widt. CD uniformity of 60 nm line and space pattern is 2.0 nm at 3sigma and mean CD of it is 58.2 nm. And mean CD of 60 nm pillar pattern is 59.7 nm. Fabrication process for sub-60 nm pattern based on effective mirror widt of etced multilayer EUV mask is ready for dark-field exposure. Acknowledgement Te autors would like to tank Tosiba colleagues; Yukiyasu Arisawa for providing simulation results of EUV reflectivity and discussions, Rikiya Taniguci for te discussion of mask metrology tools and is measurements. References [1] V. Pilipsen et al., Actinic caracterization and modeling of te EUV mask stack, Proc. SPIE 8886, 8860B (2013). [2] L.V. Look et al., Alternative EUV mask tecnology to compensate mask 3D effects, Proc. SPIE 9658, 96580I (2015). [3] K. Takai et al., Patterning of EUVL binary etced multilayer mask, Proc. SPIE 8880, 88802M (2013). [4] K. Takai et al., Capability of etced multilayer EUV mask fabrication, Proc. SPIE 9235, (2014). [5] K. Takai et al., Process capability of etced multilayer EUV mask, Proc. SPIE 9635, 96351C (2015).

5 Volume 32, Issue 11 Page 5 Figure 6. CD uniformity of p 60nm line and space. Figure 7. SEM images of 60nm pillar patter.

6 Page 6 Volume 32, Issue 11 Industry Briefs Sponsorsip Opportunities Sign up now for te best sponsorsip opportunities Advanced Litograpy 2017 Contact: Teresa Roles-Meier, Tel: ; teresar@spie.org Potomask 2017 Contact: Melissa Farlow, Tel: ; melissaf@spie.org Advertise in te BACUS News! Te BACUS Newsletter is te premier publication serving te potomask industry. For information on ow to advertise, contact: Melissa Farlow, Tel: melissaf@spie.org BACUS Corporate Members Acupase Inc. American Coating Tecnologies LLC AMETEK Precitec, Inc. Berliner Glas KGaA Herbert Kubatz GmbH & Co. FUJIFILM Electronic Materials U.S.A., Inc. Gudeng Precision Industrial Co., Ltd. Halocarbon Products HamaTec APE GmbH & Co. KG Hitaci Hig Tecnologies America, Inc. JEOL USA Inc. Mentor Grapics Corp. Molecular Imprints, Inc. Panavision Federal Systems, LLC Profilocolore Srl Rayteon ELCAN Optical Tecnologies XYALIS 200mm Fabs on te Rise Solid State Tecnology One year after te debut of te industry s first 200mm Fab Outlook report, SEMI as issued an October 2016 update, wit te report forecasting 200mm fab trends out to SEMI s analysts updated information on almost 200 facilities, including new and closures of existing facilities. Te igest level of 200mm capacity was recorded in 2007 and te lowest following tis peak in Te capacity decline was driven by te 2008/2009 global financial crisis, wic caused te closure of many facilities, and te transition of memory and MPU fabrication to 300mm fabs. Since 2009, installed 200mm fab capacity as increased, and by 2020, 200mm capacity is expected to reac 5.5 million wafers per mont (wpm), toug still less tan te 2007 peak. According to SEMI s data, by 2019, installed capacity will reac close to 5.38 million wpm, almost as ig as capacity in From 2015 to 2020, 200mm facilities are forecast to add 618,000 wpm net capacity. Two applications account for te growing demand for 200mm: mobile devices and IoT. Rising fab capacity from 2015 to 2020 will be driven by MEMS devices, Power, Foundry and Analog. By region, te greatest increases in capacity are expected to be in Cina, Souteast Asia, Americas, and Taiwan. Anoter trend is also observed: 200mm fabs are increasing te capacity to provide process capability below 120nm. Higer capacity does not mean more fabs, but fewer, larger fabs. In fact, te number of fabs in 2020 is almost te same as te count seen in So 2020 capacity eads toward industry igs wile in comparison 2009 ad te lowest levels off te 2007 peak. ttp://electroiq.com/ EUV Litograpy A Double Wammy For Intel Corporation Stock Piyus Arora Wat Is EUV Litograpy? We ave seen several node srinks over te past decade, were eac iteration delivered promising performance, efficiency and power gains. But we ave arrived at a point were srinking nodes furter, beyond 10nm, requires sizable investments, wit little performance gains to sow for. So it s just not feasible anymore to keep up wit node srinks if cips are manufactured te conventional way. Speculative reports suggest tat cips manufactured using EUV litograpy are up to 100 times faster tan teir conventional counterparts. Weter tis claim is true, still remains to be seen. But te next-gen EUV litograpy won t defy te laws of pysics. Te concerning ting for Intel is tat te cipzilla was earlier oping to manufacture 10nm cips using EUV litograpy next year. None of its competitors ad suc an aggressive timeline. But Intel is now looking to deploy EUV litograpy at te 7nm node. Samsung, Taiwan Semiconductor and GlobalFoundries plan to introduce EUV litograpy along te same timeline as well. And witout te EUV advantage, Intel would pretty muc be at par wit its competitors in terms of cip fabrication tecnologies. Its manufacturing lead would srink to noting. Deploying EUV litograpy is an expensive activity, wit eac alpa tool costing as muc as $100 million. Intel is believed to ave already spent $1 billion as of April last year on tese tools. Intel ramped up tese purcases in te ope of deploying te next-gen tecnology commercially next year. Wit te delay of 2 years, Intel would not be generating any returns out of its expensive equipment. It s non-cas depreciation expenses would continue to pile up over te next 2 years, causing a drag on its profitability, witout seeing a single dollar in revenue. So tis could particularly urt Intel s bottom-line. Secondly, wit Intel s manufacturing lead srinking over te next few years, ARM-based server offerings could pick up steam. Qualcomm, AMD and Cavium would get access to same EUV litograpy, at te same nodes, by 2019, wic could teoretically bring te performance of teir cips close to Intel Xeons. So Intel may struggle to curb te growt of ARM-based offerings in te server space, leading to a loss of te revenue and profits. Putting it all togeter Intel as delayed te deployment of a tecnology tat would ave potentially aided in retaining its manufacturing lead. Now, multiple companies will ave similar cip fabrication tecnologies by Tis would be bad for Intel, bot operationally and financially. It needs to get its ouse in order if it wants to curb te growt of its competition. ttp://amigobulls.com/

7 Volume 32, Issue 11 Page 7 About te BACUS Group Join te premier professional organization for mask makers and mask users! Founded in 1980 by a group of crome blank users wanting a single voice to interact wit suppliers, BACUS as grown to become te largest and most widely known forum for te excange of tecnical information of interest to potomask and reticle makers. BACUS joined SPIE in January of 1991 to expand te excange of information wit mask makers around te world. Te group sponsors an informative montly meeting and newsletter, BACUS News. Te BACUS annual Potomask Tecnology Symposium covers potomask tecnology, potomask processes, litograpy, materials and resists, pase sift masks, inspection and repair, metrology, and quality and manufacturing management. Individual Membersip Benefits include: Subscription to BACUS News (montly) Eligibility to old office on BACUS Steering Committee Corporate Membersip Benefits include: 3-10 Voting Members in te SPIE General Membersip, depending on tier level Subscription to BACUS News (montly) One online SPIE Journal Subscription Listed as a Corporate Member in te BACUS Montly Newsletter C a l e n d a r 2017 SPIE Advanced Litograpy 26 February-2 Marc 2017 San Jose Marriott and San Jose Convention Center San Jose, California, USA SPIE Potomask Tecnology and SPIE International Conference on Extreme Ultraviolet Litograpy September 2017 Monterey, California, USA Te 24t Symposium on Potomask and NGL Mask Tecnology 5-7 April 2017 Pacifico Yokoama Yokoama, Japan Te 33rd European Mask and Litograpy Conference EMLC June 2017 Hilton Hotel Dresden, Germany SPIE is te international society for optics and potonics, an educational not-for-profit organization founded in 1955 to advance ligt-based science and tecnology. Te Society serves nearly 264,000 constituents from approximately 166 countries, offering conferences and teir publised proceedings, continuing education, books, journals, and te SPIE Digital Library in support of interdisciplinary information excange, professional networking, and patent precedent. SPIE provided more tan $5.2 million in support of education and outreac programs in International Headquarters P.O. Box 10, Bellingam, WA USA Tel: Fax: elp@spie.org Sipping Address t St., Bellingam, WA USA Managed by SPIE Europe 2 Alexandra Gate, Ffordd Pengam, Cardiff, CF24 2SA, UK Tel: Fax: spieeurope@spieeurope.org You are invited to submit events of interest for tis calendar. Please send to lindad@spie.org; alternatively, or fax to SPIE.