Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits

Transcription

1 Design and Test of Millimeter-Wave/Subteraertz Circuits and Systems Adaptive Circuit Design Metodology and Test Applied to Millimeter-Wave Circuits J.-O. Ploucart, Benjamin Parker, Bodisatwa Sadu, Alberto Valdes-Garcia, and Daniel Friedman IBM T. J. Watson Researc Center Fa Wang and Xin Li Carnegie Mellon University Miai Sanduleanu Masdar Institute of Science and Tecnology Andreea Balteanu University of Toronto Editor s Notes: Tis paper presents a design metodology of millimeter-wave circuits tat are insensitive to process, voltage, and temperature variations. Instead of using conventional direct sensing, te autors propose an indirect sensing metod wit Bayesian fusion, wic simplifies te sensors and allows more adaptive circuit loops to be integrated. VDeukyoun Heo, Wasington State University integrated in advanced nanometer CMOS are difficult to design using te traditional six sigma circuit design metodology, in part because of teir sensitivities to process ðpþ, supply voltage ðv Þ, temperature ðt Þ, and also to model unknowns, tus motivating new researc work focused on developing self-ealing circuit capabilities [1], [2]. One of te primary goals of self-ealing as been to use oncip sensors, actuators, and algoritms to increase ig-frequency TRx yield. Tis objective can be formalized using te following inequality: M spec;i ðp; V; T ; ActÞ T spec;i ; for all i ¼ 1ton (1) MILLIMETER-WAVE (MM-WAVE) TRANSCEIVERS were M spec;i is te measured specification i, andt spec;i is te target specification i for a set of n specifications. Te measured specifications are functions of P; V; T, and actuators ðactþ. Te circuit specifications are typically derived from system analysis and ardware measurements. By meeting or exceeding te set of TRx circuit specifications, it is possible to acieve a bit error rate target for a given communication cannel. Terefore, te target expression can be reformulated as a single bit-error rate inequality BERðP; V; T ; Can; ActÞ T BER (2) Digital Object Identifier /MDAT Date of publication: 25 July 2014; date of current version: 04 December were T BER is te targeted bit error rate for te communication link. Based on circuit sensor information and driven by a resident algoritm, actuators /14 B 2014 IEEE Copublised by te IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC

2 will be set suc tat adaptive circuits will use te minimum power to transmit data at a targeted bit error rate. As sown by te close relationsip between (1) and (2), self-ealing design tecniques focused on yield maximization may also enable data communication energy minimization. Note tat te biterrorratetargetcanbedependentontetypeof data sent. For example, te bit error rate can be relaxed for voice or picture, and be more stringent for text or code. Even toug te inequality appears to be simple, it in fact represents a complex nonlinear optimization problem. Anoter level of complexity is tat for wireless communication te cannel can cange rapidly wit time. Several initial adaptive radio-frequency (RF) circuits ave already been reported [3] [8]. In [3], an automatic amplitude control circuit was proposed and its feedback ratio was optimized for noise minimization.in[4],aself-calibrated frequency-domain on-cip pase-noise measurement circuit is designed to accurately measure pase noise. In [5], a cost-effective alternative-test-based performance calibration metod is introduced, were a number of performance models are created by considering process and knob variations separately. Tese models are ten used to adaptively configure te knobs and improve te yield during production test. In [6], an ortogonally tunable low-noise amplifier (LNA) is designed, were te performance specifications (i.e., gain and linearity) can be independently controlled to explore tradeoffs between circuit performance and power consumption. In [7] [9], an indirect performance sensing metod is developed to adaptively tune a voltage-controlled oscillator (VCO) to improve its performance and/or yield. Te key idea of indirect performance sensing is to use a set of easily measurable metrics [e.g., direct current (dc) bias current] to predict oter performance metrics of interest tat are difficult to measure by oncip sensors. In tis paper, we describe a design and test metodology wic adaptively configures mm-wave circuits for performance and/or yield enancement by on-cip self-ealing. In te Design and Test Metodology for Adaptive Circuits section, we will review a novel approac, indirect performance sensing based upon Bayesian model fusion (BMF) tat can effectively enable sopisticated mm-wave performance prediction witout demanding integrated mm-wave circuit measurement infrastructure. In te Figure 1. Design of an adaptive circuit must take into account tree critical components: sensing, controlling, and integration. System-on-Cip Arcitecture for Adaptive Circuits section, we present an adaptive system-on-cip arcitecture tat allows te efficient integration of a large number of sensors, actuators, and adaptive control loops. Also, in tis section, we discuss ow to practically integrate ardware, software, and test. Finally, in te Case Study: An Adaptive Millimeter- Wave LNA section, we will sow a design example of an adaptive mm-wave LNA. Design and test metodology for adaptive circuits Designing an effective adaptive circuit is not a trivial task. Te major callenge stems from te requirement tat te circuit must adaptively respond to canges in process and environmental conditions and automatically correct its beavior. In general, tree critical components must be carefully considered for adaptive circuit design, as sowninfigure1. Sensing: Te beaviors and performance variables of an adaptive circuit must be accurately monitored by on-cip sensors. Te power consumption and silicon area of tese on-cip sensors must be minimized so tat te overead of an adaptive circuit is sufficiently small. Controlling: Based on te information collected byon-cipsensors,anefficientalgoritmmustbe implemented to optimally control te tuning knobs (e.g., bias current, capacitor array, etc.) to maintain te desired circuit beavior. Integration: All on-cip sensors and tuning knobs must be seamlessly integrated wit oter core November/December

3 Design and Test of Millimeter-Wave/Subteraertz Circuits and Systems circuit blocks wit small silicon area and low power consumption, wile quickly and automatically accommodating environmental canges. Among tese tree components, on-cip performance sensing is te most callenging, because many analog performance metrics [e.g., noise factor (NF)] cannot be easily measured by on-cip sensors. To address tis issue, we propose te idea of indirect performance sensing [9] were te performance of interest (PoI) is not directly measured by an on-cip sensor. Instead, it is accurately predicted from a set of oter performance metrics, referred to as te performances of measurement (PoM), wic are igly correlated wit PoI and are easy to measure. In te following, we will discuss te algoritms and metodologies of te proposed indirect performance sensing in detail. On-cip indirect performance sensing Witoutlossofgenerality,wedenoteaPoIasf and te PoM as x ¼½x 1 x 2 x M Š T (3) were M stands for te number of performance metrics belonging to te PoM. Te objective of indirect performance sensing is to build a matematical model f ðxþ to accurately estimate te PoI f from te PoM x. Generating an indirect sensor model f ðxþ typically consists of tree major steps: presilicon feature extraction aims to identify a set of important performance metrics (i.e., te PoM) tat are igly correlated wit te PoI and can be easily measured by on-cip sensors; presilicon model training aims to approximate te indirect sensor model f ðxþ by linear regression based on presilicon simulation data; postsilicon model calibration aims to calibrate te indirect sensor model f ðxþ based on postsilicon measurement data so tat te errors posed by presilicon simulation can be appropriately corrected. To facilitate efficient generation of indirect sensor models, advanced statistical algoritms must be developed to keep te modeling cost affordable. In oter words, since bot presilicon simulation and postsilicon measurement can be expensive, te aforementioned tree steps for indirect sensor modeling must be accomplised wit limited simulation and measurement data. As suc, te overead of indirect performance sensing and, eventually, te overead of adaptive analog circuit can be minimized. Presilicon indirect sensor modeling As previously mentioned, te objective of presilicon modeling is to identify a set of important performance metrics as te PoM x (i.e., feature selection) and ten fit te matematical model f ðxþ (i.e., model training). To acieve tis goal, we propose to adopt te sparse regression (SR) tecnique [10] to seamlessly integrate te feature selection step and te modeling training step into a unified framework. In general, a matematical function f ðxþ can be approximated as te linear combination of a set of basis functions f ðxþ ¼ XK k¼1 k g k ðxþ (4) were fg k ðxþ; k ¼ 1; 2;...; Kg contains te basis functions (e.g., linear and quadratic polynomials), f k ; k ¼ 1; 2;...; Kg contains te model coefficients, and K is te total number of basis functions. To intuitively illustrate te basic idea of SR, we consider te following simple case were te basis functions are linear: f ðxþ ¼ XM m¼1 m x m þ 0 (5) were f m ; m ¼ 1; 2;...; Mg are te linear model coefficients and 0 is te constant term. Since we do not know te PoM x (i.e., te important performance metrics tat sould be measured by on-cip sensors) in advance, our proposed strategy is to take a large number of possible candidates and apply SR to fit te model coefficients f m ; m ¼ 0; 1;...; Mg as in (5), suc tat only a small number of tese coefficients are nonzero and all oter coefficients are zero. Hence, based on te SR results, we can find te set of important performance metrics fx m ; m 6¼ 0g as te features of interest. In addition, te model coefficients associated wit te selected PoM are simultaneously determined during te aforementioned SR procedure. 10

4 Unlike te conventional least squares fitting tat solves an overdetermined linear equation by minimizing te mean squared error, SR formulates a convex optimization problem wit a unique constraint (e.g., based on L1-norm regularization) tat is able to promote sparse model coefficients. Suc a convex optimization can be solved bot efficiently (i.e., wit low computational cost) and robustly (i.e., wit guaranteed global convergence). More details regarding te SR algoritm can be found in [10]. Te aforementioned SR metod can be efficiently applied to presilicon feature selection and model training. However, te device and parasitics models used for presilicon simulation are not perfectly accurate and may differ from te postsilicon measurement results. For tis reason, tere is a strong need to furter calibrate te proposed indirect sensor models based on postsilicon measurement data, as will be discussed in te next section. Postsilicon indirect sensor calibration Te objective of postsilicon sensor calibration is to furter correct te modeling error arising from presilicon simulation inaccuracies and also to accommodate te process sift associated wit manufacturing lines. One straigtforward approac for sensor calibration is to collect a large amount of postsilicon measurement data and ten completely refit te indirect sensor model. Suc a simple approac, owever, can be practically unaffordable, since postsilicon testing is time consuming and, ence, it is overly expensive to collect a large set of postsilicon measurement data. To address tis cost issue, we propose a novel statistical framework, referred to as BMF [11], for efficient postsilicon sensor calibration. BMF relies on an important observation, namely, tat even toug te simulation and/or measurement data collected at multiple stages (e.g., presilicon versus postsilicon) are not exactly identical, tey are expected to be strongly correlated. Hence, it is possible to borrow te data from an early stage (e.g., presilicon) for sensor calibration at a late stage (e.g., postsilicon). In tis context, even a small number of postsilicon measurements can be leveraged effectively to enance model accuracy, allowing te cost of sensor calibration to be substantially reduced. More specifically, our indirect sensor models are initially fitted by using te early-stage (e.g., presilicon) data. Next, a model template is statistically extracted and encoded as our prior knowledge based on te early-stage model. Finally, te model template is furter calibrated by applying Bayesian inference to very few late-stage (e.g., postsilicon) measurements to accurately update tese sensor models. Here, by fusing te early-stage and late-stage sensor models troug Bayesian inference, te amount of required measurement data (ence, te measurement cost) can be substantially reduced. To fully understand te proposed BMF metod, we need to first explain te common caracteristics between te early-stage and late-stage sensor models. To tis end, we represent bot te earlystage model f E ðxþ and te late-stage model f L ðxþ as te linear combinations of K basis functions, similar to (4) f E ðxþ XK k¼1 f L ðxþ XK k¼1 E;k g k ðxþ (6) L;k g k ðxþ (7) were f E;k ; k ¼ 1; 2;...; Kg and f L;k ; k ¼ 1; 2;...; Kg denote te early-stage and late-stage model coefficients, respectively. Since bot f E ðxþ and f L ðxþ model te same PoI of te same circuit, we expect tat te model coefficients E;k and L;k are similar, but not exactly identical. Suc prior knowledge can be statistically encoded as a prior distribution. Next, we apply Bayesian inference to statistically combine te prior distribution and very few late-stage measurements to accurately estimate te late-stage model coefficients f L;k ; k ¼ 1; 2;...; Kg based on te posterior distribution. Suc an approac is referred to as maximum a posteriori (MAP) estimation in te statistics community. Additional matematical details regarding BMF can be found in [11]. In summary, SR and BMF are two core tecniques tat facilitate our proposed on-cip indirect performance sensing for adaptive analog circuits. In te Case Study: An Adaptive Millimeter-Wave LNA section, we will describe a mm-wave circuit example were indirect performance sensing as been successfully applied to enable adaptive circuit operations. November/December

5 Design and Test of Millimeter-Wave/Subteraertz Circuits and Systems Figure 2. Healing and adaptive control loops. (a) ADC control loop. (b) Sensor control loop. (c) Adaptive circuit control loop. System-on-cip arcitecture for adaptive circuits Adaptive SoC arcitecture Te implementation of on-cip adaptive algoritms requires complex SoC design, especially for mm-wave TRx. Figure 2 sows te proposed SoC arcitecture intended to enable circuits to be adaptive. In tis arcitecture, te serial interface and microcontroller data flows are multiplexed suc tat te algoritm can be run eiter outside te cip on a ost or inside te cip on te microcontroller. A microcontroller was cosen to run most of te algoritms, because it offers muc more flexibility (as compared to direct algoritm implementation in ardware) to enance te algoritm once te cip is tested or in te field. Eac circuit is connected troug a data bus tat allows writing and reading registers. Te data bus includes a control sceme tat allows writing to a single circuit or multiple circuits (broadcast mode). For added flexibility, a control circuit can be used to control multiple circuits. Te enablement of series and parallel register writing and series register reading allows te proper syncronization and control of multiple tasks running in parallel. A syntesizer is required to generate te multiple clocks used in te different circuits and te clock used for te microcontroller. Because multiple clock domains coexist inside te SoC, careful task orcestration and syncronization is required. ADC control loop A large number of control loops may be required to enable a complete adaptive TRx. Since most sensor outputs are analog and must be digitized to enable algoritmic control, te first loops tat must be establised at startup are tose for te analog-todigital converters (ADCs). As sown in Figure 2a, te ADC can be, for example, calibrated by applying one or several bandgap voltages to its inputs. Different analog-to-digital conversion modes can be supported by selecting different digital-to-analog converter (DAC) settings, tus enabling ADC range programmability. In operation, it is desirable for te self-ealing control system to periodically ceck te temperature sensor output, using tis result to evaluate temperature drift and ten decide weter a new calibration is required. Sensor control loop Once te self-ealing control system as completed te ADC calibration, it can start to calibrate 12

6 te sensors tat are sensitive to process, supply voltage, and temperature variations. An implementation example is sown in Figure 2b. Since te ADC circuit area is typically muc larger tan te sensor area, it is advantageous to group local sensors and select te sensor tat needs to be read wit an analog multiplexer (Figure 2b). Of course, sensors tat are far away from a given ADC migt require te instantiation of an additional ADC, since te sensitive analog voltage migt be contaminated, for example, by digital or clock circuit noise. Te sensor calibration algoritm can take into account not only te sensor output, but also tat of oter internal sensor nodes (Figure 2b), as well as temperature. Te algoritm integrates all te different inputs and adjusts te DAC setting to adjust and calibrate te sensor. An algoritm metodology (using direct and indirect measurements) similar to te one described in te DesignandTestMetodologyforAdaptiveCircuits section can be used to calibrate te sensor across P; V, andt. Adaptive circuit control loop Once te self-ealing control system as completed te sensor calibrations, it can start to run te adaptive circuit algoritms. As sown in Figure 2c, te analog information coming from j sensors is digitized one by one. Te digital information is used by te adaptive algoritms to set te circuit control bits and settings for te current control DACs. Te DACs can be implemented using many different arcitectures, including capacitor, resistor, or fieldeffect transistor (FET) bank switcing. Te algoritms can take several iterations to converge to te optimum circuit setting. Eac circuit can be set to target certain specifications across P; V, and T using te metodology discussed in te Design and Test Metodology for Adaptive Circuits section. We are also envisioning running adaptive algoritms for several circuits at once, wic could allow furter reduction in power consumption. Since te software algoritm latency is in te order of a microsecond to a millisecond, te fast adaptive algoritm must be implemented in ardware. Terefore, ardware and software adaptive algoritms will coexist on te same SoC. Software and ardware codesign metodology Anoter important aspect of te self-ealing approac is its software and ardware codesign. As sown in Figure 3a, te software is typically developed after te ardware is fabricated and is under test. Tis metodology as two drawbacks: first, tere is no development during te fabrication; and second, it is not possible to coverify te software wit te ardware, wic can lead to some implementation issues tat can only be discovered wen te SoC is tested. Figure 3. (a) Typical SoC design, verification, and integration flow. (b) Proposed verification and software and ardware codesign flow using ig-level beavioral models. November/December

7 Design and Test of Millimeter-Wave/Subteraertz Circuits and Systems In order to efficiently cosimulate te ardware and te software, we ave developed ig-level very ig speed integrated circuit (VHSIC) ardware description language (VHDL) matematical models for te mm-wave, RF, analog, and mixed-signal macros used in our designs. Te advantage of using VHDL is tat continuous analog signals can be applied to te circuits and can be processed by te beavioral models. Tus, analog and digital signals can be computed efficiently by te VHDL simulator. Te oter means of acceleration exploited in our work is tat te software is initially run externally, wit sense data and control signals applied to te mm-wave circuit troug its serial interface. Te software is written in tool command language (TCL), wic is also te language used to drive te VHDL simulations. By using tis metodology (refer to Figure 3b), we can avoid time-consuming, resource-intensive emulation of te microcontroller, instead natively running te TCL code on te simulation computer, resulting in a speedup of several orders of magnitude. Anoter important advantage of using TCL is tat te testing code used to test te ardware can be te same as tat used to verify te cip using te simulator, allowing unification of testing and verification flows. Case study: An adaptive millimeter-wave LNA Performance variability of LNA Te effects of process variations ave become a callenging issue for RF LNA design [5], [6], and are even more significant at mm-wave frequencies [1], [2]. In particular, te gain, noise factor (F ), and matcing of te LNA are susceptible to process variations.figure4aandbsowstedesignscematic and layout of a 60-GHz LNA designed in a 32-nm Figure 4. Te 32-nm SOI tree-stage 60-GHz LNA. (a) Scematic. (b) Pysical design. (c) Simulated and measured S-parameter comparison. (d) Simulated 60-GHz NF versus current DAC code D I at T ¼ 85 C, 25 C, and 25 C. 14

8 silicon on insulator (SOI) process. Te FETs, along wit all te wire parasitics, were extracted from te layout to enable more accurate simulation. Te circuit was simulated using ig-frequency models for te transmission lines, capacitors, and resistors used in te design. In Figure 4c, we sow te LNA initial S-parameter measurement results. Te simulated S-parameters sown in Figure 4c are in agreement wit te measured one, tus validating our models. Figure 4d sows te simulated NF sweeping versus current biasing DAC code D I at different temperatures. D I directly controls I S in Figure 4a. Monte Carlo simulation results sow tat bot gain (wit mean value of db and standard deviation of 2.19 db) and NF (wit mean value of 5.15 db and standard deviation of 0.49 db) present large variability for tis design. Te variation of NF and gain of te LNA will significantly affect te performance of te wole receiver system. In our case, te first stage of te receiver is te LNA, followed by an RF mixer as te second stage and an in pase and pase quadrature (IQ) mixer as te tird stage. According to Friis formula, te total NF of te receiver system F RX is represented as F RX ¼ F LNA þ F RF MIXER 1 G LNA þ F IQ MIXER 1 þ (8) G LNA G RF MIXER were F represents te NF, G represents te gain, and subscripts represent te name of te stage. We can see tat te NF of all stages after te LNA will be attenuated by te gain of LNA, so te NF of te receiver F RX is mostly determined by LNA NF and gain. Terefore, it is essential to overcome te variations in te LNA to acieve low noise for te overall receiver.intispaper,weassumetattegainoflna will be measured by an on-cip peak detector, and we focus on NF self-ealing only. Indirect NF sensing NF is generally difficult and expensive to measure directly on cip. Hence, ere we apply te indirect sensing tecnique, correlating NF wit easy-to-measure PoMs. We collect a set of transistorlevel Monte Carlo simulation data over te joint space of process, temperature T,andbiascurrentI S. After te simulation data are collected, we are able to apply te presilicon indirect sensor modeling procedure described in te Presilicon Indirect Sensor Modeling section. In tis LNA example, tere are multiple possible PoMs (e.g., peak detector output voltage, dc voltages, temperature) tat can be correlated wit NF. We need to mention ere tat te LNA cip in Figure 4 does not include a peak detector at 60 GHz. Tis is because te LNA will be integrated wit a downconversion mixer tat will include a peak detector at te intermediate frequency (IF) wic is easier to design. In tis paper, we assume tat te output signal amplitude is sensed by a virtual peak detector. In simulations, we record te 60-GHz output signal amplitude and use it as one of PoM. By applying te SR algoritm, we are able to find te most important PoMs and select te important ig-order terms associated wit tem. Te final PoM set includes V PD (te output voltage of te peak detector), V N (te drain dc voltage in te biasing stage in Figure 4a), D I (te digital code controlling te bias current I S in tunable current mirror), and T (temperature). Correlation coefficients between NF and V PD, V N, D I,andT are 0.82, 0.81, 0.67, and 0.30, respectively. Here, V PD can be measured by a peak detector, V N canbemeasuredbyanon-cip ADC, and T canbemeasuredbyanon-ciptemperature sensor. D I can be directly known from te digital code. Te indirect sensor model solved from SR is NFðV PD ; D I ; T ; V N Þ ¼ a 1000 V PD þ a 0100 D I þ a 0010 T þ a 2000 VPD 2 þ a 0200DI 2 þ a 0020 T 2 þ a 0030 T 3 þ a 0003 V 3 N þ a 1010V PD T þ a 3000 V 3 PD þ a 0000: (9) Te mean error of tis indirect sensor model is db. Given tat V PD, V N,andT require on-cip measurements, te impact of quantization error is also considered for te proposed indirect sensor. According to te variation range of V PD, V N,andT in simulation data, te sensors dynamic ranges are V for V PD, V for V N,and 20 C 80 C for T. A sweeping analysis for te bits is performed to evaluate te error under different quantization conditions. Final decisions for quantization bits for V PD, V N,andT are5,4,and4bits,respectively.te quantization bits are selected as te minimum bits were not muc accuracy is lost. Wit te November/December

9 Design and Test of Millimeter-Wave/Subteraertz Circuits and Systems Figure 5. Monte Carlo simulation results. (a) and (b) NF and total current istograms after self-ealing. (c) Comparison between self-ealing wit peak detector and fixed-biasing cases. (d) Comparison between self-ealing witout peak-detector and fixed-biasing cases. quantization effect considered, te NF indirect sensor error is db. Self-ealing algoritm and results Using te indirect sensor model, we can predict NF according to on-cip sensor measurements. In tis context, we propose te following self-ealing algoritm. 1) Set bias current of all cips to minimum value. 2) V PD, V N, and T are measured using on-cip sensors. 3) Calculate predicted NF of eac cip using te indirect sensor model and compare te result wit te NF specification. If te NF meets te specification, te algoritm stops. Oterwise, te bias current is increased by a small value, after wic steps 2) and 3) are repeated until te NF specification is met or te maximum DAC control word is reaced. Te algoritm generally tries to find te minimum bias current tat meets te NF specification. Indirect sensor model error must be carefully considered during self-ealing. Due to te NF prediction error, te estimated NF will be different from te actual NF. Terefore, to andle te uncertainty in NF prediction, a guard band is required. Te guard band is te extra margin we leave for NF in selfealing, so tat ig yield can be acieved. Te size of te guard band is determined by statistically modeling indirect sensor error. First, we collect te error data from indirect sensor model fitting. Te error data are ten fitted against a distribution by using kernel density estimation. Te guard band can ten be optimally determined once te error distribution is known. Te calculated guard band is added to te predicted NFs for all cips to guarantee ig yield. To validate te self-ealing algoritm wit guard band at te simulation and design level, 40 cips are randomly generated from transistor-level simulations. After applying te self-ealing procedure and adding guard band, te 40 cips acieve 100% yield wit te NF specification of 5.5 db. Te average total LNA current for all cips is 14.7 ma. Te istograms of NF and total current are sown in Figure 5a and b. We also consider te fixed-biasing cases for comparison purpose. In te fixed-biasing cases, all te cips select te same tuning knob configuration. Te power and yield of a set of fixed biasing cases are compared wit te proposed selfealing metod (wit peak detector) in Figure 5c. Te self-ealing metod is able to acieve 25% power reduction compared to te best fixed biasing case (wit 19.4-mA total current), wile not losing any yield. Te key reason for te proposed selfealing metod acieving better performance is tat it adaptively selects an optimum bias current for eac cip. For te cips wit good NF, te algoritm will try to bias at low current so tat power consumption is low. For te cips wit bad NF, te algoritm tends to bias at a ig current value so tat te cip can meet te NF specification. We also compare te fixed biasing cases wit te self-ealing metod (witout peak detector) in Figure 5d. Te indirect sensor model, quantization, and guard band are formulated similarly as te case wit peak detector. In tis case, te self-ealing metod is able to acieve te same performance as te best fixedbiasing case. In future work, we plan to implement te algoritm on te microcontroller and perform all te mm-wave measurement across P; V, and T. IN THISPAPER, we propose a teoretical framework tat allows te prediction of RF and mm-wave circuit 16

10 performance wit on-cip sensors troug te use of indirect sensing wit BMF instead of troug costly and difficult direct integrated measurement. Because te simpler sensors required by indirect sensing, along wit te circuit actuators, can be efficiently integrated, a large number of adaptive circuit loops can be envisioned, wic will allow transceivers to adapt to process variability and external canges suc tat te energy spent by bit transmitted is minimized. Te adaptation can be performed by algoritms running on an integrated microcontroller, or, alternately, using off-cip compute engines accessing internal sensors and actuators. We proposed a design and test metodology tat allows te verification and integration of te software wit te digital, mixed-signal, RF, and mmwave circuits. Tis metodology also enables significant convergence between te code used for circuit verification and tat use for test. Finally, we described te design example of a 60-GHz LNA tat can be self-ealed using indirect NF sensing and adaptive biasing. Monte Carlo simulations sow tat te LNA average power consumption can be improved by 25% wit adaptive biasing wile acieving te same 100% yield as tat acieved wit te optimum fixed bias. References [1] C. Maxey, G. Creec, S. Raman, and J. Rockway, Mixed-signal SoCs wit in situ self-ealing circuitry, IEEE Design Test Comput., vol. 29, no. 6, pp , Nov./Dec [2] C. Cien, A. Tang, F. Hsiao, and M. F. Cang, Dual-control self-ealing arcitecture for ig-performance radio SoCs, IEEE Design Test Comput., vol. 29, no. 6, pp , Nov./Dec [3]M.Margarit,J.L.Tam,R.Meyer,andM.Deen, A low-noise, low-power VCO wit automatic amplitude control for wireless applications, IEEE J. Solid-State Circuits, vol. 34, no. 6, pp , Jun [4] W. Kalil, B. Bakkaloglu, and S. Kiaei, A self-calibrated on-cip pase-noise measurement circuit wit 75 dbc single-tone sensitivity at 100 khz offset, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp , Dec [5] N. Kupp, H. Huang, Y. Makris, and P. Drineas, Improving analog and RF device yield troug performance calibration, IEEE Design Test Comput., vol. 28, no. 3, pp , May/Jun [6] S. Sen, D. Banerjee, M. Verelst, and A. Catterjee, A power-scalable cannel-adaptive wireless receiver based on built-in ortogonally tunable LNA, IEEE Trans. Circuits Syst., vol. 59, no. 5, pp , May [7]J.-O.Ploucartetal., A23.5GHzPLLwitan adaptively biased VCO in 32 nm SOI-CMOS, IEEE Trans. Circuits Syst., vol. 60, no. 8, pp , Aug [8] B. Sadu et al., A linearized, low-pase-noise VCO-based 25-GHz PLL wit autonomic biasing, IEEE J. Solid-State Circuits, vol. 48, no. 5, pp , May [9] S. Yaldiz et al., Indirect pase noise sensing for self-ealing voltage controlled oscillators, in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2011, DOI: /CICC [10] F. Wang, W. Zang, S. Sun, X. Li, and C. Gu, Bayesian model fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data, in Proc. Design Autom. Conf., Jun. 2013, pp [11] X. Li, Finding deterministic solution from underdetermined equation: Large-scale performance modeling of analog/rf circuits, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.29, no. 11, pp , Nov J.-O. Ploucart is a Researc Staff Member at IBM Researc, Yorktown Heigts, NY, USA, working on communication circuits and tecnologies. Ploucart as a PD in electronics from te University of Paris, Paris, France. He is a senior member of te IEEE. Benjamin Parker is retired. Parker as an MS in pysics from Brown University, Providence, RI, USA. Bodisatwa Sadu is currently a Researc Staff Member at T.J. Watson Researc Center, IBM Researc, Yorktown Heigts, NY, USA. His researc interests include low-noise and wide-tuning range PLLs, circuits for cognitive radios, and millimeter-wave transceiver circuits. Sadu as a PD in electrical engineering from te University of Minnesota, Minneapolis, MN, USA (2012). He is a member of te IEEE. November/December

11 Design and Test of Millimeter-Wave/Subteraertz Circuits and Systems Alberto Valdes-Garcia is currently a Researc Staff Member and Manager of te RF Circuits and Systems Group, IBM Researc, Yorktown Heigts, NY, USA. His present work is on silicon-integrated millimeter-wave systems and carbon electronics. Valdes-Garcia as a PD in electrical engineering from Texas A&M University, College Station, TX, USA (2006). He is a senior member of te IEEE. Daniel Friedman joined IBM Researc, Yorktown Heigts, NY, USA, in He now manages te Communication Circuits and Systems group tere, investigating I/O, millimter-wave communication, and computation acceleration. Friedman as a PD in engineering science from Harvard University, Cambridge, MA, USA (1992). He cairs te IEEE International Solid-State Circuits Conference (ISSCC) wireline subcommittee. He is a member of te IEEE. Fa Wang is currently working toward a PD at te Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburg, PA, USA. Wang as a BS in control teory and information tecnology from Tsingua University, Beijing, Cina (2009). He is a student member of te IEEE. Xin Li is currently an Associate Professor in te Electrical and Computer Engineering Department and te Assistant Director of te Center for Silicon System Implementation, Carnegie Mellon University, Pittsburg, PA, USA. His researc interests include integrated circuit and signal processing. Li as a PD in electrical and computer engineering from Carnegie Mellon University (2005). Miai Sanduleanu is currently an Associate Professor at Masdar Institute of Science and Tecnology, Abu Dabi, United Arab Emirates. He was previously wit T.J. Watson Researc Center, IBM Researc, Yorktown Heigts, NY, USA. His area of researc includes wireless transceiver design for RF/millimter-wave/teraertz communication, and THz electronics. Sanduleanu as a PD from te University of Twente, Enscede, Te Neterlands. Andreea Balteanu is currently working toward a PD at te University of Toronto, Toronto, ON, Canada. Se received te Best Student Paper Award at te 2012 IEEE International Microwave Symposium. Balteanu as a BASc from te University of Waterloo, Waterloo, ON, Canada (2007) and an MASc from te University of Toronto (2010). Direct questions and comments about tis article to J.-O. Ploucart, IBM T. J. Watson Researc Center, Yorktown Heigts, NY USA; ploucar@us.ibm. com. 18