Journal of Engineering Science and Technology Review 7 (1) (2014) Research Article

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1 Jestr Journal of Engineering Science and Tecnology Review 7 (1) (2014) Researc Article JOURNAL OF Engineering Science and Tecnology Review A Parallelized Implementation of Turbo Decoding Based on Networ on Cip Multi-core Processor Caolong ZHANG 1,*, Zeun HU 2 and Jie Cen 1 1 Institute of Microelectronics, Cinese Academy of Sciences, Beijing 10029, Cina 2 Te 709t Researc Institute of Cina Sipbuilding Industry Corporation, Wuan , Cina Received 1 May 2013; Accepted 13 Marc 2014 Abstract Wit te evolution of wireless communication systems, it is increasingly difficult for Application Specific Integrated Circuit (ASIC) solutions to meet te daily canging requirements. A networ on cip (NOC) multi-core processor based on message-passing programming model is designed to implement te LTE-A turbo decoder in a parallel mode using pure Software Defined Radio (SDR) approac. Te NOC is well balanced between te ardware and software design wit a ig degree of programmability and re-configurability. According to te features of te NOC multi-core processor, te implementation of turbo decoder is optimized to reduce te computational complexity and to increase te parallelization. Several aspects of turbo decoder are investigated in software radio approac rater tan ardware. Compared wit te results of te software simulation and te Field Programmable Gate Array (FPGA) demonstration, te NOC multicore processor is flexible to realize te proposed turbo decoding algoritm. In addition, our solution as comparable performance wit oter publised ones. Keywords: Networ on Cip, Turbo Decoding, Low Complexity, Parallel Computation 1. Introduction Since Berrou publised te seminal paper about turbo coder[1], te properties of turbo code as been studied torougly in academy and industry for over twenty years. Recently, te researc as been focusing on ow to reduce te complexity and latency resulted from MAP decoding (also nown as te BCJR algoritm). In order to relax te ig demanding on memory during decoding, sliding window algoritm is invented to separate te long data bloc into sort sub-blocs[2]. By adopting appropriate early stopping criteria[3], te number of iteration is reduced, so is te computational complexity. However, wit te development of communications systems, te baseband solutions are canged rapidly. Besides te computational complexity, being programmable and configurable is also very important for wireless baseband processing. Because of lac of flexibility, long development period and ig cost of ASIC solutions, Software Defined Radio (SDR) arises to be a muc better coice. Networ on Cip, a new arcitecture for multi-core processor, is well balanced between ardware and software degign. Due to SDR approac, it is easy to map various signal processing algoritms onto NOC. In tis paper, a NOC multi-core processor is designed. Being different wit[4], by using a message-passing programming model, te proposed NOC processor as low complexity in ardware and ig flexibility of software wic gives te programmer more freedom to realize te parallelized turbo decoding algoritm. Te software radio approac maes te system easy to transplant and update. In addition, a parallel turbo decoder solution based on SDR is proposed and mapped onto te NOC. Several aspects of te turbo decoder suc as te max* operators used in te log- MAP algoritm and early stopping criteria are reinvestigated to reduced te computational complexity. Te oter sections of tis paper are organized as below: section 2 describes te turbo decoding algoritm and several modifications compared wit[5]; te ardware arcitecture and software communication protocol of te proposed NOC processor are explained in section 3 and ow te proposed turbo algoritm is mapped on to NOC is also given in tis section; section 4 provides te simulation results coming from bot te software simulation and te NOC on FPGA board; at last, section 5 contains te conclusion. 2. Turbo Coder and Decoder 2.1 Turbo decoder In tis paper, as a concrete example, te turbo coder used in 3GPP LTE-A is adopted. As illustrated in Fig 1, te LTE-A turbo encoder is composed of two parallel recursive systematic convolutional (RSC) encoders wit constraint lengt 4. * address: zangcaolong@ime.ac.cn ISSN: Kavala Institute of Tecnology. All rigts reserved.

2 Caolong ZHANG, Zeun HU and Jie Cen/Journal of Engineering Science and Tecnology Review 7 (1) (2014) Fig. 1. Turbo encoder adopted by 3GPP LTE-A ' In Fig. 1, u is te information bits, u te interleaved 1 2 version ofu, x te system information bit and 1 up, u p te parity cec coded bits coming from te two RSC coders. Te lengt of interleaver is K, were 40 K A contention-free quadratic polynomial permutation (QPP) interleavers wit bloc size K is defined as Π i = f x+ f x K (1) 2 () ( 1 2 ) mod Te index can be calculated iteratively. 2.2 Turbo Decoder Te decoding algoritm is based on log-map algoritm and te algoritm is implemented using single-precision floating-point aritmetic on te NOC. Te sliding-window algoritm described in[2] is improved in order to reduce te overead communication between te micro-processors on te NOC. Te arcitecture of te log-map decoder is sown as Fig 2: R, R stand for te pats corresponding input 1 and to, respectively. ' Ps (, sy, ) represents te joint probability of receiving te Were in te trellis grap from time 1 ' s at time 1 sequence y and being in state and in state s at time. α, β are called te forward and bacward variables. Actually, for te memory-less cannel α, β, γ can be calculated iteratively. Te main difference between te variant of MAP algoritm is te so-called max* operator[5] wic use x y te Jacobi algoritm to calculate ln( e + e ), namely: max*(, ) ln( x y xy= e+ e) (4) Currently,Tere are four max* operators used: 1) Log-MAP operator x y max*( xy, ) max( xy, ) ln(1 e ) 2) Max-MAP operator max*( xy, ) max( xy, ) = + + (5) = (6) 3) Constant-log-MAP operator 0 if x y T max*( xy, ) = max( xy, ) + C if x y T (7) 4) Linear-log-MAP operator 0 if x y t max*( xy, ) = max( xy, ) + ( x y T) if x y T (8) Fig. 2. Arcitecture of te Proposed turbo decoder In Fig 2, D1 and D2 stand for te two soft-input softoutput decoders. Te input to te decoder is supposed to be in log-lieliood ratio (LLR) format wic taes te soft information about te cannel gain and te noise variance into consideration. Te LLR is defined as equation (2): Pu ( =+ 1 y) Lu ( y) = ln Pu ( = 1 y ) Wit te assistance of trellis grap, equation (2) can be written as: Ps (, s, y) α ( s) γ ( s, s) β ( s) (3) Lu ( y) = ln = ln Ps ( ', s, ) ( s) ( s, s) ( s) ' ' ' 1 R1 R1 ' ' y α 1 γ β R0 R0 (2) In te fourt max* operator, te linear-log-map operator, it s sown in Ref. [8] tat te optimal values for and T are = and T = , respectively. Different from te linear-log-map, first introduced in[8], in tis paper, troug quadratic curve fitting, we get a quadratic polynomial approximation to te max* operator. Te quadratic max* is sown as: max*( xy, ) = max( xy, ) + ( x y ) + ( x y ) + (9) Wit 95% confidence bounds, 2 [ , ], 1 [ , ], 0 [0.6503,0.6531] Te max* operators are sown in Fig 3. 53

3 Caolong ZHANG, Zeun HU and Jie Cen/Journal of Engineering Science and Tecnology Review 7 (1) (2014) In Fig 4, controller1 is te SRAM controller wile controller2 is te router controller, namely te networ interface. Te processing unit (PU) on te NOC is a smallscale 32-bit RISC processor wic as 3-level pipeline arcitecture. Te data and command are accessed troug AHB bus from te private 32 KB SRAM. Inter-processor communication is conducted via te worm-ole switc routers and networ interfaces using two virtual cannels. In te wormole switcing networ, te data pacet is passed from one PU to anoter in te format of "flit" containing te routing information and data wose format will be sown later. Te circuit of te worm-ole router wit two virtual cannels is sown as Fig 5. Fig. 3. different max* operators used in log-map, linear-log-map, constant-log-map and te quadratic-log-map. As sown in Fig 3, te quadratic-log-map fits te log- MAP most effectively. In section 4, te BER-SNR curves resulted from different max* operators are also sown tat algoritm using te quadratic-log-map operator as te best performance. Anoter tecnique used in tis paper to reduce te computational complexity is te early stopping criteria. In general, as te number of iteration increases, te performance of te decoder will not be improved linearly wic means too many iterations only bring ig complexity and ig latency. To combat tis problem, early stopping criteria is adopted during te decoding process[3]. Basically, tere are two inds of early stopping criteria: 1) te arddecision principle, wic compares two output of successive iteration of SISO decoder. If te outputs are equal, te iteration is stopped. 2) te soft-decision principle, wic compares te LLR of te SISO wit a given tresold. In tis paper, te later principle is adopted, and te impact of different tresold on te BER performance is simulated and analyzed in section 4. Of course, a maximum number of iteration is set in case tat te iteration will not stop. 3. Mapping Turbo decoder to NOC processor In tis section, te arcitecture of te NOC multi-core processor is described briefly and te parallel turbo decoding is explained and mapped onto te NOC. Fig. 5. circuit bloc grap of te wormole switc router Te capacity of te virtual cannel list is set to 8 during te routing processing. Te adjacent routers utilize te measure of credit to control te data flow as sow in Fig 5. In order to avoid deadloc during routing process, XY-algoritm is adopted[6]. Te XY-algoritm is not only easy to implement but also effective to guarantee te order and consistence of te data pacets. 3.2 Te Software Protocol of te NOC Multi-core Processor Te ardware provides te foundation in switcing te data pacet wile te software tells te ardware wat and were to send. To acieve tis goal, inter-processor software communication protocol is to be made. As mentioned before, te data is transmitted between te PUs in te format of "flit" wic contains te routing information and data. One data pacet is composed of flits. Te format of a data pacet is sown as Fig 6(a). 3.1 Te Hardware of te NOC Multi-core Processor Based on te message-passing programming model, witin a 4 4 2D mes networ on cip, te multi-core processor is designed wit 16 small RISC micro-processors[6]. Te arcitecture of te NOC and eac micro-processor is sown as Fig 4. Fig. 4. Te arcitecture of NOC and eac micro-processor (a) 54

4 Caolong ZHANG, Zeun HU and Jie Cen/Journal of Engineering Science and Tecnology Review 7 (1) (2014) stages. However, instead of using overlapping, te forward and bacward variables wic were computed in te previous iteration of te adjacent sub-blocs are utilized to provide appropriate boundary distributions for eac subbloc MAP decoder. All sub-bloc MAP decoders perform te computation simultaneously and ence, te proposed algoritm (as sown in Fig. 7) reduces te decoding computation time exactly by a factor of K. (b) Fig. 6. te format of it and command field in te data pacet Te first flit of te data pacet is composed of five fields: te first and second fields are te coordinate of te destination PU to wic te pacet are sent wile te tird and te fourt are te coordinate of te source PU from wic te pacet are sent; te last fields is a 16-bit command wose format is sown as Fig 6(b). Te second flit of te data pacet is te starting address (in C programming language, te pointer of te data) of SRAM to store te data. Te tird flit may be eiter te data part or te address for te acnowledgement according to te parameter set in te programming API. Te following flits contain te data. Basically, te software protocol provides tree important APIs for te programmer to conduct te data transmitting from one PU to anoter. 1) void get_curr_pos(int *x, int *y); used to get te coordinate of te current PU, and stored te result in x and y. 2) int send_message(long msg[], int lengt, int dest_x, int dest_y, unsigned long dest_address,unsigned long cmd, int vcid, int blocing); used to send messages between te PU on te cip. msg and lengt is te starting address and lengt of te data to be sent, respectively. (dest_x,dest_y) is te coordinate of te destination PU. cmd is te command wic will be executed on te data and can be defined by te programmer. vcid is used to indict wic virtual cannel is to be used to send te data and blocing tell te destination PU to send bac an acnowledgement message if set to be 1. 3) void barrier(volatile struct sync s* sync_p, unsigned int proc_mas, int proc_num, int major_x, int major_y); used to syncronize te data stored in different PUs. sync_p is te syncronizing struct. proc_mas: a two bytes value, mass te processors engaged in syncronisation. proc_num: te number of processors engaged in syncronization, equal to te number of 1s in proc_mas. (major_x, major_y): te coordinate of te processor responsible for te syncronization. 3.2 Te Mapping Procedure Te ey step of mapping te turbo decoder to te NOC is to separate te data bloc y into sub-blocs witout interaction wit eac oter so as to reduce te intercommunication between te PUs. Te received symbols in y is separated witout overlapping by improving algoritm used in[2][7]. A received y of lengt L is divided into K sub-blocs of lengt M = L/ K trellis Fig. 7. Parallel turbo decoding In Fig. 7, eac SISO decoder is implemented on one PU, and all te SISO can be executed in a parallelized and pipelined way. At first, te received data for eac RSC codes are separated into several continuous non-overlapping subblocs (also nown as windows). Eac sub-bloc is decoded separately using te quadratic-log-map metod. Te initial values for α and β variables come from previous iteration of adjacent windows. All te sub-blocs are decoded in te parallel mode at te same time, during te next iteration te initial values for all te sub-blocs are ready to be read. As can be seen, no extra procedure needed for te initialization of state probabilities at eac iteration. Te lengt of te subblocs is an important factor tat will be analyzed in section 4. Te decoding timing diagram of te parallel sub-bloc processors (also nown as te SISOs) on te NOC is sown as figure 8(a), and its vector version is sown as 8(b). Te symbols tat processed at te same time are written as a vector. Te lengt of te vector is sown is M. Te elements of eac vector coming from different sub-bloc processors. (a) 55

5 Caolong ZHANG, Zeun HU and Jie Cen/Journal of Engineering Science and Tecnology Review 7 (1) (2014) (b) Fig. 8. Te timing diagram of te decoder running on te NOC multicore processor.(b) is te vector version of (a). Te proposed structure is inspired by te messagepassing algoritm wic can be illustrated by graps. In tis paper, te graps are divided into several sub-graps and sceduled for parallel decoding. Tis partition sceme is useful to parallelize te decoding of on constituent code. Te grap of te turbo decoder and its partitioned version are sown in Fig. 9. Fig. 11. Map te SISO onto te NOC multi-core processor. Eac PU is executed as a SISO decoder. 4 Simulation Results 4.2 Frequency and area of te NOC To evaluate te frequency and area of te NOC, Te PUs and te router of te multi-core processor are syntesized using te low leaage low tresold voltage 65nm library of Semiconductor Manufacturing International Corporation (SMIC). Te frequency and area of te single PU and te router are sown as table 1. Fig. 9. Te grap of turbo decoder and its partitioned version Te optimum algoritm is te log-map metod. Here we use te quadratic-log-map version wic is analyzed in section 2 and will be simulated in section 4. Te processing of te sub-blocs in two constituent codes can be executed in parallel mode. However, tans to te QPP interleaver[7] adopted in LTE-A standard, in parallel turbo code, wen te two RSCs are te same encoder(wic is satisfied in tis paper), te SISO blocs for all constituent codes can be sared. Eventually, te number of processors used to implement turbo decoding can be only alf of te metod sown in Fig. 7. Te new arcitecture of te parallel turbo decoder is sown as Fig. 10. Fig. 10. New parallel turbo decoder arcitecture. All te SISOs illustrated in Fig. 7 and Fig. 10 are mapped onto te NOC as depicted in Fig. 11. Table 1: Te Syntesis Results of PU and Router PU Router cloc 200MHz 400MHz combinational µm µm 2 circuit sequential circuit µm µm 2 SRAM µm 2 total area µm µm 2 gate equivalent From table 1, we can see tat te area of te router accounts for about 1/5 of te single PU and about 75% of te router is sequential logic circuit. Te router can wor at frequency double times as tat of te PU wic means wen te bandwidt and latency can not satisfy te applications, we could separate te cloc of te PU and te router to improve te performance. 4.3 Simulation of Turbo Decoder on te NOC Te NOC processor is verified on an Altera EPS180 evaluation FPGA board and te BER-SNR( Bit Error Rate- Signal to Noise Ratio) curve(under AWGN cannel, te lengt of interleaver is 1024) is drawn as Fig. 12. wic is te same as te simulation results coming from Matlab simulation on PC and sows tat te parallel turbo decoding algoritm can wor correctly on te NOC multi-core processor. 56

6 Caolong ZHANG, Zeun HU and Jie Cen/Journal of Engineering Science and Tecnology Review 7 (1) (2014) For eac case, wen BER= 10, te Eb / N0 is sown in Table 2. Table 2: Eb / N0 Required wen BER is 10 max-logmap constantlog-map linearlog-map quadraticlog-map log-map Fig. 12. BER-SNR curve(under AWGN cannel, wit interleaver lengt 1024) 5 AWGN K=512 K= dB 0.82dB Rayleig Fading K=512 K= dB 2.09dB 1.28dB 0.45dB 2.52dB 1.59dB 1.22dB 0.44dB 2.49dB 1.57dB 1.16dB 0.41dB 2.45dB 1.55dB 1.12dB 0.38dB 2.41dB 1.53dB From Fig. 13 and Fig. 14, te max-log-map as te worst performance requiring at least 0.39dB iger (K=512, AWGN) tan te log-map. Except te max-log-map, all oter tree algoritms (constant-log-map, linear-log-map and te quadratic-log-map) are close to te log-map. In particular, Te quadratic-log-map boasts te narrowest gap wit te log-map(only 0.02dB wen K=4096, Rayleig fading). If te total number of data bloc used in te simulation is increased, te error floor would be reaced[15] wic is obvious in Fig. 13 wen K=512 under AWGN cannel. In te error floor, te five curves will converge togeter. Hence, te algoritm may ave a significant impact at low SNR regime and becomes insignificant at ig SNR regime. Te error-floor penomenon means tat in a software radio implementation, we can coose te algoritm adaptively according to te SNR to reduce te computational complexity. 4.4 Performance of Different Max* Operators Te BER-SNR curves resulted from different max* operators mentioned in section 2 is drawn in Fig 13 and Fig 14. Te data bloc lengt is 512 in Fig 10 wile in Fig. 14 te data bloc lengt is In Fig. 13 and Fig. 14, te blue lines are te BER-SNR curves under AWGN cannel wile te red lines are te BER-SNR curves under Rayleig fading cannel. 4.5 Early Stopping Criteria Te results from te previous section were generated under te condition tat te decoder stopped te iteration wen it converged, namely all te errors in te data blocs were corrected. During te simulation, te transmitted data blocs are nown at te receiver. However, te decoder does not now te data, and tus a criteria is needed to stop te iteration. In practice, te BER performance will not be improved endlessly by increasing te number of iteration, so utilize an early stopping criterion will generate a muc iger trougput in a software radio implementation[8]. Tere are many early stopping criteria publised[8]. Tey are proposed based on te cross entropy between iterations or on te sign-difference ratio. In tis paper, a stopping criteria based on te log-lieliood ratio is employed. Te decoder will stop once te LLRs are greater Fig. 13. te BER-SNR curves wit different max* operators under AWGN cannel(te blue curves) and Rayleig fading cannel(te red ones), wit data bloc lengt equal to 512. tan a tresold Δ,namely te decoder stops wen Equation (10) is satisfied. min{ Δ2 } > Δ (10) 1 K Obviously, te stopping tresold influence on te performance. If Fig. 14. te BER-SNR curves wit different max* operators under AWGN cannel(te blue curves) and Rayleig fading cannel(te red ones), wit data bloc lengt equal to Δ as Δ is a significant set to be a small number, te decoder will not operate enoug iterations. If, 57

7 Caolong ZHANG, Zeun HU and Jie Cen/Journal of Engineering Science and Tecnology Review 7 (1) (2014) on te contrast, Δ is large, ten te decoder will run in vain and te trougput will decrease. BER-SNR curves wit different Δ are drawn in Fig. 15. As sown in Fig. 15, Δ = 1and Δ = 6 are too small and te BER performance suffers under tese two conditions. Wen Δ = 10,te BER-SNR curve is almost overlapped wit tat of perfect decoding. Interestingly, te BER wit Δ = 10 is sometimes lower tan tat of ideal stopping. Actually, te output bit sequence of a turbo decoder fluctuates from one iteration to next at times. Wen te received symbol sequenced is corrupted by te cannel seriously, it is impossible for te turbo decoder to correct some bits. However, if te LLR are ig, te early-stopping rule will alt te decoder even te BER is not zero. Hence, te stopping criteria can sometimes lower te BER. Table 3(part 1): Implementations of Turbo Coder Based on Various NOC Arcitecture.(All data as been converted to te 65nm CMOS tecnology), Part 1: results about te NOC Processor. NOC Arcitecture Cloc (MHz) Area (mm 2 ) Troug put (Mbps) Butterfly[10] Benes[6][10] Toroidal[10] Kautz[10] Tis paper Trougput to area ratio Table 3(part 2): Implementations of Turbo Coder Based on Various NOC Arcitecture.(All data as been converted to te 65nm CMOS tecnology), Part 2: results about te Routers Router Arcitecture Cloc (MHz) Area (mm 2 ) Trougput (Mbps) Trougput to area ratio [11] [12] Tis paper Table 3(part 3): Implementations of Turbo Coder Based on Various NOC Arcitecture.(All data as been converted to te 65nm CMOS tecnology), Part 3: results about te decoders Decoder Arcitecture Cloc (MHz) Area (mm 2 ) Trougput (Mbps) NOC overead [13] % [14] % [15] % tis paper % Fig. 15. BER-SNR curve wit quadratic-log-map decoding in AWGN wit different tresold Δ (K=512) As can be seen from part 1 of table 3, even we use a SDR approac to implement te turbo encoder, te area and trougput is also comparable wit te ones listed in Table 3. Te message-passing programming model exploits te NOC effectively. Compared wit oter arcitecture[10] suc as Butterfly, Benes, Toroidal and Kautz, te ardware and software proposed in tis paper outperforms tem in te aspect of degree of programmability. From part 2 of table 3, te router arcitecture designed in tis paper as te igest trougput and trougput to area ratio[11][12]. Part 3 of table 3 tells us tat even te SISO proposed in tis paper as smaller trougput compared wit[13][14][15], we also ave smaller overead. 4.6 Trougput and Circuit Complexity Several turbo decoder implementations based on NOC ave been publised. However, because different degree of flexibility in te computation to be supported always comes at a relevant cost, bot in terms of occupied area and acievable trougput, comparison between tem tends to be difficult. In Table 3, some multi-core processor based arcitectures are reported. To conduct a fair comparison, area and trougput of different parts in te NOC are given in table 3. All data ave been converted to a 65 nm CMOS tecnology. To sum up, te main purpose of table 3 are:1) compare NOC based solutions proposed in tis paper wit oter arcitectures used in parallel turbo decoders. From tis point, comparisons are conducted on te area and trougput. 2) to evaluate te flexibility cost of te NOC arcitecture. From tis point, direct area comparison maes no sense. However, we can get te overead rate associated wit various NOC arcitectures. 5 Conclusions In tis paper, a parallel turbo decoding algoritm is implemented in te pure software radio approac on a NOC multi-core processor. Te NOC multi-core processor is evaluated correctly using FPGA. As an example, te Turbo encoder defined in LTE-A is adopted. During te parallel implementation, te way ow to separate te data bloc in to sub-blocs wit proper lengt is given. Te BER-SNR performance of decoder wit different interleaver lengt is simulated in bot serial and parallel style. It is sown tat tere is little performance degradation resulted from te parallel decoding algoritm implemented on NOC multi-core processor. Compared wit oter implementations, our solution can finis te turbo decoder wit ig parallel degree and low overead complexity. Te BER performance is also comparable wit te publised NOC arcitectures. 58

8 Caolong ZHANG, Zeun HU and Jie Cen/Journal of Engineering Science and Tecnology Review 7 (1) (2014) Acnowledgements Tis wor was financially supported by te National Natural Science Foundation of Cina (No , No and No ). References 1. C. Berrou, A. Glavieux, and P. Titimajsima, Near Sannon limit error-correcting coding and decoding: Turbo-codes. 1, presented at te Tecnical Program, Conference Record, IEEE International Conference on Communications, ICC 93 Geneva, 1993(2), pp H. Lim, Y. Kim, and K. Ceun, An efficient sliding window algoritm using adaptive-lengt guard window for turbo decoders, Journal of Communications and Networs, 14(2), 2012, pp P. Reddy, F. Clermidy, A. Bagdadi, and M. Jezequel, A low complexity stopping criterion for reducing power consumption in turbo decoders, presented at te Design, Automation Test in in Europe Conference & Exibition (DATE), 2011, pp C. Condo, M. Martina, and G. Masera, A Networ-on-Cip-based turbo/ldpc decoder arcitecture, presented at te Design, Automation Test in Europe Conference Exibition (DATE), 2012, pp M. C. Valenti and J. Sun, Te UMTS turbo code and an efficient decoder implementation suitable for software defined radios, International Journal of Wireless Information Networs, 2001(8), pp HU Zeun and CHEN Jie, Design of a Message-passing Multicore System, Journal of Hunan University(Natural Sciences), 40(8) Aug. 2013, pp S. Yoon and Y. Bar-Ness, A parallel MAP algoritm for low latency turbo decoding, IEEE Communications Letters, 6(7),2002, pp A. Taffin, Generalised stopping criterion for iterative decoders, Electronics Letters, 39(13),2003, pp M. J. Tul, F. Gilbert, and N. Wen, Concurrent interleaving arcitectures for ig-trougput cannel coding, presented at te 2003 IEEE International Conference on Acoustics, Speec, and Signal Processing, Proceedings. (ICASSP 03), 2003(2), pp M. Martina, G. Masera, H. Moussa, and A. Bagdadi, On cip interconnects for multiprocessor turbo decoding arcitectures, Microprocessors and Microsystems, 35(2), 2011 pp F. Gilbert, M. J. Tul, and N. Wen, Communication centric arcitectures for turbo-decoding on embedded multiprocessors, presented at te Design, Automation and Test in Europe Conference and Exibition, 2003, pp I. Amed and C. Vitanage, Dynamic reconfiguration approac for ig speed turbo decoding using circular rings, Proceedings of te 19t ACM Great Laes symposium on VLSI. ACM, 2009, pp M. May, T. Ilnseer, N. Wen, and W. Raab, A 150Mbit/s 3GPP LTE Turbo code decoder, presented at te Design, Automation Test in Europe Conference Exibition (DATE), 2010, pp J.-H. Kim and I.-C. Par, A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE, presented at te IEEE Custom Integrated Circuits Conference, CICC 09, 2009, pp P. Urard, L. Paumier, M. Viollet, E. Lantreibecq, H. Micel, S. Muroor, B. Coates, and B. Gupta, A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder, presented at te Solid-State Circuits Conference, Digest of Tecnical Papers. ISSCC IEEE International, 2004(1), pp