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1 doi: info:doi/0.09/cpe

2 New Measurement Base De-embedded Load Model for Power Delivery Network Design Motochika Okano,2, Koji Watanabe 3, Masamichi Naitoh, and chiro Omura Kyushu nstitute of Technology, Japan 2 Toshiba Corporation, Japan 3 Toshiba Digital Media Engineering Corporation, Japan Abstract-- load model including on-chip wiring and package interconnection has been required for printed circuit board (PCB) design of digital products according to the improvement in the speed of operation in recent years. Especially, accurate power delivery network (PDN) information inside is indispensable for PCB design according to requirement of low-impedance and the broadband (from DC to GHz) from the inside of to DC-DC converter. While the detailed impedance information inside s is not disclosed to PCB board designers with the complicated back-end and front-end production design for chip and package. This paper aims to establish new methodology to extract load model with combination of measurement and simulation. The method is simple yet powerful for high-end board design. Fig.. PDN from DC-DC converter to the inside of. ndex Terms-- Load Model, De-embedded, Power delivery network, Target impedance. NTRODUCTON Severe voltage margin for the power supply has been required according to the decrease of supply voltage for high performance. n order to supply required power to the under GHz operation, it is necessary to precisely design the power delivery network (PDN) from DC-DC converter to the digital circuit on chip including wiring on the chip, in the package, and other interconnections as shown in Fig.. Specially, mω level low-impedance characteristics along entire PDN is required in frequency range up to tens of GHz. This impedance is called Target impedance (Z t ). Power supply voltage, Current consumption, and Z t of high-end in recent years are shown in Fig. 2. Z t is calculated by (). Z t V 0% s () c Where V s is the Power supply voltage and c is the Current consumption. Current consumption c has the frequency dependence, so that Z t also has the frequency dependence as shown in (2). Z t V 0% ( f ) s (2) ( f ) c Power supply voltage[v] Target mpedance[mω] Power supply voltage Current consumption Target mpedance Year Fig.2 Trend of high-end Power supply voltage (V s), Current consumption ( c), and Target impedance (Z t). Current waveform (Time domain) of and its frequency dependence (Frequency domain) by Fourier transform are illustrated in Fig. 3. Frequency domain target impedance Z t can be directly obtained from Fig. 3 (b) as shown in fig. 4. The target impedance Z t is defined as the lower side envelope of the impedance curve obtained. As indicated in Fig. 4, although the frequency basis impedance increases as frequency, Z t is required to maintain relatively low level even in high frequency range. Since the load models are not disclosed from vendors to board designers, the amount of capacitors has been assembled on the PCB, based on designer s experience, to maintain low impedance up to the high frequency and no practical method exists to ensure the design validity Current consumption[a]

3 Current consumption[a] Current consumption[a] Target impedance[ω] E Time[ns] (a) Time domain 00k M 0M 00M G (b) Frequency domain Fig.3. Example of Current consumption waveform Target impedance line 00k M 0M 00M G Fig.4. Example of Target impedance. n order to realize PDN for required target low impedance and frequency, with minimum number of capacitors, it is necessary to design entire network including inside package and on-chip wiring. The impedance information is not disclosed from the vendor, thus extraction method become important. Although there have been some papers on extraction method for impedance inside [-3], the low accuracy and the complication has been the problem. This paper aims to introduce novel method to extract impedance inside package by the combination of measurement and simulation. The method is simple and accurate without special measurement tools. The method will contribute efficient design for power delivery on PCB.. NECESSTY OF LOAD MODEL The PDN impedance with and without load model are shown in Fig. 5. The PDN impedance curves ( blue and aqua colored lines in Fig. 5) are calculated with the exact load model specially calculated from the chip and the package design detail in Toshiba Corp. for the particular. The detailed PKG design data used for the exact load mode is shown in Fig. 6. The model includes the effect of vias and bonding wires inside package. (The data and model is not provided for users). The blue line is the impedance at chip indicated by Point B in Fig., and the aqua line is the impedance of at package BGA indicated by Point A in Fig.. t should be noted that detailed package wiring data is required to obtain the impedance at chip shown by blue line in Fig. 5, thus the impedance at Point A is the practical index for the board design without detailed package and wiring information. Without load model, the calculated PDN impedance is out of the target impedance at high frequency range as shown in Black line. Therefore, the number of required capacitors is always over estimated by the board designer, resulting higher board cost and larger board size. Further, mutual correlation effects, such as anti-resonance effect appeared at 20 MHz in Fig. 5 in blue and aqua line, are not considered without load model. The load model is important for following three points according to above discussion. (a) Provide model to board designer to minimize on-board capacitors (b) Ensure the board design validity to the target impedance of the PDN (c) Co-design of PCB board package in terms of PDN quality As described, most of the vendors do not provide the load model of their products nor detailed package and wiring information. Therefor the accurate extraction method for the load model is indispensable. n the next section, the new experiment simulation combined load model extraction method is proposed. The load model is extracted from the difference between PDN impedances obtained by board level measurement with on the board and by the board level simulation without. This technique is the very powerful to minimize the size and cost in terms of PDN design, even if the model is not provided from the vendor.

4 Power Delivery Network mpedance [Ω] Simulation Result Point A(fig.) w/o model Point A(fig.) w/ model Point B(fig.) w/ model Target impedance Zt anti-resonance k 0k 00k M 0M 00M G. NEW EXTRACTON METHOD PCB in which was mounted is prepared, and the Power-GND impedance is measured. Moreover, the Power-GND impedance is simulated in the state where all parts included are not mounted, using PCB design data. The PDN information inside is extracted by taking these both difference. The image is shown in Fig. 7. Fig. 5. PDN mpedance w/ and w/o. load model is precisely calculated from design data. Fig. 7. Load Model extraction concept. A. Proposed Method The relation of input and output can be realized by (3) (4) and (5), if F parameter [F PCB ] is defined as shown in Fig. 8. [F PCB ] is converted from S parameter by (6) even in high frequency. This S parameter [S PCB ] is the impedance of the PCB without, and it can calculate it in analysis from PCB design data. Z N is the Power-GND impedance. S of S parameter between Power and GND of input side is measured using PCB with by Shunt-Thru method. n Shunt-Thru method, the transmission characteristic (S ) comes to hand as S 2. Z N can be transformed from S by (7). (a) PCB design data N * Z N FPCB FPCB 2 * Z (3) N FPCB2 FPCB N N Z F F * PCB FPCB 2 N PCB2 F PCB Z (4) (b) Package design data f N * Z a, b then N a Z (5) b F F PCB PCB2 2 S 2 F F PCB2 PCB ( + S ( S )( S )( S Z ref ) + S2S ) S S [( + S )( + S ) S S ] ( S )( + S 2 2 ) + S S 2 Z 2 (6) ref (c) Wire Bonding data Fig. 6. PCB and Package design data mounted inside Toshiba, which is not disclosed for users. 50 S (7) 2 ( S ) Z N

5 Port near Power supply is mounted. Fig. 8. Load model extraction method. Other parts are not mounted. B. Work Flow to extract load impedance These workflow are indicated in Fig9. Board S-parameter measurement w/ Power-GND impedance S is measured using the PCB with. Shunt-Thru method E836C@Agilent *The transmission characteristic (S) comes to hand as S2 of Shunt-Thru method. Fig. 0. PCB mounted only for measurement. S parameter(s 2 ) can be measured by the Shunt-Thru method. Z N calculated from this S 2 of [S Measure ] is shown in Fig. -2. (S 2 of the Shunt-Thru means the transmission characteristic (S )). S is changed into Z N by (7). S Z N Board S-parameter simulation w/o Power-GND impedance [S PCB ] is simulated using the PCB design data w/o. [S PCB ] is changed into [F PCB ], and [F PCB] - by (6). [S PCB ] [F PCB ] [F PCB ] - Z N 0 0. Fig.. Equivalent circuit of Z N Z N Z can be calculated by (4) and (5). Fig. 9. Work flow for load model with combination of simulation and measurement. 0M 00M Fig. 2. Measurement result Z N G V. RESULTS AND DSCUSSON A. Calculation of Z N The PCB mounted is shown in Fig. 0. Only is mounted in this substrate. The measurement point is Port near DC-DC converter. Measuring instruments is the network/impedance analyzer (product E836C made by Agilent). The frequency range is 0[MHz]- [GHz]. B. Calculation of [F PCB ] [S PCB ] was calculated in the Power-GND impedance simulation using the PCB design data which does not mount any parts included. The simulator is used PowerS(Cadence) Ver0. (Fig. 3). PCB is 4-layer through-hole. The layer structure is shown in TABLE. Port is the same as the measurement point, and Port2 is set to the power and ground pads of as far as possible from Port as shown in Fig. 4.

6 0 Z PCB Z PCB 0. 0M 00M G Fig. 3. Simulation model of PCB (PowerS) Fig. 6. Simulation result Z PCB TABLE THE LAYER STRUCTURE OF THE PCB L S/V/G Material Thickness Conductivity Dielectric Loss [mm] [S/m] Constant Tan Solder Resist S Copper E+07 +Plating P.P G Copper E+07 Core V Copper E+07 P.P S Copper E+07 +Plating Solder Resist C. Calculation of Z The load impedance (Z ) is calculated using Z N of measurement and [F PCB ] - of simulation by (4) and (5). This extracted result is shown in Fig Fig. 7. Equivalent circuit of Z Port All parts are NOT mounted. Port2: Power and GND (Power and GND are groupings, Z cpu 0 De-embedded Result by this method Z 0. Fig. 4. Simulation Ports setting Z PCB calculated from S of [S PCB ] is shown in Fig. 5-6, and it was changed into [F PCB ] and [F PCB ] - from this [S PCB ] by (6). 0M 00M G Fig. 8. Z obtained by this de-embedded method. D. Verification of extracted Z The extracted Z is applied to part on Fig. 9 and the result Z N simulated is indicated on Fig. 20. To compare, Measurement result of Fig.2 is also shown on the same chart. Z N using Z agrees very well with measurement result. This proves that it can be De-embedded Load Model correctly by this method. Fig. 5. Equivalent circuit of Z PCB

7 Z N Fig. 9. Equivalent circuit of Z N using extracted Z Z N using extracted Z Z N calculated from measurement result 0M 00M G Fig. 20. Comparison of Z N using extracted Z ( Red ) and Z N calculated from measurement result( Black ). E. PDN mpedance using extracted Z The Power-GND impedance of Point A in Fig. using PCB data and extracted Z is shown by the green line in Fig. 2. This impedance is equivalent to the aqua line using the load model specially calculated from design data. With the proposed method, load model is successfully extracted with high accuracy. Power Delivery Network mpedance [Ω] 0 0. Simulation Result Point A(fig.) using 's design data (same as "aqua" line of Fig.3) De-embedded Result by this method Point A(fig.) using extracted Z 0M 00M G Fig. 2. PDN using extracted Z As show in Fig. 8, the load model of (Z ) is rising by more than 40 MHz, and PDN is also rising in the same way by more than 40 MHz as shown in Fig. 2. This means that the inductance ingredient of (especially Package in ) becomes dominant for more than 40 MHz of impedance. n other words, there are no ways but vender increases the capacity in included Package to lower more than 40 MHz of impedance and it's ineffective that PCB designer arranges additional capacitors on PCB. The conventional Power-GND impedance which has no Load models and this Power-GND impedance using the Load model extracted by this method are shown in Fig.. PCB designer didn't know even the frequency range to take a measure at the PCB design side, because there were no Load models. With the proposed method, on the other hand, the Load model was clearly defined. n case of this example, it's necessary that the PCB side to take the measure to lower PDN impedance in frequency range less than 40 MHz. n particular, there is the sudden change impedance rise around 20MHz. This seems to depend on anti-resonance of PCB and (especially Package). Therefore, PCB designer has to arrange some capacitors to lower impedance around 20MHz, avoid the signal line of around 20MHz from this PDN, and design the shape of Power and Ground plane without resonance 20MHz. Power Delivery Network mpedance [Ω] Simulation Result Point A(fig.) without model De-embedded Result by this method Point A(fig.) using extracted Z k 0k 00k M 0M 00M G Fig.. PDN mpedance without and with load model extracted by this method. V. CONCLUSONS A novel extraction method for load impedance inside package including on-chip wiring has been successfully demonstrated. The method is simple yet accurate without special equipment. The method will contribute efficient design for power delivery on PCB. REFERENCES [] Alex Waizman, Power Supply mpedance Profile Measurement Using FFT and Clock Gating, Electrical Performance of Electronic Packaging, 2003, pp.29-32, Oct [2] W.J.Lambert, R.Ayyanar, Estimation of Microprocessor nstantaneous Load Current for Voltage Regulator Optimization, Applied Power Electronics Conference and Exposition, APEC Twenty-Third Annual EEE, pp , Feb [3] S.Chickamenahalli, K.Aygun, M.J.Hill, K.Radhakrishnan, K.Eilert, E Stanford, Microprocessor Platform mpedance Characterization using VTT Tools Applied Power Electronics Conference and Exposition, APEC Twentieth Annual EEE, pp Vol. 3, 6-0 March 2005.