Eff ic ien t Space A lloca tion and Reclama tion M echan ism for Fla sh M em ory
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1 Journal of Chinese Com puter System s V ol131 N o ,,, (, ) E2m ail: zzliu@m ail. ustc. edu. cn : W eb,,, BSFTL. BSFTL, BSFTL, : ; ; ; ; ; : TP316 : A : (2010) Eff ic ien t Space A lloca tion and Reclama tion M echan ism for Fla sh M em ory YU E L i2hua, L IU Zhan2zhan, J IN Pei2quan, X IAN G X ian2yan (D epa rtment of Computer Science and Technology, U niversity of Science and Technology of China, Hefei , China) Abstract:W ith rap id increase of the density of flash m em ory and the em ergence of new flash2based app lications such as enterp rise com puting and w eb data m anagem ent, it becom es a critical issue to p rovide efficient m anagem ent for large2scale flash m em ory. This paper focuses on the low perform ance in garbage collection and space utilization of existing flash m em ory space m anagm ent m ethods, and p resents a novel efficient space allocation and reclaim ation m echanism, called BSFTL. BSFTL p rovides different m anagem ent schem es w ith hot and cold blocks. head, keep ing space utilization at high level. The experim ental results show ed that BSFTL could significantly reduce garbage collection over2 Key words: flash m em ory; flash translation layer; space allocation; garbage collection; space utilization; update load 1 ( Flash M em ory) [ 1 ].,, PDA, 2006,,, [ 1, 7, 12 ]..,, ( 2. 1 ).,,,,,,,, Intel 1998 ( Flash Translation L ayer, FTL ). FTL,, ( O racle DB 2 ) FTL, FTL [ 1, 4, 5, 10 ], N FTL [ 4 ] FA ST [ 10 ]. N FTL (NAND Flash Translation L ayer),. FA ST,., N FTL,, FA ST, N FTL ( ). N FTL FA ST, FTL 22 BSFTL (B lock2set2based FTL ). BSFTL FTL. N FTL FA ST, : (1) BSFTL ( 3 )., : : ( ). :,, 1952,,,,, ;,, 1983,, ;,, 1975,,,,, ;,, 1983,,
2 , N FTL FA ST, BSFTL, (2) BSFTL ( 4 ). (3), ( 5 )., BSFTL 2 ( ), FTL 2. 1 NO R NAND. NO R, NAND,. NAND. NAND [ 11 ], (w rite2once) ( bulk2erasing) / /, /,,,, ( out2 p lace update),,. [ 9 ]., /,,,, FTL FTL ( Flash Translation L ayer) [ 3 ],,,,, N FTL (NAND Flash Translation L ayer) [ 4 ],,,., FA ST [ 10 ]. FA ST,,, A FTL ( an adap tive flash translation layer) [ 1 ] A FTL,,, Kang FTL ( superblock2based FTL ) [ 5 ].,,.,,, NFTL N FTL [ 4 ] N FTL, ( ) (p rim ary block, P2 B lock),, ( ) ( rep lacem ent block, R 2 B lock).,,,,,,, N FTL,. N FTL, BSFTL,,, 2. 4 FAST FA ST ( Fully A ssociative Sector Translation) [ 10 ],,. FA ST,,,,,. FA ST, B SFTL,,,, 3 BSFTL 3. 1,, [ 6, 8 ]., N FTL, ;, 1 ( a). FA ST, BSFTL, N FTL FA ST,,,,,, (B lock2set) : n m. n m :
3 5 : n N 0 m f ng, 0 < f 1 (1) n +m 2, N, f,,, 2 BSFTL Fig. 2 A rchitecture of BSFTL,, 4 BSFTL,,.,, ( full) ( N FP ) : N FP = 0 m = f ng, ( overflow ). (2) m > f ng (3) 2. (B lock2g roup ) : 3. (B lock2pair) :., ; N FTL, BSFTL. BSFTL :. BSFTL ( ), 1 ( b), BSFTL,, ;,,, BSFTL, ( insertion) ( sepa2 ration),, BSFTL LB PB, LB, 3 ( a) :, LB,, BS., BS,,, LB BS, LB BS ;, LB,,,, 4. 2,. LB, TH, LB 3 ( b) B SFTL,,,,, ;.,,,,, HB, PB HB, BG HB, HB 3 ( c). 4. 4,,,
4 if (LB BG ) if (BG RB ) RB ; for(bg B lock) if (B lock ) B lock BG ; if (BG ) (BG ) BG ; BG RB; RB BG ; RB ; if (LB BP ) if (BP RB ) RB ; BP ; / /LB If (LB ) && ( BS) PB BS; BS RB ; PB RB, PB RB B P; RB ; ( a) LB. upda teload + +; Rank = LB. rank; P rev = LB. p rev; / / LB w hile ( P rev! = null && P rev. upda teload < LB. upda teload) P rev. rank + +; if ( P rev. rank > TH && P rev ) P rev ; Rank - - ; P rev = P rev. p rev; end w hile if (LB. rank! = Rank) LB. rank = Rank; if (LB. rank < = TH &&LB ) LB ; LB Rank ; ( b) HB B lock; for ( HB BG Page) Page B lock ; Page ; HB PB, PB ; for (BG RB ) if ( RB ) RB, RB ; ; ( c) BP B lock; for (BP Page) Page B lock, Page ; B P PB RB, PB RB ; ; ( d) 3 Fig. 3 A lgorithm s, B P, PB RB B P 3 ( d).,.,,, ;,,,. f,,., BSFTL, BSFTL. : 2. 0GH z (AM D A lthon X P 2. 0G ), 1GB ( Kingston DD R2). NAND [ 2, 7, 9 ], 1 [ 11 ] , 20%, 20%, 1 Table 1 Experim ental conditions 64 ( ) 128KB 2KB 1. 5m s 200 s 25 s 80%.,. N FTL FAST BSFTL (4) : f = (MAX R2B lock - N HB ) /N CB (4), MAX R2B lock N HB N CB., ( ). 4, 4 ( a) ( ), 4 ( b) ( 160).
5 5 : 823, FA ST BSFTL N FTL., 160, N FTL FA ST BSFTL ,, N FTL,., 4, BSFTL FA ST, BSFTL, 5 N FTL FA ST BSFTL, 5 ( a) 5 ( b). 5 ( a) 5 ( b), N FTL, 5 ( a) 5 ( b), N FTL 2. 5 ( a ) N FTL FA ST BSFTL ( ). 5 ( a), FA ST BSFTL N FTL, BSFTL FA ST BSFTL, N FTL FA ST,,., 5 ( a),, BSFTL FA ST,, BSFTL FA ST N FTL, BSFTL FA ST,, 5 ( b ) N FTL FA ST BSFTL ( 160). 5 ( b ), FA ST BSFTL N FTL, BSFTL FA ST., 5 ( b), FAST BSFTL, FA ST 3. 2, BSFTL N FTL, N FTL FA ST, BSFTL, , 6 ( a) 6
6 ( b), FA ST BSFTL N FTL. 6 ( a) ( ). 6 ( a),, FA ST BSFTL,, BSFTL FA ST.,. 6 ( b) FA ST BSFTL ( 160). 6 ( b), FA ST BSFTL,,, N FTL FA ST, BSFTL, 6 BSFTL, BSFTL BSFTL,,., BSFTL N FTL FA ST., N FTL FA ST, BSFTL References: [ 1 ] W u C H, Kuo T W. A n adap tive tw o2level m anagem ent for the flash translation layer in em bedded system s [ C ]. In Proc. of the 2006 IEEE /ACM Int l Conf. on Computer2A ided D esign ( ICCAD 06), 2006, [ 2 ] W u C H, Kuo T W, Chang L P. The design of efficient initializa2 tion and crash recovery for log2based file system s over flash m em o2 ry [ J ]. ACM Trans. on S torage ( TO S), 2006, 2 (4) : [ 3 ] Intel Corporation. U nderstanding the flash translation layer ( FTL ) specification[ R ]. Technical Report A P2684, [ 4 ] Kim J, Kim J M, N oh S H, et al. A space2efficient flash transla2 tion layer for compact2flash system s [ J ]. IEEE Trans. on Consum 2 er Electronics, 2002, 48 ( 2) : [ 5 ] Kang J U, Jo H, Kim J S, et al. A superblock2based flash transla2 tion layer for NAND flash m em ory [ C ]. In Proc. of the 6 th ACM & IEEE Int l Conf. on Em bedded Softw are ( EM SO FT 06), 2006, [ 6 ] Hsieh J W, Kuo T W, Chang L P. Efficient Identification of hot data for flash m em ory storage system s [ J ]. ACM Trans on S torage ( TOS ), 2006, 2 (1) : [ 7 ] Chang L P, Kuo T W. Efficient m anagem ent for large2scale flash2 m em ory storage system s w ith resource conservation [ J ]. ACM Trans. on S torage ( TOS ), 2005, 1 ( 4) : [ 8 ] Chang L P. O n efficient w ear leveling for large2scale flash2m em ory storage system s [ C ]. In Proc. of the 2007 ACM Symp. on Ap2 p lied Computing ( SAC 2007), 2007, [ 9 ] W ei P, Yue L, L iu Z, et al. Flash m em ory m anagem ent based on p redicted data exp iry2tim e in em bedded real2tim e system s [ C ]. In Proc. of the 2008 ACM Symp. on App lied Computing ( SAC 2008). 2008, [ 10 ] L ee S W, Park D J, Chung T S, et al. A log buffer2based flash translation layer using fully2associative sector translation [ J ]. ACM Trans. on Em bedded Computing System s, 2007, 6 ( 3 ) : A rticle 18. [ 11 ] Sam sung Electronics. K9XXG08UXA 1G x 8 B it / 2G x 8 B it / 4G x 8 B it NAND Flash M em ory D ata Sheet[ Z ] [ 12 ] X iang X, Yue L, L iu Z, et al. A reliable B 2tree imp lem entation o2 ver flash m em ory [ C ]. In Proc. of the 2008 A CM Symp. on Ap2 p lied Computing ( SAC 2008). 2008,
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