Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure

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1 736 IEICE TRANS. ELECTRON., VOL.E91 C, NO.5 MAY 2008 PAPER Special Section on Fundamentals and Applications of Advanced Semiconductor Devices Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure Han-A-Reum JUNG, Member, Kyoung-Rok HAN, Young-Min KIM, and Jong-Ho LEE a), Nonmembers SUMMARY A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (V th ) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (V th, DIBL and SS) by considering device structure and doping profile of the cell. key words: saddle, SONOS, side-gate, recess channel, DIBL 1. Introduction As non-volatile memory technology enters into sub-100 nm node and reaches sub-40 nm, it is needed to apply the highdensity and high-performance memory cell transistors such as a recessed structure as a flash memory cell [1] [6]. The recess channel MOSFETs is a promising device for suppressing short channel effects (SCE), because the structures with shallow junctions can be fabricated without any increase in series resistance [9], [10]. Recently, the recessed channel array transistor (RCAT) has also been proposed to reduce SCE in cell transistor [7] and the RCAT asymmetric channel doping (ASC) [8] have been proposed to improve electrical characteristics. However, these recessed channel devices have several problems such as high V th and DIBL. To overcome these problems, a saddle MOSFET [8], [9] with a recessed channel and side gates has been proposed. The saddle MOSFET has advantages such as excellent short-channel effect immunity, less DIBL, reasonable V th. SONOS type flash memory cell for multi-bit operation uses nitride layer to localize charge trapping [11], [12]. In this paper, we propose a new SONOS flash memory cell with saddle type channel structure, and its performance is compared with those of SONOS type recessed channel device. In addition, we are consider device design by changing recess depth (x rd ), side-gate overlap length (L ov side ), local channel doping concentration, and ΔR p of channel doping Manuscript received September 19, Manuscript revised January 11, The authors are with School of Electrical Engineering Computer Science, Kyungpook National University in Daegu , Korea. a) jongho@ee.knu.ac.kr DOI: /ietele/e91 c using 3-D device simulation [13] and compare the device with conventional SONOS flash memory cell with recessed channel structure. 2. Device Structure and Key Fabrication Steps Figure 1(a) shows 3-dimensional schematic view of the SONOS flash memory cell with saddle type channel structure. The side-gate (hatched region) covers some of the sidesurface of the recessed channel region. The L ov side is a distance that the control gate and underneath gate stack (ONO) cover the side-surface of the recessed region. Figure 1(b) shows cross-sectional view of the proposed cell structure cut along channel length direction. The open width of the recess region is 40 nm. The gate length is limited by the gate stack which filled in the recessed region. For example, if O/N/O stack is 4/5/6 nm thick, the gate stacks formed on both sides of the recessed region consumes 30 nm. Then remaining 10 nm for a given 40 nm open width is used for the filling of the control gate. The x j stands for the junction depth from the top of the body and is fixed at 30 nm. The L g represents physical gate length and is considered to be equal to the recess open width in the top view. The x rd is defined as a recess depth from the top surface of the thin body. Here, actual effective channel length (L eff ) depends on the recess depth and is longer than the recess width. For the given recess width and depth, the L eff is given by approximately L g + 2(x rd x j ) [1]. The physical control gate width is 10 nm for an L g of 40 nm. The thin body width is fixed Fig. 1 (a) 3-dimensional schematic view of saddle SONOS flash memory device and its cross sectional views across the gate (b) and the body (b). Copyright c 2008 The Institute of Electronics, Information and Communication Engineers

2 JUNG et al.: DEVICE DESIGN OF SONOS FLASH MEMORY CELL WITH SADDLE TYPE CHANNEL STRUCTURE 737 Fig. 2 Key steps to form SONOS flash memory cell with saddle type channel structure. at 20 nm. The thicknesses of O/N/O layers are 4 nm (tunnel oxide), 5 nm (nitride), and 6 nm (block oxide), respectively. The uniform body doping is cm 3 and n + poly gate is applied. The device has two localized channel doping profiles. The #1 p-type channel doping is localized under a vertical position near source/drain (S/D) junction for V th control, suppression of DIBL, and hot electron generation when it is applied to NOR flash memory. The #2 p-type channel doping is localized near the bottom of the recessed region for NAND flash memory application. This localized channel doping has to reduce bottom corner effect. Figure 2 shows the schematic key process steps are an example to fabricate the Saddle MOSFETs in this work. Fig. 2(a) shows the schematic after planarization by using CMP. A half of the Si body is shown together with the isolation oxide beside the Si body to show the structure inside trench clearly in later steps. Trench is formed in the wordline direction across the Si body and the oxide. To form the trench, patterned oxide and Si are etched as shown in Fig. 2(b). The oxide exposed in the recessed region can be etched to a reasonable thickness by isotropic wet etching as shown in Fig. 2(c), by which the side-gate can be realized with a side-gate overlap length (L ov side ). Then the tunneling oxide is grown (4 nm), followed by nitride deposition (5 nm) for storage node. The blocking oxide is formed (6 nm), and then poly-silicon for control gate is formed as shown in Fig. 2(d). This process step is an example to fabricate the device structure in this manuscript. There should be another method to fabricate the structure D Device Simulation and Results Figure 3 shows V th and DIBL characteristics versus the local channel doping (#1) concentration at recess depth of 70 nm and 90 nm. The S/D doping has a cm 3 and the L ov side is 15 nm. The high S/D doping concentration of cm 3 is applied to generate hot carriers near the drain junction easily for NOR type flash memory opera- Fig. 3 V th and DIBL characteristics versus p-type local channel doping concentration of #1. The recess depth is 70 nm and 90 nm. The uniform body doping is cm 3. Here, ΔR p is 15 nm. tions. And the device has #1 p-type local channel doping of 10 nm underneath of S/D forv th control and DIBL suppression. As the #1 doping concentrations with the ΔR p of 15 nm increases from cm 3 to cm 3,the V th is increased linearly. The V th is not sensitive to short channel effect because effective channel length is long. The device structure in this work has a triple-gate structure. The V th model of a long-channel triple-gate device is given by [14], V th = V FB + 2ψ B + qα cn b x dep (1) C ox where α c, N b,andx dep represent a corner factor (0.4), body doping concentration, and gate depletion width, respectively. If the body is fully deleted, then the x dep becomes 0.5 of the body thickness. For planar double-gate or singlegate MOSFETs, the α c is 1. Thus the V th for a triple-gate MOSFET has less dependence on N b or x dep. Linear V th versus N b shown in Fig. 3 can be explained well by (1). If we change the x dep (i.e. body thickness) at a fixed N b,then we can expect the V th changes linearly. With increasing the peak of #1 local channel doping concentration, DIBL starts to decrease and then increases. Since the DIBL increase is abnormal, we investigated potential ratio along the channel surface. Figure 4 shows the potential ratio (Φ s (V DS = 0.1 V)/ Φ s (V DS = 1.1 V)) with local channel doping of #1. The potential was obtained at V GS = V th for each V DS. Here, smaller DIBL means that the ratio is closer to 1 in the channel region. The potential ratio at an #1 local channel doping of cm 3 shows the channel potential ratio closer to 1, and the DIBL at the concentration is lower as shown in Fig. 3. In Fig. 5, shows V th and DIBL characteristics of the saddle flash memory cell with the #1 local channel doping at recess depth of 90 nm and 120 nm. Here, ΔR p is 30 nm. With increase of #1 local channel doping, V th is increased irrespectively of x rd or ΔR p. For x rd of 90 nm, abnormal DIBL is shown at #1 local channel doping of cm 3 and the x rd of 120 nm, it is shown at #1 local channel doping

3 738 IEICE TRANS. ELECTRON., VOL.E91 C, NO.5 MAY 2008 Fig. 4 Potential ratio along the channel near the recess for the DIBL comparison between cm 3 and cm 3 of #1. The potential values were captured at V GS of 0 V. Fig. 7 V th and DIBL characteristics versus ΔR p of the #1 doping profile as a function of a peak concentration ( cm 3 ). The x rd is 90 nm and 120 nm. Fig. 5 V th and DIBL characteristics versus p-type localized doping profiles of #1 (nearby x j ). The x rd is 90 nm and 120 nm. Here the x j doping has a peak value of cm 3 and ΔR p of 30 nm. Fig. 8 V th and DIBL characteristics with x rd. The #1 channel doping concentration is cm 3 and the ΔR p is 15 nm. Here the x j is 30 nm and L ov side is 15 nm. Fig. 6 I D -V GS characteristics of the saddle type device and recess type device with x rd of 90 nm. The insert shows V th and DIBL versus #1 doping concentration. The ΔR p of the #1 doping profiles are 15 nm and 30 nm. Here, x j is 30 nm and L ov side is 15 nm. of cm 3. Abnormal DIBL is observed as explained in Fig. 4. Figure 6 shows I D -V GS characteristics curves of the saddle flash cell and recess flash cell at ΔR p of 15 nm and x rd of 90 nm. The #1 local channel doping is fixed at cm 3. The saddle type device has very low V th and DIBL. The SS and I on characteristic is improved than a recessed type device. Figure 7 shows V th and DIBL characteristics versus ΔR p of the #1 local channel doping. Here, the peak concentration of the #1 local channel doping is fixed at cm 3. The x rd is fixed at 90 nm and 120 nm, respectively. With increase ΔR p of #1 channel doping, DIBL is decreased and V th is increased. By comparing V th at x rd sof 90 nm and 120 nm, V th at x rd of 90 nm is higher than that of 120 nm, and DIBL is increased abnormally due to the fact explained in Fig. 3. Figure 8 showsv th and DIBL characteristics with x rd. The recess open width (L g )is40nmandl ov side is 15 nm. Here, peak concentration of #1 channel doping is cm 3 and the ΔR p is 15 nm. As the x rd increases from 50 nm to 90 nm, V th and DIBL decrease and then show saturation for further increase of x rd.whenx rd was deeper than 90 nm, V th is not influenced by local channel doping. The DIBL increase at x rd of 120 nm is abnormal and needs to be studied. In Fig. 9, shows the V th and DIBL versus S/D junction depth (x j ). Here, ΔR p of #1 channel doping profiles

4 JUNG et al.: DEVICE DESIGN OF SONOS FLASH MEMORY CELL WITH SADDLE TYPE CHANNEL STRUCTURE 739 Fig. 9 V th and DIBL characteristics with x j as a ΔR p of the #1 channel doping profiles. The ΔR p of 16 nm, 24 nm and 32 nm and #1 local channel doping of cm 3. Fig. 11 V th and DIBL characteristics with localized channel doping concentration of #2. The #2 doping type is 5-point peak value. Most similar real process type. Here the L ov side is 15 nm. Fig. 10 V th and DIBL characteristics with L ov side of the saddle SONOS flash memory cells. The x j doping has a peak value of cm 3 and #1 localized channel doping concentration of cm 3. Here, ΔR p is 15 nm. is increased as x j increases to reflect practical situation. The ΔR p s corresponding to x j s of 10 nm, 30 nm, 50 nm are 16 nm, 24 nm and 32 nm, respectively, at #1 local channel doping of cm 3. With increasing x j, V th and DIBL are increased due to the increase of doping concentration at the recessed bottom region. By changing side-gate overlap length (L ov side ), we can obtain V th and DIBL as shown in Fig. 10. Here, the S/D junction doping and #1 doping concentration are fixed at cm 3 and cm 3.Thex rd and ΔR p are fixed at 90 nm and 15 nm, respectively. The V th and DIBL increases with increasing x j due to the fact that doping increases near the bottom of the recessed region. With increasing L ov side, the V th decreases and DIBL is improved. We obtain reasonable L ov side at the range between 10 nm and 15 nm. Next, we compare the NOR cells and the NAND cells while keeping the same geometry including the film structure to clarify the effect of the saddle structure. Figure 11 shows V th and DIBL characteristic with #2 local channel doping concentration. Here, S/D doping concentration is fixed at cm 3, which is lower than S/D doping of NOR type flash memory. This channel doping design is Fig. 12 Potential ratio obtained by cutting along recess channel of saddle type device with cm 3 and cm 3 of #2. adaptable for NAND type flash memory using FN tunneling mechanism for programming/erasing. #2 local channel doping near the bottom of recess region reduces bottom corner effect. With increasing #2 channel doping concentration, V th is increased. However, DIBL is increased abnormally. To show internal physics of the abnormal DIBL, we check up the potential ratio along the recess channel with #2 local channel doping as shown in Fig. 12. The potential ratio for #2 local channel doping of low local doping ( cm 3 ) is close to 1 than that of the high local doping ( cm 3 ). The potential ratio value close to 1 represents smaller DIBL. Figure 13 shows I D -V GS curves of saddle type device with ΔR p of #2 local channel doping. The #2 channel doping profile is fixed at the peak concentration of cm 3. The x rd and L g are fixed at 90 nm and 40 nm, respectively. With ΔR p increase, V th is increased and DIBL is decreased. However, the SS is increased. The insert in this figure represents V th and DIBL versus the ΔR p of #2 local channel doping, which shows the ΔR p variation more clearly. V th increases at a ΔR p over 20 nm and DIBL decreases significantly at a ΔR p at 30 nm. Figure 14 shows V th and DIBL characteristics with L ov side of the saddle SONOS flash memory cell. Because

5 740 IEICE TRANS. ELECTRON., VOL.E91 C, NO.5 MAY 2008 Fig. 10. Figure 15 shows V th and DIBL versus x rd at the #2 local channel doping concentration of cm 3 and ΔR p of 15 nm. DIBL is improved with increasing x rd owingtothe increase of effective channel length. The V th has nearly constant value about V irrespectively of the x rd,since the V th near the bottom of the recess region determines V th of the device at a given channel doping. 4. Conclusion Fig. 13 I D -V GS characteristics with ΔR p of the #2 doping profile as a function of a peak ( cm 3 ). The insert shows V th and DIBL versus ΔR p of #2. The L g is 40 nm and x rd is 90 nm. We proposed a new SONOS flash memory cell with saddle type channel structure and considered device design in terms of electrical characteristics (V th, DIBL and SS) for high performance of sub-40 nm flash memory cell transistor. Saddletype cell transistors showed lower V th, and better DIBL, SS and I on than those recessed channel devices. The proposed Saddle-type memory cell transistors were designed in terms of local channel doping profile and geometry for NOR type and NAND type flash memory cell applications. These devices have better DIBL and reasonable V th with changing local doping profile, recess depth, and side-gate length. Acknowledgments This work was supported by The National research program for the 0.1 Tb Non-volatile Memory Development sponsored by Korea Ministry of Science & Technology in Fig. 14 V th and DIBL characteristics with L ov side of the saddle type device. The #2 channel doping concentration has cm 3. Here, ΔR p is 15 nm. Fig. 15 V th and DIBL characteristics as a parameter of x rd. The #2 doping concentration is cm 3 and the ΔR p is 15 nm. Here the x j is 30 nm and L ov side is 15 nm. NAND flash memory cells in this figure have only #2 local channel doping having peak concentration of cm 3 near the bottom of the recessed region, V th and DIBL are decreased with increasing L ov side. V th anddiblshownosaturation while changing L ov side from 5 nm to 15 nm, which is different from the data in NOR cell transistors shown in References [1] K.R. Han and J.H. Lee, Two-bit/cell programming characteristics of high-density NOR-type flash memory device with recessed channel structure and spacer-type nitride layer, JJAP, vol.45, no.38, pp.l1027 L1029, [2] B.Y. Choi, B.G. Park, Y.K. Lee, S.K. Sung, T.Y. Kim, E.S. Cho, H.J. Cho, C.W. Oh, S.H. Kim, D.W. Kim, C.H. Lee, and D.G. Park, Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 60 nm NVM technology using outer sidewall spacer scheme with damascene gate process, VLSI Symp. Tech. Dig., pp , [3] Y.K. Lee, J.S. Sim, S.K. Sung, C.J. Lee, T.H. Kim, J.D. Lee, B.G. Park, D.H. Lee, and Y.W. Kim, Multilevel vertical-channel SONOS nonvolatile memory on SOI, IEEE Electron Device Lett., vol.23, no.11, pp , Nov [4] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.J. King, FinFET SONOS flash memory for embedded applications, IEDM Tech. Dig., pp , [5] J.Y. Kim, C.S. Lee, S.E. Kim, I.B. Chung, Y.M. Choi, B.J. Park, J.W. Lee, D.I. Kim, Y.S. Hwang, D.S. Hwang, H.K. Hwang, J.M. Park, D.H. Kim, N.J. Kang, M.H. Cho, M.Y. Jeong, H.J. Kim, J.N. Han, S.Y. Kim, B.Y. Nam, H.S. Park, S.H. Chung, J.H. Lee, J.S. Park, H.S. Kim, Y.J. Park, and K.N. Kim, The breakthrough in data retention time of DRAM using recess-channel-array transistor (RCAT) for 88 nm feature size and beyond, VLSI Symp. Tech. Dig., pp.11 12, [6] K.R. Han, B.K. Choi, Y.M. Kim, K.H. Park, M.K. Jeong, and J.H. Lee, Analysis of geometric dependency and local channel doping effect on recessed channel MOSFETs, Proc. SNW., pp.77 78, 2006.

6 JUNG et al.: DEVICE DESIGN OF SONOS FLASH MEMORY CELL WITH SADDLE TYPE CHANNEL STRUCTURE 741 [7] J.W. Lee, Y.S. Kim, J.Y. Kim, Y.K. Park, S.H. Shin, S.H. Lee, J.H. Oh, J.G. Lee, J.Y. Lee, D.I. Bae, E.C. Lee, C.S. Lee, C.J. Yun, C.H. Cho, K.Y. Jin, Y.J. Park, T.Y. Chung, and K.N. Kim, Improvement of data retention time in DRAM suing recess channel array transistors with asymmetric channel doping for 80 nm feature size and beyond, Proc. ESSDERC., pp , [8] K.H. Park, K.R. Han, and J.H. Lee, Highly scalable saddle MOS- FET for high-density and high-performance DRAM, IEEE Electron Device Lett., vol.26, no.9, pp , Sept [9] K.H. Park, K.R. Han, and J.H. Lee, Characterizations of saddle MOSFET with recessed channel and side-gate, Proc. SNW., pp.66 67, [10] J. Tanaka, T. Toyabe, S. Ihara, S. Kimura, H. Noda, and K. Itoh, Simulation of sub-0.1-pm MOSFET s with completely suppressed short-channel effect, IEEE Electron Device Lett., vol.14, no.8, pp , [11] Y.K. Lee, K.W. Song, J.W. Hyun, J.D. Lee, B.G. Park, S.T. Kang, J.D. Choe, S.Y. Han, J.N. Han, S.W. Lee, O.I. Kwon, C. Chung, D.G. Park, and K.N. Kim, Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process, IEEE Electron Device Lett., vol.25, no.5, pp , May [12] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, NROM: A novel localized trapping, 2-bit nonvolatile memory cell, IEEE Electron Device Lett., vol.21, no.11, pp , Nov [13] SILVACO International, ATLAS User s Manual, [Online], Available: [14] B.K. Choi, K.R. Han, Y.M. Kim, Y.J. Park, and J.H. Lee, Threshold-voltage modeling of body-tied FinFETs (Bulk Fin- FETs), IEEE Trans. Electron Devices, vol.54, no.3, pp , March Han-A-Reum Jung was born in Daegu, Korea, on October 9, She received the B.S. degree in Electrical Engineering and Computer Science in 2006 from Kyungpook National University, Daegu, Korea, where she is currently working toward the M.S. degree from Kyungpook National University, Daegu, Korea. Her research interests include nano-scale CMOS (bulk FinFET) devices simulation and Saddle type flash memory device design. Young-Min Kim received the B.S. degree in chemical engineering from Kyungpook National University, Daegu, Korea, and the M.S. degrees from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, and North Carolina State University (NCSU), Raleigh, USA. He is currently pursuing the Ph.D. degree in the guidance of Professor Jong- Ho Lee. His research interest is in the simulation and fabrication of quantum wire transistor and NFGM. Jong-Ho Lee received the B.S. degree from Kyungpook National University, Daegu, Korea, in 1987 and the M.S. and Ph.D. degrees from Seoul National University, Seoul, in 1989 and 1993, respectively, all in electronic engineering. In 1993, he worked on advanced BiCMOS process development at ISRC, Seoul National University as an Engineer. In 1994, he was with the School of Electrical Engineering, Wonkwang University, Iksan, Chonpuk, Korea. From 1994 to 1998, he was with ETRI as an invited member of technical staff, where he worked on deep submicron SOI devices, device isolation, 1/f noise, and device mismatch characterization. From August 1998 to July 1999, he was with Massachusetts Institute of Technology, Cambridge, as a Post-Doctor, where he was engaged in the research on sub-100 nm double-gate CMOS devices. Since 2002, he has been with Kyungpook National University, Daegu, Korea, where he is currently a Full Professor of electrical and computer engineering. He has authored or coauthored over 87 journal papers and over 189 conference papers related to his research and has been granted 46 patents in this area. His research interests include sub-100 nm device technologies, device characterization and DC/RF device modeling, high performance IC design, and 3-D Microsystems including sensors. In 2006, he was a recipient of the This Month s Scientist Award for his contribution in the development of practical highdensity/high-performance 3-dimensional nano-scale CMOS devices. Kyoung-Rok Han received the B.S. degree in electrical engineering in 2002 from Wonkwang University and M.S. degree in electrical engineering in 2004 from Kyungpook National University, Daegu, Korea. He is pursuing Ph.D. degree at the same institution. His research interests include the nano-scale CMOS (bulk FinFETs) and flash memory application of the device structure.

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