FC1001 Specification (Voice Synthesis IC)

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Dorothy Walters
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2 1. General Description FC1001 is a (VSI) with LDO(Low Drop-Out regulator), the Power-On Reset (POR), the Ring Oscillator, and the Power stage. FC1001 is adopted the FusionChips s Sub-Band Codec(SBC) Algorithm for maintaining the high quality acoustic sound. For the low power consumption, FC1001 is made by the low power CMOS processes. 1.1 Feature Built-in Power-On Reset Built-in PWM processor and Power Stage for 8Ω Speaker - AVDD=3.0V : 400mW (Typ) - AVDD=3.3V : 490mW (Typ) - AVDD=5.0V : 1.1W (Typ) Built-in Ring Oscillator (16.384MHz ± 7%) Built-in Low Drop-Out regulator (2.8V ± 0.2V) Use external Serial Flash memory. (1Mbits ~ 128Mbits) Volume Controller Text Edit Function. Maximum 30 Chapter continuous indexing play (MCU mode) (For indexing play, the sampling frequency must be same over all selected chapters) Two LED connection ports. SBC Decoder for mono sound (3.526:1) CRC Check to detect Error of recorded Serial Flash data (MCU mode Only) 430bytes data FIFO to manage data control Supported Sampling Frequency (fs) : 4kHz, 8kHz, 16kHz Play time (External 4Mbits) : 230sec@4kHz, 115sec@8kHz, 57sec@16kHz Number of Phrases : - 16 under Stand Alone Operation under MCU Operation Repeat function : 1 / infinite times Control method : Stand Alone Operation(by external keys), MCU Operation(By SPI I/F) Master clock Frequency : MHz Supply voltage : 3.0~5V Package : 48 QFN (7X7) 1.2 Application GPS, Navigation, Toy, Audio Book Machinery and Tools where the small-sized electronics and vocal guidance is necessary. FusionChips Inc. Rev

3 2. Block Diagram 3. PKG Diagram FusionChips Inc. Rev

4 4. Pin Descriptions M mode : MCU mode, S mode : Standalone mode No Name IO Description 1 LED_OUT1 O LED1 connection port. 8mA 2 LED_OUT2 O LED1 connection port. 8mA 3 DEC I Chapter decrement command in STA mode. PU 4 DVSS1 G Digital ground. 5 CSB_SEL I M mode : Flash memory chip selection for debug. PD H : Flash memory debugging mode. L : MCU debugging mode. 6 PLAY/BUSY IO When STA mode, this pin is used as PLAY key. PU Otherwise this pin is used as BUSY signal. 7 CSB/VUP I M mode : Chip selection for SPI command. PU S mode : Volume up. Active L One shot pulse. 8 SCK I M mode : Serial clock input. PD 9 SDATI/VDN I M mode : Serial data input. PU S mode : Volume down. Active L One shot pulse. 10 SDATO O Serial data output. 11 MCU I L=Standalone mode, H=MCU(SPI I/F mode) PD 12 CSB_SF O External Serial Flash memory Chip select. Active L. 13 CLK_SELB I Clock source selection control pin. PD L : Internal Ring Oscillator, H : External X tal 14 SO_SF I External Serial Flash memory Data Output. 15 KEY0 I Direct voice synthesis for chapter1. Active L One shot PU 16 KEY1 I Direct voice synthesis for chapter2. Active L One shot PU 17 KEY2 I Direct voice synthesis for chapter3. Active L One shot PU 18 KEY3 I Direct voice synthesis for chapter4. Active L One shot PU 19 KEY4 I Direct voice synthesis for chapter5. Active L One shot PU 20 KEY5 I Direct voice synthesis for chapter6. Active L One shot PU 21 KEY6 I Direct voice synthesis for chapter7. Active L One shot PU 22 KEY7 I Direct voice synthesis for chapter7. Active L One shot PU 23 KEY8 I Direct voice synthesis for chapter9. Active L One shot PU 24 KEY9 I Direct voice synthesis for chapter10. Active L One shot PU FusionChips Inc. Rev

5 No Name IO Description 25 REP I S mode only. Repeat control command. PD REP=0 : 1 time REP=1 : infinite time 26 RCK O Test mode signal output. 27 STOP I Voice synthesys stop command. PU Active L One shot pulse. 28 DVSS2 G Digital ground. 29 RESETB IO POR output in normal mode. Reset input in test mode. 30 VDDL P Digital Power. 31 LDO_OUT Ana LDO output 32 LDO_IN Ana LDO input 33 AVDD P Analog power. 34 PWM_A Ana Power Stage s terminal A output. (BTL mode) 35 PWM_B Ana Power Stage s terminal B output. (BTL mode) 36 AVSS G Analog ground. 37 SI_SF O External Serial Flash memory Data Input. 38 KEY10 I Direct voice synthesis for chapter11. Active L One PU shot 39 KEY11 I Direct voice synthesis for chapter12. Active L One PU shot 40 KEY12 I Direct voice synthesis for chapter13. Active L One PU shot 41 SCK_SF O External Serial Flash memory clock. 42 KEY13 I Direct voice synthesis for chapter14. Active L One PU shot 43 KEY14 I Direct voice synthesis for chapter15. Active L One PU shot 44 KEY15 I Direct voice synthesis for chapter16. Active L One PU shot 45 XI I MHz X tal is used. 46 XO O 47 TEST0 I Test mode 0 pin. Please connect to DVSS. PD 48 TEST1 I Test mode 1 pin. Please connect to DVSS. PD *1. PU : Pull-Up type pad *2. PD : Pull-Down type pad FusionChips Inc. Rev

6 5. Electrical Characteristics 5.1 absolute Maximum Ratings Symbol Parameter Min Max Unit Comment AVDD Analog DC Supply voltage V VDDL Digital DC Supply voltage V VIN Input voltage V Except LDO_IN VOUT Output voltage 0 VDDL+0.5 V Except A, B, LDO_OUT TSTG Storage temperature Recommended Operating Conditions Symbol Parameter Min Max Unit Comment AVDD Analog DC Supply voltage V VDDL Digital DC Supply voltage V Connect to LDO_OUT VIN Input voltage V Except LDO_IN VOUT Output voltage V Except A, B, LDO_OUT TA Operating temperature FusionChips Inc. Rev

7 5.3 DC Characteristics (Except XI, XO, AVDD and all analog pins) VDDL=2.8V, Junction temperature=0~100 Symbol Parameter Condition Min Typ Max Unit V IH Input High Voltage CMOS *1 2.0 V Schmitt Trigger *1 (V T+ ) 2.0 V V IL Input Low Voltage CMOS *1 0.4 V Schmitt Trigger *1 (V T- ) 0.4 V V hyx Hysteresis (V T+ - V T- ) 0.6 V I IH Normal Input High Current VIN=VDDL ua Pull-down Inpu High Current VIN=VDDL 72 ua I IL Normal Input Low Current VIN=GND ua Pull-down Input Low Current VIN=GND -82 ua V OH Output High Voltage *2 Type B1 I OH =-0.9mA 2.4 V Type B2 I OH =-1.8mA 2.4 V Type B4 I OH =-3.6mA 2.4 V Type B8 I OH =-7.2mA 2.4 V V OL Output Low Voltage *2 Type B1 I OH =0.9mA 0.4 V Type B2 I OH =1.8mA 0.4 V Type B4 I OH =3.6mA 0.4 V Type B8 I OH =7.2mA 0.4 V *1 : Input buffers meet both LVCMOS and LVTTL specifications *2 : Type B1 = 0.9mA output drive cells. Type B2 = 1.8mA output drive cells. Type B4 = 3.6mA output drive cells. Type B8 = 7.2mA output drive cells. FusionChips Inc. Rev

8 5.4 Timing Diagram SPI1 Timing (MCU command sending interface) Fig 5-1 SPI1 Command Write Timing (C1,C0=2 b00) Fig 5-2 SPI1 Command Read Timing (C1,C0=2 b01) Fig 5-3 SPI1 AC Timing Table 5.1 SPI1 AC Characteristics Symbol Parameter Min Typ Max Unit t1 CSB Setup 5 20 ns t2 SDATI Setup 5 20 ns t3 SCK Clock Duty 40:60 50:50 60:40 % t4 SCK Period 2 MHz t5 CSB High Width 3 us FusionChips Inc. Rev

9 5.4.2 SPI2 Timing (SPI I/F for Serial Flash Debugging) SPI2 mode is used to program, erase, read operation of Internal Serial Flash memory. This mode uses CSB_SEL, CSB, SCK, SDATI, SDATO pins. In this mode, MCU pin should be connected to VDD. (FC1001 assume that W# and HOLD# of Serial Flash memory is connected to VDD) See Serial Flash Memory Spec for detail Function and timing Decode Timing Using Internal Flash Memory Mode Decoding Command AOUT td1 trep_d1 Fig 5.4 Decoding & repeat timing in Internal Flash memory mode Using Data by SPI I/F Decoding Command AOUT td2 td1 Fig 5.5 Decoding timing in SPI I/F mode Table 5.2 AC timing for decoding Symbol Parameter fs=4khz fs=8khz fs=16khz Comments td1 Data out delay 32msec 16msec 8msec *1 td2 FIFO buffer delay *2 trep_d1 Blank period in repeat mode 16msec 8msec 4msec *1 : The td1 is the time-gap between the start command for decoding and the real audio output. *2 : The td2 is the data downloading time from the flash memory to FIFO buffer. 1. FC1001 has the 256 byte FIFO for data buffer. FusionChips Inc. Rev

10 6. Function Description 6.1 LED Function FC1001 has two LED control output ports. In the STA mode, LED is controlled by voice level as shown Fig7-1. Here, Voice signal is non-volume controlled signal. 100% 50% 25% Audio Out LED_OUT1 LED_OUT2 Fig 7-1 The relation between Voice level and LED control signal In the MCU mode, LED output mode is controlled by register. ($07) Fig 7.2 LED connection method FusionChips Inc. Rev

11 6.2 Index Play mode (MCU mode Only) The index play mode is prepared to increase Memory efficiency. Index play mode is valid in the MCU mode and data should be same sampling frequency. Index play mode is performed as below 1 Set index_m($01.bit1) to 1. 2 Set chapter numbers using INDEX_CHAP($0b). You can set maximum 30 chapters. 3 Set sbc_on($02.bit7) to 1. 4 Voice is synthesized. 6.3 Ext_Mem play mode (MCU mode Only) You can use data that is transferred MCU or another IC instead of the external serial flash that is connected to FC1001 directly. Input data should be encoded SBC Codec, 1 set ext_mem($01.bit0) to 1. 2 set sbc_on($02.bit7) to 1. 3 Data is inputted by SBC_DATA($0ah) register. When BUSY pin goes High, FC1001 s Internal FIFO is full. So, you stop data transfer till BUSY pin goes low. 4 After voice synthesis process is completed, clear ext_mem($01.bit0)to DEC KEY (STA mode Only) 1 When current chapter number is n and you push DEC key one time, chapter number n-1 is decoded. After process is completed, chapter number is n-1. 2 When current chapter number is n and you push DEC key m time, chapter number n-m is decoded. After process is completed, chapter number is n-m. 3 When current chapter number is n and you push DEC key m time, chapter number n-m is decoded. If you stop decoding, the synthesis process is stopped and chapter number is n-m. 6.5 PLAY Key (STA mode Only) 1 When current chapter number is n and you push PLAY key one time, chapter n is decoded. After decoding process is completed, chapter number is n+1. 2 When current chapter number is n and you push PLAY key one time, chapter n is decoded. If you push STOP key during decoding process, the decoding process is stopped and chapter number is n. (Chapter number does not change) 6.6 KEY0 ~ 15 (STA mode Only) You can decode chapter directly from chapter 0 to chapter 15 using KEY0 ~ KEY15. Chapter16 and above chapters can be decoded by PLAY key or DEC key. 6.7 REP key (STA mode Only) When you set REP key as High, the same chapter is decoded repeatedly. FusionChips Inc. Rev

12 7. Application 7.1 Reference Board Circuit AVDD(>DC 3V) 47uF 0.1uF DVDD(DC 2.8V) 18pF 1M 0.1uF VSS LED1 18pF TEST0 TEST1 SCK_SF SI_SF LED2 CSB_SEL BUSY CSB SCK SDATI SDATO MCU DVDD(2.8V) DEC 3 VSS CSB_SF 12 DEC DVSS1 CSB/VUP SCK SDATI/VDN SDATO MCU CSB_SF TEST1 LED_OUT1 LED_OUT2 CSB_SEL PLAY/BUSY TEST0 XO KEY0 SO_SF CLK_SELB XI KEY4 SCK_SF KEY5 KEY7 KEY10 FC1001 ( External Memory Version) KEY1 KEY15 KEY2 KEY14 QFN48 (7X7) KEY3 KEY13 KEY12 KEY6 KEY11 KEY8 SI_SF AVSS PWM_B PWM_A AVDD LDO_IN LDO_OUT VDDL RESETB DVSS2 STOP KEY9 RCK REP 36 VSS 1.5nF Ω AVDD nF 31DVDD(2.8V) VSS 27 STOP REP 22uF TEST TEST0 CLK_SELB SO_SF CLK_SELB KEY0 KEY8 REP KEY1 KEY9 CSB_SF 1 CSB VCC 8 DVDD PLAY (BUSY) KEY2 KEY10 SO_SF 2 DO HOLDB 7 DVDD DEC STOP KEY3 KEY4 KEY11 KEY12 DVDD VSS 3 WPB CLK 6 4 VSS DI 5 SCK_SF SI_SF VUP (CSB) VDN (SDATI) KEY5 KEY6 KEY7 KEY13 KEY14 KEY15 Serial Flash (1Mbit ~ 128Mbit) FusionChips Inc. Rev

13 7.2 PKG Dimension FusionChips Inc. Rev

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