High-Speed, Single-Supply, Rail-to-Rail OPERATIONAL AMPLIFIERS

Transcription

1 For most current data sheet and other product information, visit OPA233 OPA433 OPA433 OPA33 OPA233 OPA433 High-Speed, Single-Supply, Rail-to-Rail OPERATIONAL AMPLIFIERS MicroAmplifier Series FEATURES RAIL-TO-RAIL INPUT RAIL-TO-RAIL OUTPUT (within 0mV) WIDE BANDWIDTH: 44MHz HIGH SLEW RATE: 22V/µs LOW NOISE: nv/ Hz LOW THD+NOISE: % UNITY-GAIN STABLE MicroSIZE PACKAGES SINGLE, DUAL, AND QUAD DESCRIPTION OPA33 series rail-to-rail CMOS operational amplifiers are designed for low cost, miniature applications. They are optimized for low voltage, single-supply operation. Rail-to-rail input/output, low noise (nv/ Hz), and high speed operation (44MHz, 22V/µs) make them ideal for driving sampling analog-to-digital converters. They are also well suited for cell phone PA control loops and video processing (7Ω drive capability) as well as audio and general purpose applications. Single, dual, and quad versions have identical specifications for design flexibility. The OPA33 series operates on a single supply as low as 2.V with an input common-mode voltage range that SPICE Model available at APPLICATIONS CELL PHONE PA CONTROL LOOPS DRIVING A/D CONVERTERS VIDEO PROCESSING DATA ACQUISITION PROCESS CONTROL AUDIO PROCESSING COMMUNICATIONS ACTIVE FILTERS TEST EQUIPMENT extends 300mV beyond the supply rails. Output voltage swing is to within 0mV of the supply rails with a 0kΩ load. Dual and quad designs feature completely independent circuitry for lowest crosstalk and freedom from interaction. The single (OPA33) packages are the tiny -lead SOT- 23- surface mount and SO-8 surface mount. The dual (OPA233) comes in the miniature MSOP-8 surface mount and SO-8 surface mount. The quad (OPA433) packages are the space-saving SSOP-6 surface mount and SO-4 surface mount. All are specified from 40 C to +8 C and operate from C to +2 C. OPA433 OPA33 Out A 6 Out D NC In NC V+ In A +In A 2 3 A D 4 In D +In D Out V 2 OPA33 +In V V+ 3 4 SO-8 6 Output NC Out A In A +In A 2 3 OPA233 A B V+ Out B In B +V +In B In B Out B NC B C V +In C In C Out C NC +In 3 SOT-23-4 In V 4 SO-8, MSOP-8 +In B SSOP-6 (SO-4 package not shown) International Airport Industrial Park Mailing Address: PO Box 400, Tucson, AZ 8734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 8706 Tel: (20) 746- Twx: Internet: Cable: BBRCORP Telex: FAX: (20) Immediate Product Info: (800) SBOS Burr-Brown Corporation PDS-479B Printed in U.S.A. March, 999

2 SPECIFICATIONS: V S = 2.7V to.v At T A = +2 C, R L = kω connected to V S /2 and V OUT = V S /2, unless otherwise noted. Boldface limits apply over the specified temperature range, T A = 40 C to +8 C. V S = V. OPA33NA, UA OPA233EA, UA OPA433EA, UA PARAMETER CONDITION MIN TYP () MAX UNITS OFFSET VOLTAGE Input Offset Voltage V OS V S = V ±3 ±8 mv T A = 40 C to +8 C ±0 mv vs Temperature T A = 40 C to +8 C ± µv/ C vs Power Supply Rejection Ratio PSRR V S = 2.7V to.v, V CM = 0V 40 0 µv/v T A = 40 C to +8 C V S = 2.7V to.v, V CM = 0V 7 µv/v Channel Separation (dual, quad) dc 0. µv/v INPUT BIAS CURRENT Input Bias Current I B ±0. ±0 pa T A = 40 C to +8 C See Typical Curve Input Offset Current I OS ±0. ±0 pa NOISE Input Voltage Noise, f = 00Hz to 400kHz 4 µvrms Input Voltage Noise Density, f = 0kHz e n 7 nv/ Hz f = 00kHz nv/ Hz Current Noise Density, f = 0kHz i n 4 fa/ Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range V CM 0. (V+) + 0. V Common-Mode Rejection Ratio CMRR 0.V < V CM < (V+) 2.4V db V S = V, 0.V < V CM <.V db T A = 40 C to +8 C V S = V, 0.V < V CM <.V 8 db INPUT IMPEDANCE Differential Ω pf Common-Mode Ω pf OPEN-LOOP GAIN Open-Loop Voltage Gain A OL R L = 0kΩ, 0mV < V O < (V+) 0mV db T A = 40 C to +8 C R L = 0kΩ, 0mV < V O < (V+) 0mV 00 db R L = kω, 200mV < V O < (V+) 200mV db T A = 40 C to +8 C R L = kω, 200mV < V O < (V+) 200mV 00 db FREQUENCY RESPONSE C L = 00pF Gain-Bandwidth Product GBW G = 44 MHz Slew Rate SR G = 22 V/µs Settling Time, 0.% G = ±, 2V Step 0.22 µs 0.0% G = ±, 2V Step 0. µs Overload Recovery Time V IN G = V S 0. µs Total Harmonic Distortion + Noise THD+N R L = 600Ω, V O = 2.Vp-p (2), G =, f = khz % Differential Gain Error G = 2, R L = 600Ω, V O =.4V (3) 0.7 % Differential Phase Error G = 2, R L = 600Ω, V O =.4V (3) 0.7 deg OUTPUT Voltage Output Swing from Rail (4) V OUT R L = 0kΩ, A OL 00dB 0 0 mv T A = 40 C to +8 C R L = 0kΩ, A OL 00dB 0 mv R L = kω, A OL 00dB mv T A = 40 C to +8 C R L = kω, A OL 00dB 200 mv Output Current I OUT ±40 () ma Short-Circuit Current I SC ±80 ma Capacitive Load Drive C LOAD See Typical Curve POWER SUPPLY Operating Voltage Range V S T A = 40 C to +8 C 2.7. V Minimum Operating Voltage 2. V Quiescent Current (per amplifier) I Q I O = ma T A = 40 C to +8 C I O = 0 9 ma TEMPERATURE RANGE Specified Range C Operating Range +2 C Storage Range +2 C Thermal Resistance θ JA SOT C/W MSOP-8 Surface Mount 0 C/W SO-8 Surface Mount 0 C/W SSOP-6 Surface Mount 00 C/W SO-4 Surface Mount 00 C/W NOTES: () V S = +V. (2) V OUT = 0.2V to 2.7V. (3) NTSC signal generator used. See Figure 6 for test circuit. (4) Output voltage swings are measured between the output and power supply rails. () See typical performance curve, Output Voltage Swing vs Output Swing. OPA33, 233, 433 2

3 PIN CONFIGURATION Top View SO-4 ELECTROSTATIC DISCHARGE SENSITIVITY OPA433 Out A In A 2 A +In A 3 V+ 4 +In B B In B 6 D C Out D In D +In D V +In C In C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Out B 7 8 Out C ABSOLUTE MAXIMUM RATINGS () Supply Voltage....V Signal Input Terminals, Voltage (2)... (V ) 0.3V to (V+) + 0.3V Current (2)... 0mA Output Short-Circuit (3)... Continuous Operating Temperature... C to +2 C Storage Temperature... C to +2 C Junction Temperature... 0 C Lead Temperature (soldering, 0s) C NOTES: () Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Input terminals are diode-clamped to the power supply rails. Input signals that can swing more than 0.3V beyond the supply rails should be current-limited to 0mA or less. (3) Short circuit to ground, one amplifier per package. PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER () RANGE MARKING NUMBER (2) MEDIA Single OPA33NA -Lead SOT C to +8 C D3 OPA33NA/20 Tape and Reel " " " " " OPA33NA/3K Tape and Reel OPA33UA SO-8 Surface Mount C to +8 C OPA33UA OPA33UA Rails " " " " " OPA33UA/2K Tape and Reel Dual OPA233EA MSOP-8 Surface Mount C to +8 C E3 OPA233EA/20 Tape and Reel " " " " " OPA233EA/2K Tape and Reel OPA233UA SO-8 Surface Mount C to +8 C OPA233UA OPA233UA Rails " " " " " OPA233UA/2K Tape and Reel Quad OPA433EA SSOP-6 Surface Mount C to +8 C OPA433EA OPA433EA/20 Tape and Reel " " " " " OPA433EA/2K Tape and Reel OPA433UA SO-4 Surface Mount C to +8 C OPA433UA OPA433UA Rails " " " " " OPA433UA/2K Tape and Reel NOTES: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 200 devices per reel). Ordering 200 pieces of OPA233EA/2K will get a single 200-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3 OPA33, 233, 433

4 TYPICAL PERFORMANCE CURVES At T A = +2 C, V S = +V, and R L = kω connected to V S /2, unless otherwise noted. Voltage Gain (db) OPEN-LOOP GAIN/PHASE vs FREQUENCY 0 4 φ 90 G k 0k 00k M 0M 00M Frequency (Hz) Phase ( ) PSRR, CMRR (db) POWER SUPPLY AND COMMON-MODE REJECTION RATIO vs FREQUENCY PSRR CMRR (V S = +V V CM = 0.V to.v) k 0k 00k M 0M Frequency (Hz) 00k INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY 0k 40 CHANNEL SEPARATION vs FREQUENCY Voltage Noise (nv Hz) 0k k Current Noise k 00 Voltage Noise k 0k 00k M 0M Frequency (Hz) Current Noise (fa Hz) Channel Separation (db) Dual and Quad 70 Versions k 0k 00k M Frequency (Hz) 0M THD+N (%) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY G = 00, 3Vp-p (V O = V to 4V) G = 0, 3Vp-p (V O = V to 4V) G =, 3Vp-p (V O = V to 4V) Input goes through transition region G =, 2.Vp-p (V O = 0.2V to 2.7V) Input does NOT go through transition region k 0k 00k Frequency (Hz) R L = 600Ω Harmonic Distortion (%) ( 40dBc) 0. ( 60dBc) 0.0 ( 80dBc) 0.00 ( 00dBc) ( 20dBc) HARMONIC DISTORTION + NOISE vs FREQUENCY G = V O = 2.Vp-p R L = 600Ω 3rd Harmonic 2nd Harmonic k 0k 00k M Frequency (Hz) OPA33, 233, 433 4

5 TYPICAL PERFORMANCE CURVES (CONT) At T A = +2 C, V S = +V, and R L = kω connected to V S /2, unless otherwise noted. Differential Gain (%) Differential Phase ( ) DIFFERENTIAL GAIN/PHASE vs RESISTIVE LOAD Gain Phase G = 2 V O =.4V NTSC Signal Generator See Figure 6 for test circuit. Open-Loop Gain (db) OPEN-LOOP GAIN vs TEMPERATURE R R L = kω L = 0kΩ R L = 600Ω Resistive Load (Ω) Temperature ( C) 90 COMMON-MODE AND POWER SUPPLY REJECTION RATIO vs TEMPERATURE 0 40 SLEW RATE vs TEMPERATURE 3 CMRR (db) PSRR CMRR, V S = V (V CM = 0.V to +.V) PSRR (db) Slew Rate (V/µs) Negative Slew Rate Positive Slew Rate Temperature ( C) Temperature ( C) Quiescent Current (ma) QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE I SC +I SC I Q Short-Circuit Current (ma) Quiescent Current (ma) QUIESCENT CURRENT vs SUPPLY VOLTAGE Per Amplifier Temperature ( C) Supply Voltage (V) OPA33, 233, 433

6 TYPICAL PERFORMANCE CURVES (CONT) At T A = +2 C, V S = +V, and R L = kω connected to V S /2, unless otherwise noted. k INPUT BIAS CURRENT vs TEMPERATURE. INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE Input Bias Current (pa) 00 0 Input Bias Current (pa) Temperature ( C) Common-Mode Voltage (V) Output Impedance (Ω) CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY G = 00 G = 0 G = Output Voltage (Vp-p) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY V S =.V V S = 2.7V Maximum output voltage without slew rate-induced distortion k 0k 00k M 0M 00M Frequency (Hz) 0 00k M 0M Frequency (Hz) 00M Output Voltage (V) V+ (V+) (V+) 2 (V )+2 (V )+ OUTPUT VOLTAGE SWING vs OUTPUT CURRENT +2 C +2 C C +2 C +2 C Depending on circuit configuration (including closed-loop gain) performance may be degraded in shaded region. C Open-Loop Gain (db) OPEN-LOOP GAIN vs OUTPUT VOLTAGE SWING I OUT = 20µA I OUT = 2.mA I OUT = 4.2mA (V ) 0 ±0 ±20 ±30 ±40 Output Current (ma) Output Voltage Swing from Supply Rails (mv) OPA33, 233, 433 6

7 TYPICAL PERFORMANCE CURVES (CONT) At T A = +2 C, V S = +V, and R L = kω connected to V S /2, unless otherwise noted. Percent of Units (%) OFFSET VOLTAGE PRODUCTION DISTRIBUTION Typical production distribution of packaged units. Percent of Amplifiers (%) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Typical production distribution of packaged units Offset Voltage (mv) Offset Voltage Drift (µv/ C) 80 SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 0 SETTLING TIME vs CLOSED-LOOP GAIN Overshoot (%) G = G = SMALL-SIGNAL STEP RESPONSE C L = 00pF LARGE-SIGNAL STEP RESPONSE C L = 00pF 0mV/div V/div G = ±0 Settling Time (µs) 0.0% k 0k 00k M 0.% 0. ± ±0 ±00 Load Capacitance (pf) Closed-Loop Gain (V/V) 00ns/div 200ns/div 7 OPA33, 233, 433

8 APPLICATIONS INFORMATION OPA33 series op amps are fabricated on a state-of-the-art 0.6 micron CMOS process. They are unity-gain stable and suitable for a wide range of general purpose applications. Rail-to-rail input/output make them ideal for driving sampling A/D converters. They are well suited for controlling the output power in cell phones. These applications often require high speed and low noise. In addition, the OPA33 series offers a low cost solution for general purpose and consumer video applications (7Ω drive capability). Excellent ac performance makes the OPA33 series well suited for audio applications. Their bandwidth, slew rate, low noise (nv/ Hz), low THD (0.0006%), and small package options are ideal for these applications. The class AB output stage is capable of driving 600Ω loads connected to any point between V+ and ground. Rail-to-rail input and output swing significantly increases dynamic range, especially in low voltage supply applications. Figure shows the input and output waveforms for V IN V OUT V 0 V 0 V S = +, G = +, R L = kω FIGURE. Rail-to-Rail Input and Output..2V/div the OPA33 in unity-gain configuration. Operation is from a single +V supply with a kω load connected to V S /2. The input is a Vp-p sinusoid. Output voltage is approximately 4.9Vp-p. Power supply pins should be bypassed with 0.0µF ceramic capacitors. OPERATING VOLTAGE OPA33 series op amps are fully specified from +2.7V to +.V. However, supply voltage may range from +2.V to +.V. Parameters are guaranteed over the specified supply range a unique feature of the OPA33 series. In addition, many specifications apply from 40 C to +8 C. Most behavior remains virtually unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltages or temperature are shown in the typical performance curves. RAIL-TO-RAIL INPUT The guaranteed input common-mode voltage range of the OPA33 series extends 00mV beyond the supply rails. This is achieved with a complementary input stage an N-channel input differential pair in parallel with a P-channel differential pair (see Figure 2). The N-channel pair is active for input voltages close to the positive rail, typically (V+).8V to 00mV above the positive supply, while the P-channel pair is on for inputs from 00mV below the negative supply to approximately (V+).8V. There is a small transition region, typically (V+) 2V to (V+).6V, in which both pairs are on. This 400mV transition region can vary ±400mV with process variation. Thus, the transition region (both input stages on) can range from (V+) 2.4V to (V+) 2.0V on the low end, up to (V+).6V to (V+).2V on the high end. V+ Reference Current V IN + V IN V BIAS Class AB Control Circuitry V O V BIAS2 V (Ground) FIGURE 2. Simplified Schematic. OPA33, 233, 433 8

9 A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class AB output stage. Normally, input bias current is approximately 00fA. However, large inputs (greater than 300mV beyond the supply rails) can turn on the OPA33 s input protection diodes, causing excessive current to flow in or out of the input pins. Momentary voltages greater than 300mV beyond the power supply can be tolerated if the current on the input pins is limited to 0mA. This is easily accomplished with an input resistor as shown in Figure 3. Many input signals are inherently current-limited to less than 0mA, therefore, a limiting resistor is not required. FEEDBACK CAPACITOR IMPROVES RESPONSE For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a feedback capacitor across the feedback resistor, R F, as shown in Figure 4. This capacitor compensates for the zero created by the feedback network impedance and the OPA33 s input capacitance (and any parasitic layout capacitance). The effect becomes more significant with higher impedance networks. C F R IN R F V IN V+ V+ I OVERLOAD 0mA max OPAx33 V OUT C IN V IN kω R IN C IN = R F C F OPA33 C L V OUT C IN FIGURE 3. Input Current Protection for Voltages Exceeding the Supply Voltage. Where C IN is equal to the OPA33 s input capacitance (approximately 9pF) plus any parastic layout capacitance. RAIL-TO-RAIL OUTPUT A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For light resistive loads (>0kΩ), the output voltage swing is typically ten millivolts from the supply rails. With heavier resistive loads (600Ω to 0kΩ), the output can swing to within a few tens of millivolts from the supply rails and maintain high open-loop gain. See the typical performance curves Output Voltage Swing vs Output Current and Open-Loop Gain vs Output Voltage. CAPACITIVE LOAD AND STABILITY OPA33 series op amps can drive a wide range of capacitive loads. However, all op amps under certain conditions may become unstable. Op amp configuration, gain, and load value are just a few of the factors to consider when determining stability. An op amp in unity gain configuration is the most susceptible to the effects of capacitive load. The capacitive load reacts with the op amp s output impedance, along with any additional load resistance, to create a pole in the small-signal response which degrades the phase margin. In unity gain, OPA33 series op amps perform well with large capacitive loads. Increasing gain enhances the amplifier s ability to drive more capacitance. The typical performance curve Small-Signal Overshoot vs Capacitive Load shows performance with a kω resistive load. Increasing load resistance improves capacitive load drive capability. FIGURE 4. Feedback Capacitor Improves Dynamic Performance. It is suggested that a variable capacitor be used for the feedback capacitor since input capacitance may vary between op amps and layout capacitance is difficult to determine. For the circuit shown in Figure 4, the value of the variable feedback capacitor should be chosen so that the input resistance times the input capacitance of the OPA33 (typically 9pF) plus the estimated parasitic layout capacitance equals the feedback capacitor times the feedback resistor: R IN C IN = R F C F where C IN is equal to the OPA33 s input capacitance (sum of differential and common-mode) plus the layout capacitance. The capacitor can be varied until optimum performance is obtained. DRIVING A/D CONVERTERS OPA33 series op amps are optimized for driving medium speed (up to 00kHz) sampling A/D converters. However, they also offer excellent performance for higher speed converters. The OPA33 series provides an effective means of buffering the A/D s input capacitance and resulting charge injection while providing signal gain. For applications requiring high accuracy, the OPA30 series is recommended. 9 OPA33, 233, 433

10 Figure shows the OPA33 driving an ADS786. The ADS786 is a dual, 2-bit, 00kHz sampling converter in the small SSOP-24 package. When used with the miniature package options of the OPA33 series, the combination is ideal for space-limited and low power applications. For further information consult the ADS786 data sheet. OUTPUT IMPEDANCE The low frequency open-loop output impedance of the OPA33 s common-source output stage is approximately kω. When the op amp is connected with feedback, this value is reduced significantly by the loop gain of the op amp. For example, with 22dB of open-loop gain, the output impedance is reduced in unity-gain to less than 0.00Ω. For each decade rise in the closed-loop gain, the loop gain is reduced by the same amount which results in a ten-fold increase in output impedance (see the typical performance curve, Output Impedance vs Frequency ). At higher frequencies, the output impedance will rise as the open-loop gain of the op amp drops. However, at these frequencies the output also becomes capacitive due to parasitic capacitance. This prevents the output impedance from becoming too high, which can cause stability problems when driving capacitive loads. As mentioned previously, the OPA33 has excellent capacitive load drive capability for an op amp with its bandwidth. VIDEO LINE DRIVER Figure 6 shows a circuit for a single supply, G = 2 composite video line driver. The synchronized outputs of a composite video line driver extend below ground. As shown, the input to the op amp should be ac-coupled and shifted positively to provide adequate signal swing to account for these negative signals in a single-supply configuration. The input is terminated with a 7Ω resistor and ac-coupled with a 47µF capacitor to a voltage divider that provides the dc bias point to the input. In Figure 6, this point is approximately (V ) +.7V. Setting the optimal bias point requires some understanding of the nature of composite video signals. For best performance, one should be careful to avoid the distortion caused by the transition region of the OPA33 s complementary input stage. Refer to the discussion of rail-to-rail input. C B 2kΩ 2kΩ +V V IN B 2 4 /4 3 OPA433 0.µF 0.µF C B kΩ V IN B0 2kΩ V IN A 2kΩ 6 /4 OPA C A 2kΩ /4 OPA CH B+ CH B CH B0+ CH B0 CH A+ CH A CH A0+ CH A0 REF IN REF OUT +V D +V A Serial Data A Serial Data B BUSY CLOCK CS ADS786 RD CONVST A0 M0 M Serial Interface C A0 DGND AGND 2kΩ 2kΩ 2 V IN A0 /4 OPA433 4 V IN = 0V to 2.4V for 0V to 4.9V output. Choose C B, C B0, C A, C A0 to filter high frequency noise. FIGURE. OPA433 Driving Sampling A/D Converter. OPA33, 233, 433 0

11 R G kω R F kω C 220µF +V + 0.µF 0µF C 4 0.µF 7 Video In C 2 47µF R 7Ω R 2 kω R 3 kω OPA33 4 R 4 kω 6 +V (pin 7) C 000µF R OUT Cable R L V OUT C 3 0µF FIGURE 6. Single-Supply Video Line Driver. +V 0kΩ (2.V) 8 R G REF V 4 R 00kΩ R 2 2kΩ /2 OPA233 R 3 2kΩ R 4 00kΩ /2 OPA233 V OUT G = + 200kΩ R G R L 0kΩ FIGURE 7. Two Op-Amp Instrumentation Amplifier With Improved High Frequency Common-Mode Rejection. <pf (prevents gain peaking) 0MΩ R 0.kΩ +V +2.V λ OPA33 V O C 830pF C 2 270pF OPA33 V OUT FIGURE 8. Transimpedance Amplifier. V IN R kΩ 2.V R L 20kΩ C 4.7µF +2.V FIGURE 0. 0kHz High-Pass Filter. R 2.74kΩ R 2 9.6kΩ OPA33 V OUT V IN C 2 nf 2.V R L 20kΩ FIGURE 9. 0kHz Low-Pass Filter. OPA33, 233, 433

12 PACKAGE OPTION ADDENDUM 4-Sep-208 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan OPA233EA/20 ACTIVE VSSOP DGK 8 20 Green (RoHS OPA233EA/20G4 ACTIVE VSSOP DGK 8 20 Green (RoHS OPA233EA/2K ACTIVE VSSOP DGK Green (RoHS OPA233EA/2KG4 ACTIVE VSSOP DGK Green (RoHS OPA233UA ACTIVE SOIC D 8 7 Green (RoHS OPA233UA/2K ACTIVE SOIC D Green (RoHS OPA233UA/2KG4 ACTIVE SOIC D Green (RoHS OPA233UAG4 ACTIVE SOIC D 8 7 Green (RoHS OPA33NA/20 ACTIVE SOT-23 DBV 20 Green (RoHS OPA33NA/3K ACTIVE SOT-23 DBV 3000 Green (RoHS OPA33NA/3KG4 ACTIVE SOT-23 DBV 3000 Green (RoHS OPA33UA ACTIVE SOIC D 8 7 Green (RoHS OPA33UA/2K ACTIVE SOIC D Green (RoHS OPA33UAG4 ACTIVE SOIC D 8 7 Green (RoHS OPA433EA/20 ACTIVE SSOP DBQ 6 20 Green (RoHS OPA433EA/20G4 ACTIVE SSOP DBQ 6 20 Green (RoHS OPA433UA ACTIVE SOIC D 4 0 Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAUAG Level-2-260C- YEAR -40 to 8 E3 CU NIPDAUAG Level-2-260C- YEAR -40 to 8 E3 CU NIPDAUAG Level-2-260C- YEAR -40 to 8 E3 CU NIPDAUAG Level-2-260C- YEAR -40 to 8 E3 CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 233UA CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 233UA CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 233UA CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 233UA CU NIPDAU Level-2-260C- YEAR -40 to 8 D3 CU NIPDAU Level-2-260C- YEAR -40 to 8 D3 CU NIPDAU Level-2-260C- YEAR -40 to 8 D3 CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 33UA CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 33UA CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 33UA CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 433EA CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA 433EA CU NIPDAU Level-2-260C- YEAR OPA433UA Device Marking (4/) Samples Addendum-Page

13 PACKAGE OPTION ADDENDUM 4-Sep-208 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan OPA433UA/2K ACTIVE SOIC D Green (RoHS OPA433UAG4 ACTIVE SOIC D 4 0 Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/) CU NIPDAU Level-2-260C- YEAR -40 to 8 OPA433UA CU NIPDAU Level-2-260C- YEAR OPA433UA Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 0 RoHS substances, including the requirement that RoHS substance do not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=000ppm threshold. Antimony trioxide based flame retardants must also meet the <=000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

14 PACKAGE MATERIALS INFORMATION -Sep-208 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant OPA233EA/20 VSSOP DGK Q OPA233EA/2K VSSOP DGK Q OPA233UA/2K SOIC D Q OPA33NA/20 SOT-23 DBV Q3 OPA33NA/3K SOT-23 DBV Q3 OPA33UA/2K SOIC D Q OPA433EA/20 SSOP DBQ Q OPA433UA/2K SOIC D Q Pack Materials-Page

15 PACKAGE MATERIALS INFORMATION -Sep-208 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA233EA/20 VSSOP DGK OPA233EA/2K VSSOP DGK OPA233UA/2K SOIC D OPA33NA/20 SOT-23 DBV OPA33NA/3K SOT-23 DBV OPA33UA/2K SOIC D OPA433EA/20 SSOP DBQ OPA433UA/2K SOIC D Pack Materials-Page 2

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17 SCALE PACKAGE OUTLINE DBV000A SOT mm max height SMALL OUTLINE TRANSISTOR C C PIN INDEX AREA.7.4 B A.4 MAX.9 2X X C A B 4 (.) 0. TYP GAGE PLANE 0.22 TYP TYP 0.6 TYP 0.3 SEATING PLANE /C 04/207 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y4.M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-78.

18 DBV000A EXAMPLE BOARD LAYOUT SOT mm max height SMALL OUTLINE TRANSISTOR X (.) PKG X (0.6) 2 SYMM (.9) 2X (0.9) 3 4 (R0.0) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) 0.07 MIN ARROUND SOLDER MASK DEFINED SOLDER MASK DETAILS /C 04/207 NOTES: (continued) 4. Publication IPC-73 may have alternate designs.. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

19 DBV000A EXAMPLE STENCIL DESIGN SOT mm max height SMALL OUTLINE TRANSISTOR X (0.6) X (.) PKG 2X(0.9) 2 SYMM (.9) 3 4 (R0.0) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.2 mm THICK STENCIL SCALE:X /C 04/207 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-72 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design.

20 SCALE PACKAGE OUTLINE DBV000A SOT mm max height SMALL OUTLINE TRANSISTOR C C PIN INDEX AREA.7.4 B A.4 MAX.9 2X X C A B 4 (.) 0. TYP GAGE PLANE 0.22 TYP TYP 0.6 TYP 0.3 SEATING PLANE /C 04/207 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y4.M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-78.

21 DBV000A EXAMPLE BOARD LAYOUT SOT mm max height SMALL OUTLINE TRANSISTOR X (.) PKG X (0.6) 2 SYMM (.9) 2X (0.9) 3 4 (R0.0) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) 0.07 MIN ARROUND SOLDER MASK DEFINED SOLDER MASK DETAILS /C 04/207 NOTES: (continued) 4. Publication IPC-73 may have alternate designs.. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

22 DBV000A EXAMPLE STENCIL DESIGN SOT mm max height SMALL OUTLINE TRANSISTOR X (0.6) X (.) PKG 2X(0.9) 2 SYMM (.9) 3 4 (R0.0) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.2 mm THICK STENCIL SCALE:X /C 04/207 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-72 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design.

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28 SCALE DBQ006A PACKAGE OUTLINE SSOP -.7 mm max height SHRINK SMALL-OUTLINE PACKAGE SEATING PLANE C A TYP [ ] PIN ID AREA 6 4X.020 [0.63].004 [0.] C [ ] NOTE 3 2X.7 [4.4] 8 B.0-.7 [ ] NOTE 4 9 6X [ ].007 [0.7] C A B.069 MAX [.7] TYP [ ] SEE DETAIL A.00 [0.2] GAGE PLANE [ ] (.04 ) [.04] DETAIL A TYPICAL [ ] /A 03/204 NOTES:. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y4.M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed.006 inch, per side. 4. This dimension does not include interlead flash.. Reference JEDEC registration MO-37, variation AB.

29 DBQ006A EXAMPLE BOARD LAYOUT SSOP -.7 mm max height SHRINK SMALL-OUTLINE PACKAGE 6X (.063) [.6] SYMM 6 SEE DETAILS 6X (.06 ) [0.4] 4X (.020 ) [0.63] 8 9 (.23) [.4] LAND PATTERN EXAMPLE SCALE:8X METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL.002 MAX [0.0] ALL AROUND NON SOLDER MASK DEFINED.002 MIN [0.0] ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS /A 03/204 NOTES: (continued) 6. Publication IPC-73 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

30 DBQ006A EXAMPLE STENCIL DESIGN SSOP -.7 mm max height SHRINK SMALL-OUTLINE PACKAGE 6X (.063) [.6] SYMM 6 6X (.06 ) [0.4] SYMM 4X (.020 ) [0.63] 8 9 (.23) [.4] SOLDER PASTE EXAMPLE BASED ON.00 INCH [0.27 MM] THICK STENCIL SCALE:8X /A 03/204 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-72 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

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