Low Noise, Precision Instrumentation Amplifier AMP01*

Transcription

1 a FEATURES Low Offset Voltage: V Max Very Low Offset Voltage Drift:. V/ C Max Low Noise:. V p-p (. Hz to Hz) Excellent Output Drive: V at ma Capacitive Load Stability: to F Gain Range:. to, Excellent Linearity: -Bit at G = High CMR: db min (G = ) Low Bias Current: na Max May Be Configured as a Precision Op Amp Output-Stage Thermal Shutdown Available in Die Form GENERAL DESCRIPTION The AMP is a monolithic instrumentation amplifier designed for high-precision data acquisition and instrumentation applications. The design combines the conventional features of an instrumentation amplifier with a high current output stage. The output remains stable with high capacitance loads ( µf), a unique ability for an instrumentation amplifier. Consequently, the AMP can amplify low level signals for transmission through long cables without requiring an output buffer. The output stage may be configured as a voltage or current generator. Input offset voltage is very low ( µv), which generally eliminates the external null potentiometer. Temperature changes have minimal effect on offset; TCV IOS is typically. µv/ C. Excellent low-frequency noise performance is achieved with a minimal compromise on input protection. Bias current is very low, less than na over the military temperature range. High common-mode rejection of db, -bit linearity at a gain of, and ma peak output current are achievable simultaneously. This combination takes the instrumentation amplifier one step further towards the ideal amplifier. AC performance complements the superb dc specifications. The AMP slews at. V/µs into capacitive loads of up to nf, settles in µs to.% at a gain of, and boasts a healthy MHz gain-bandwidth product. These features make the AMP ideal for high speed data acquisition systems. Gain is set by the ratio of two external resistors over a range of. to,. A very low gain temperature coefficient of ppm/ C is achievable over the whole gain range. Output voltage swing is guaranteed with three load resistances; Ω, Ω, and kω. Loaded with Ω, the output delivers ±. V minimum. A thermal shutdown circuit prevents destruction of the output transistors during overload conditions. The AMP can also be configured as a high performance operational amplifier. In many applications, the AMP can be used in place of op amp/power-buffer combinations. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Low Noise, Precision Instrumentation Amplifier AMP* PIN CONFIGURATIONS -Lead Cerdip V OOS NULL V OOS NULL V IOS NULL V IOS NULL TEST PIN* OUTPUT AMP V OP V OP TOP VIEW (Not to Scale) *MAKE NO ELECTRICAL CONNECTION NC V OOS NULL NC V OOS NULL NC TEST PIN* NC NC = NO CONNECT AMP BTC/ -Terminal LCC NC NC V IOS NULL AMP TOP VIEW (Not to Scale) REF OUT NC V OP NC *MAKE NO ELECTRICAL CONNECTION -Lead SOIC TEST PIN* TEST PIN* V OOS NULL V OOS NULL AMP V IOS NULL V IOS NULL TEST PIN* TOP VIEW (Not to Scale) OUTPUT V OP V OP *MAKE NO ELECTRICAL CONNECTION V IOS NULL NC V OP NC *Protected under U.S. Patent Numbers,, and,,. One Technology Way, P.O. Box, Norwood, MA -, U.S.A. Tel: /- World Wide Web Site: Fax: /- Analog Devices, Inc.,

2 AMP SPECIFICATIONS ELECTRICAL CHARACTERISTICS V S = V, = k, R L = k, T A = C, unless otherwise noted) AMPA AMPB Parameter Symbol Conditions Min Typ Max Min Typ Max Units OFFSET VOLTAGE Input Offset Voltage V IOS T A = C µv C T A C µv Input Offset Voltage Drift TCV IOS C T A C.... µv/ C Output Offset Voltage V OOS T A = C mv C T A C mv Output Offset Voltage Drift TCV OOS = C T A C µv/ C Offset Referred to Input PS = db vs. Positive Supply G = db = V to V G = db G = db C T A C G = db G = db G = db G = db Offset Referred to Input PS = db vs. Negative Supply G = db = V to V G = db G = db C T A C G = db G = db G = db G = db Input Offset Voltage Trim Range V S = ±. V to ± V ± ± mv Output Offset Voltage Trim Range V S = ±. V to ± V ± ± mv INPUT CURRENT Input Bias Current I B T A = C na C T A C na Input Bias Current Drift TCI B C T A C pa/ C Input Offset Current I OS T A = C.... na C T A C.... na Input Offset Current Drift TCI OS C T A C pa/ C INPUT Input Resistance R IN Differential, G = GΩ Differential, G GΩ Common Mode, G = GΩ Input Voltage Range IVR T A = C ±. ±. V C T A C ±. ±. V Common-Mode Rejection CMR V CM = ± V, kω Source Imbalance G = db G = db G = db G = db C T A C G = db G = db G = db G = db NOTES V IOS and V OOS nulling has minimal affect on TCV IOS and TCV OOS respectively. Refer to section on common-mode rejection. Specifications subject to change without notice.

3 ELECTRICAL CHARACTERISTICS AMPE AMPF/G Parameter Symbol Conditions Min Typ Max Min Typ Max Units OFFSET VOLTAGE Input Offset Voltage V IOS T A = C µv T MIN T A T MAX µv Input Offset Voltage Drift TCV IOS T MIN T A T MAX.... µv/ C Output Offset Voltage V OOS T A = C mv T MIN T A T MAX mv Output Offset Voltage Drift TCV OOS = T MIN T A T MAX µv/ C Offset Referred to Input PS = db vs. Positive Supply G = db = V to V G = db G = db T MIN T A T MAX G = db G = db G = db G = db Offset Referred to Input PS = db vs. Negative Supply G = db = V to V G = db G = db T MIN T A T MAX G = db G = db G = db G = db Input Offset Voltage Trim Range V S = ±. V to ± V ± ± mv Output Offset Voltage Trim Range V S = ±. V to ± V ± ± mv INPUT CURRENT Input Bias Current I B T A = C mv T MIN T A T MAX mv Input Bias Current Drift TCI B T MIN T A T MAX pa/ C Input Offset Current I OS T A = C.... mv T MIN T A T MAX.... mv Input Offset Current Drift TCI OS T MIN T A T MAX pa/ C INPUT Input Resistance R IN Differential, G = GΩ Differential, G GΩ Common Mode, G = GΩ Input Voltage Range IVR T A = C ±. ±. V T MIN T A T MAX ±. ±. V Common-Mode Rejection CMR V CM = ± V, kω Source Imbalance G = db G = db G = db G = db T MIN T A T MAX G = db G = db G = db G = db NOTES Sample tested. V IOS and V OOS nulling has minimal affect on TCV IOS and TCV OOS, respectively. Refer to section on common-mode rejection. Specifications subject to change without notice. (@ V S = V, = k, R L = k, T A = C, C T A C for E, F grades, C T A C for G grade, unless otherwise noted) AMP

4 AMP ELECTRICAL CHARACTERISTICS V S = V, = k, R L = k, T A = C, unless otherwise noted) AMPA/E AMPB/F/G Parameter Symbol Conditions Min Typ Max Min Typ Max Units GAIN Gain Equation Accuracy G =.... % Accuracy Measured from G = to Gain Range G. k. k V/V Nonlinearity G =.... % G =.. % G =.. % G =.. % Temperature Coefficient G TC G, ppm C OUTPUT RATING Output Voltage Swing V OUT R L = kω ±. ±. ±. ±. V R L = Ω ±. ±. ±. ±. V R L = Ω ±. ±. ±. ±. V R L = kω Over Temp. ±. ±. ±. ±. V R L = Ω ±. ±. ±. ±. V Positive Current Limit Output-to-Ground Short ma Negative Current Limit Output-to-Ground Short ma Capacitive Load Stability G No Oscillations.. µf Thermal Shutdown Temperature Junction Temperature C NOISE Voltage Density, RTI e n f O = khz e n G = nv/ Hz e n G = nv/ Hz e n G = nv/ Hz e n G = nv/ Hz Noise Current Density, RTI i n f O = khz, G =.. pa/ Hz Input Noise Voltage e n p-p. Hz to Hz e n p-p G =.. µv p-p e n p-p G =.. µv p-p e n p-p G =.. µv p-p e n p-p G = µv p-p Input Noise Current i n p-p. Hz to Hz, G = pa p-p DYNAMIC RESPONSE Small-Signal G = khz Bandwidth ( db) BW G = khz G = khz G = khz Slew Rate S =.... V/µs Settling Time t S To.%, V step G = µs G = µs G = µs G = µs NOTES Guaranteed by design. Gain tempco does not include the effects of gain and scale resistor tempco match. C T A C for A/B grades, C T A C for E/F grades, C T A C for G grades. Specifications subject to change without notice.

5 ELECTRICAL CHARACTERISTICS V S = V, = k, R L = k, T A = C, unless otherwise noted) AMPA/E AMPB/F/G Parameter Symbol Conditions Min Typ Max Min Typ Max Units INPUT Input Resistance R IN kω Input Current I IN Referenced to µa Voltage Range (Note ).. V INPUT Input Resistance R IN kω Input Current I IN Referenced to µa Voltage Range (Note ).. V Gain to Output V/V POWEUPPLY C T A C for E/F Grades, C T A C for A/B Grades Supply Voltage Range V S V linked to V OP ±. ± ±. ± V V S V linked to V OP ±. ± ±. ± V Quiescent Current I Q V linked to V OP.... ma I Q V linked to V OP.... ma NOTE Guaranteed by design. Specifications subject to change without notice. ORDERING GUIDE Model Temperature Range Package Description Package Option AMPAX C to C -Lead Cerdip Q- AMPAX/C C to C -Lead Cerdip Q- AMPBTC/C C to C -Terminal LCC E-A AMPBX C to C -Lead Cerdip Q- AMPBX/C C to C -Lead Cerdip Q- AMPEX C to C -Lead Cerdip Q- AMPFX C to C -Lead Cerdip Q- AMPGBC Die AMPGS C to C -Lead SOIC R- AMPGS-REEL C to C " Tape and Reel R- AMPNBC Die -VA* C to C -Lead Cerdip Q- -A* C to C -Terminal LCC E-A -VA* C to C -Lead Cerdip Q- *Standard military drawing available. DICE CHARACTERISTICS Die Size.. inch,, sq. mils (.. mm,. sq. mm) AMP... PUT. V OOS NULL. V OOS NULL. TEST PIN*... OUTPUT. (OUTPUT)... (OUTPUT)... V IOS NULL. V IOS NULL. PUT * MAKE NO ELECTRICAL CONNECTION

6 AMP WAFER TEST LIMITS V S = V, = k, R L = k, T A = C, unless otherwise noted) AMPNBC AMPGBC Parameter Symbol Conditions Limit Limit Units Input Offset Voltage V IOS µv max Output Offset Voltage V OOS mv max Offset Referred to Input PSR = V to V db min vs. Positive Supply G = db min G = db min G = db min G = db min Offset Referred to Input PSR = V to V db min vs. Negative Supply G = db min G = db min G = db min G = db min Input Bias Current I B na max Input Offset Current I OS na max Input Voltage Range IVuaranteed by CMR Tests ± ± V min Common Mode Rejection CMR V CM = ± V db min G = db min G = db min G = db min G = db min Gain Equation Accuracy G =.. % max Output Voltage Swing V OUT R L = kω ± ± V min V OUT R L = Ω ± ± V min V OUT R L = Ω ±. ±. V min Output Current Limit Output to Ground Short ± ± ma min Output Current Limit Output to Ground Short ± ± ma max Quiescent Current I Q V Linked to V OP.. ma max V Linked to V OP.. ma max NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. V IOS NULL V OP A OUTPUT Q Q V OP R.k A AIN A R.k CALE R.k V OOS NULL R.k Figure. Simplified Schematic CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AMP features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

7 ELECTRICAL CHARACTERISTICS V S = V, = k, R L = k, T A = C, unless otherwise noted) AMP AMPNBC AMPGBC Parameter Symbol Conditions Typical Typical Units Input Offset Voltage Drift TCV IOS.. µv/ C Output Offset Voltage Drift TCV OOS = µv/ C Input Bias Current Drift TCI B pa/ C Input Offset Current Drift TCI OS pa/ C Nonlinearity G =.. % Voltage Noise Density e n G = f O = khz nv/ Hz Current Noise Density i n G = f O = khz.. pa/ Hz Voltage Noise e n p-p G =. Hz to Hz.. µv p-p Current Noise i n p-p G = pa p-p. Hz to Hz Small-Signal Bandwidth ( db) BW G = khz Slew Rate S =.. V/µs Settling Time t S To.%, V Step G = µs NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

8 AMP Typical Performance Characteristics INPUT OFFSET VOLTAGE V V S = V TEMPERATURE C Figure. Input Offset Voltage vs. Temperature INPUT OFFSET VOLTAGE V T A = C UNIT NO. POWEUPPLY VOLTAGE Volts Figure. Input Offset Voltage vs. Supply Voltage OUTPUT OFFSET VOLTAGE mv V S = V TEMPERATURE C Figure. Output Offset Voltage vs. Temperature OUTPUT OFFSET VOLTAGE CHANGE mv T A = C. POWEUPPLY VOLTAGE Volts Figure. Output Offset Voltage Change vs. Supply Voltage INPUT BIAS CURRENT na V S = V TEMPERATURE C Figure. Input Bias Current vs. Temperature INPUT BIAS CURRENT na T A = C. POWEUPPLY VOLTAGE Volts Figure. Input Bias Current vs. Supply Voltage INPUT OFFSET CURRENT na V S = V COMMON-MODE REJECTION db V S = V T A = C COMMON-MODE REJECTION db V CM = V p-p V S = V T A = C G = G = G = G =. TEMPERATURE C Figure. Input Offset Current vs. Temperature k k VOLTAGE GAIN G Figure. Common-Mode Rejection vs. Voltage Gain k k k FREQUENCY Hz Figure. Common-Mode Rejection vs. Frequency

9 AMP COMMON-MODE INPUT VOLTAGE Volts V DM = V S = V V S = V V S = V TEMPERATURE C Figure. Common-Mode Voltage Range vs. Temperature POWEUPPLY REJECTION db G = V S = V T A = C V S = V G = G = G = k k k FREQUENCY Hz Figure. Positive PSR vs. Frequency POWEUPPLY REJECTION db G = G = G = G = V S = V T A = C V S = V k k k FREQUENCY Hz Figure. Negative PSR vs. Frequency OUITPUT VOLTAGE Volts V S = V k LOAD RESISTANCE k Figure. Maximum Output Voltage vs. Load Resistance PEAK-TO-PEAK AMPLITUDE Volts V S = V R L = k k k k M FREQUENCY Hz Figure. Maximum Output Swing vs. Frequency OUTPUT IMPEDANCE... V S = V I OUT = ma p-p G = G =. k k k M FREQUENCY Hz Figure. Closed-Loop Output Impedance vs. Frequency VOLTAGE GAIN db G = G = G = G = V S = V T A = C TOTAL HARMONIC DISTORTION % V S = V R L = V OUT = V p-p G = G = G = G = TOTAL HARMONIC DISTORTION %.. V S = V G = f = khz V OUT = V p-p k k k M FREQUENCY Hz Figure. Closed-Loop Voltage Gain vs. Frequency k FREQUENCY Hz k Figure. Total Harmonic Distortion vs. Frequency k LOAD RESISTANCE k Figure. Total Harmonic Distortion vs. Load Resistance

10 AMP V S = V V S = V V S = V V STEP SLEW RATE V/ s SLEW RATE V/ s SETTLING TIME s VOLTAGE GAIN G k p n n n LOAD CAPACITANCE F VOLTAGE GAIN G k Figure. Slew Rate vs. Voltage Gain Figure. Slew Rate vs. Load Capacitance Figure. Settling Time to.% vs. Voltage Gain VOLTAGE NOISE nv/ Hz G = VOLTAGE NOISE nv/ Hz k V S = V f = khz POSITIVE SUPPLY CURRENT ma T A = C k k FREQUENCY Hz Figure. Voltage Noise Density vs. Frequency VOLTAGE GAIN G Figure. RTI Voltage Noise Density vs. Gain k POWEUPPLY VOLTAGE Volts Figure. Positive Supply Current vs. Supply Voltage NEGATIVE SUPPLY CURRENT ma T A = C POSITIVE SUPPLY CURRENT ma V S = V NEGATIVE SUPPLY CURRENT ma V S = V V = V REF = V POWEUPPLY VOLTAGE Volts Figure. Negative Supply Current vs. Supply Voltage TEMPERATURE C Figure. Positive Supply Current vs. Temperature TEMPERATURE C Figure. Negative Supply Current vs. Temperature

11 AMP INPUT AND OUTPUT OFFSET VOLTAGES Instrumentation amplifiers have independent offset voltages associated with the input and output stages. While the initial offsets may be adjusted to zero, temperature variations will cause shifts in offsets. Systems with auto-zero can correct for offset errors, so initial adjustment would be unnecessary. However, many high-gain applications don t have auto zero. For these applications, both offsets can be nulled, which has minimal effect on TCV IOS and TCV OOS The input offset component is directly multiplied by the amplifier gain, whereas output offset is independent of gain. Therefore, at low gain, output-offset errors dominate, while at high gain, input-offset errors dominate. Overall offset voltage, V OS, referred to the output (RTO) is calculated as follows; V OS (RTO) = (V IOS G) V OOS () where V IOS and V OOS are the input and output offset voltage specifications and G is the amplifier gain. Input offset nulling alone is recommended with amplifiers having fixed gain above. Output offset nulling alone is recommended when gain is fixed at or below. In applications requiring both initial offsets to be nulled, the input offset is nulled first by short-circuiting, then the output offset is nulled with the short removed. The overall offset voltage drift TCV OS, referred to the output, is a combination of input and output drift specifications. Input offset voltage drift is multiplied by the amplifier gain, G, and summed with the output offset drift; TCV OS (RTO) = (TCV IOS G) TCV OOS () where TCV IOS is the input offset voltage drift, and TCV OOS is the output offset voltage specification. Frequently, the amplifier drift is referred back to the input (RTI), which is then equivalent to an input signal change; TCV OS (RTI) = TCV TCV OOS IOS () G For example, the maximum input-referred drift of an AMP EX set to G = becomes; TCV OS (RTI ) =. µv/ C µv/ C =. µv/ C max INPUT BIAS AND OFFSET CURRENTS Input transistor bias currents are additional error sources that can degrade the input signal. Bias currents flowing through the signal source resistance appear as an additional offset voltage. Equal source resistance on both inputs of an IA will minimize offset changes due to bias current variations with signal voltage and temperature. However, the difference between the two bias currents, the input offset current, produces a nontrimmable error. The magnitude of the error is the offset current times the source resistance. A current path must always be provided between the differential inputs and analog ground to ensure correct amplifier operation. Floating inputs, such as thermocouples, should be grounded close to the signal source for best common-mode rejection. GAIN The AMP uses two external resistors for setting voltage gain over the range. to,. The magnitudes of the scale resistor,, and gain-set resistor,, are related by the formula: G = /, where G is the selected voltage gain (refer to Figure ). AMP VOLTAGE GAIN, G = ( ) OUTPUT Figure. Basic AMP Connections for Gains. to, The magnitude of affects linearity and output referred errors. Circuit performance is characterized using = kω when operating on ± volt supplies and driving a ± volt output. may be reduced to kω in many applications particularly when operating on ± volt supplies or if the output voltage swing is limited to ± volts. Bandwidth is improved with = kω and this also increases common-mode rejection by approximately db at low gain. Lowering the value below kω can cause instability in some circuit configurations and usually has no advantage. High voltage gains between two and ten thousand would require very low values of. For = kω and A V = we get = Ω; this value is the practical lower limit for. Below Ω, mismatch of wirebond and resistor temperature coefficients will introduce significant gain tempco errors. Therefore, for gains above,, should be kept constant at Ω and increased. The maximum gain of, is obtained with set to kω. Metal-film or wirewound resistors are recommended for best results. The absolute values and TCs are not too important, only the ratiometric parameters. AC amplifiers require good gain stability with temperature and time, but dc performance is unimportant. Therefore, low cost metal-film types with TCs of ppm/ C are usually adequate for and. Realizing the full potential of the AMP s offset voltage and gain stability requires precision metal-film or wirewound resistors. Achieving a ppm/ C gain tempco at all gains requires and temperature coefficient matching to ppm/ C or better.

12 AMP RESISTANCE M k k k V S = V IVR is the data sheet specification for input voltage range; V OUT is the maximum output signal; G is the chosen voltage gain. For example, at C, IVR is specified as ±. volt minimum with ± volt supplies. Using a ± volt maximum swing output and substituting the figures in () simplifies the formula to: CMVR = ±. G () For all gains greater than or equal to, CMVR is ± volt minimum; at gains below, CMVR is reduced. k k VOLTAGE GAIN Figure. and Selection Gain accuracy is determined by the ratio accuracy of and combined with the gain equation error of the AMP (.% max for A/E grades). All instrumentation amplifiers require attention to layout so thermocouple effects are minimized. Thermocouples formed between copper and dissimilar metals can easily destroy the TCV OS performance of the AMP which is typically. µv/ C. Resistors themselves can generate thermoelectric EMF s when mounted parallel to a thermal gradient. Vishay resistors are recommended because a maximum value for thermoelectric generation is specified. However, where thermal gradients are low and gain TCs of ppm ppm are sufficient, general-purpose metal-film resistors can be used for and. COMMON-MODE REJECTION Ideally, an instrumentation amplifier responds only to the difference between the two input signals and rejects commonmode voltages and noise. In practice, there is a small change in output voltage when both inputs experience the same commonmode voltage change; the ratio of these voltages is called the common-mode gain. Common-mode rejection (CMR) is the logarithm of the ratio of differential-mode gain to commonmode gain, expressed in db. CMR specifications are normally measured with a full-range input voltage change and a specified source resistance unbalance. The current-feedback design used in the AMP inherently yields high common-mode rejection. Unlike resistive feedback designs, typified by the three-op-amp IA, the CMR is not degraded by small resistances in series with the reference input. A slight, but trimmable, output offset voltage change results from resistance in series with the reference input. The common-mode input voltage range, CMVR, for linear operation may be calculated from the formula: CMVR = ± IVR V OUT G () ACTIVE GUARD DRIVE Rejection of common-mode noise and line pick-up can be improved by using shielded cable between the signal source and the IA. Shielding reduces pick-up, but increases input capacitance, which in turn degrades the settling-time for signal changes. Further, any imbalance in the source resistance between the inverting and noninverting inputs, when capacitively loaded, converts the common-mode voltage into a differential voltage. This effect reduces the benefits of shielding. AC common-mode rejection is improved by bootstrapping the input cable capacitance to the input signal, a technique called guard driving. This technique effectively reduces the input capacitance. A single guard-driving signal is adequate at gains above and should be the average value of the two inputs. The value of external gain resistor is split between two resistors and ; the center tap provides the required signal to drive the buffer amplifier (Figure ). GROUNDING The majority of instruments and data acquisition systems have separate grounds for analog and digital signals. Analog ground may also be divided into two or more grounds which will be tied together at one point, usually the analog power-supply ground. In addition, the digital and analog grounds may be joined, normally at the analog ground pin on the A-to-D converter. Following this basic grounding practice is essential for good circuit performance (Figure ). Mixing grounds causes interactions between digital circuits and the analog signals. Since the ground returns have finite resistance and inductance, hundreds of millivolts can be developed between the system ground and the data acquisition components. Using separate ground returns minimizes the current flow in the sensitive analog return path to the system ground point. Consequently, noisy ground currents from logic gates do not interact with the analog signals. Inevitably, two or more circuits will be joined together with their grounds at differential potentials. In these situations, the differential input of an instrumentation amplifier, with its high CMR, can accurately transfer analog information from one circuit to another. AND TERMINALS The sense terminal completes the feedback path for the instrumentation amplifier output stage and is normally connected directly to the output. The output signal is specified with respect to the reference terminal, which is normally connected to analog ground.

13 AMP VOLTAGE GAIN, G = ( ) A V = WITH COMPONENTS SHOWN k C NC * R V C C F GUARD DRIVE SIGNAL GROUND R M V V R M V IOS NULL VR k AMP V OOS NULL VR k R * C C F R C * * *SOLDER LINK * OUTPUT GROUND Figure. AMP Evaluation Circuit Showing Guard-Drive Connection V ANALOG POWEUPPLY V V V DIGITAL POWEUPPLY V V. F C C C C DIGITAL GROUND C C C AMP SMP- SAMPLE AND HOLD ANALOG GROUND ADC DIGITAL GROUND DIGITAL DATA OUTPUT OUTPUT HOLD CAPACITOR Figure. Basic Grounding Practice C = CERAMIC CAPACITORS

14 AMP If heavy output currents are expected and the load is situated some distance from the amplifier, voltage drops due to track or wire resistance will cause errors. Voltage drops are particularly troublesome when driving Ω loads. Under these conditions, the sense and reference terminals can be used to remote sense the load as shown in Figure. This method of connection puts the I R drops inside the feedback loop and virtually eliminates the error. An unbalance in the lead resistances from the sense and reference pins does not degrade CMR, but will change the output offset voltage. For example, a large unbalance of Ω will change the output offset by only mv. DRIVING LOADS Output currents of ma are guaranteed into loads of up to Ω and ma into Ω. In addition, the output is stable and free from oscillation even with a high load capacitance. The combination of these unique features in an instrumentation amplifier allows low-level transducer signals to be conditioned and directly transmitted through long cables in voltage or current form. Increased output current brings increased internal dissipation, especially with Ω loads. For this reason, the power-supply connections are split into two pairs; pins and connect to the output stage only and pins and provide power to the input and following stages. Dual supply pins allow dropper resistors to be connected in series with the output stage so excess power is dissipated outside the package. Additional decoupling is necessary between pins and to ground to maintain stability when dropper resistors are used. Figure shows a complete circuit for driving Ω loads. AMP * IN DIODES ARE OPTIONAL. DIODES LIMIT THE OUTPUT VOLTAGE EXCURSION IF AND/OR LINES BECOME DISCONNECTED FROM THE LOAD. * * TWISTED PAIRS REMOTE LOAD OUTPUT GROUND Figure. Remote Load Sensing POWER BANDWIDTH, G =, khz POWER BANDWIDTH, G =, khz khz, Vrms k AMP R W C V V OUT V MAX LOAD C R VOLTAGE GAIN, G = ( S ) RESISTERS R AND R REDUCE IC DISSIPATION R W Figure. Driving Ω Loads V

15 AMP HEATSINKING To maintain high reliability, the die temperature of any IC should be kept as low as practicable, preferably below C. Although most AMP application circuits will produce very little internal heat little more than the quiescent dissipation of mw some circuits will raise that to several hundred milliwatts (for example, the - ma current transmitter application, Figure ). Excessive dissipation will cause thermal shutdown of the output stage thus protecting the device from damage. A heatsink is recommended in power applications to reduce the die temperature. Several appropriate heatsinks are available; the Thermalloy B is especially easy to use and is inexpensive. Intended for dual-in-line packages, the heatsink may be attached with a cyanoacrylate adhesive. This heatsink reduces the thermal resistance between the junction and ambient environment to approximately C/W. Junction (die) temperature can then be calculated by using the relationship: P d = T J T A θ JA where T J and T A are the junction and ambient temperatures respectively, θ JA is the thermal resistance from junction to ambient, and P d is the device s internal dissipation. OVERVOLTAGE PROTECTION Instrumentation amplifiers invariably sit at the front end of instrumentation systems where there is a high probability of exposure to overloads. Voltage transients, failure of a transducer, or removal of the amplifier power supply while the signal source is connected may destroy or degrade the performance of an unprotected amplifier. Although it is impractical to protect an IC internally against connection to power lines, it is relatively easy to provide protection against typical system overloads. The AMP is internally protected against overloads for gains of up to. At higher gains, the protection is reduced and some external measures may be required. Limited internal overload protection is used so that noise performance would not be significantly degraded. AMP noise level approaches the theoretical noise floor of the input stage which would be nv/ Hz at khz when the gain is set at. Noise is the result of shot noise in the input devices and Johnson noise in the resistors. Resistor noise is calculated from the values of ( Ω at a gain of ) and the input protection resistors ( Ω). Active loads for the input transistors contribute less than nv/ Hz of noise. The measured noise level is typically nv/ Hz. Diodes across the input transistor s base-emitter junctions, combined with Ω input resistors and, protect against differential inputs of up to ± V for gains of up to. The diodes also prevent avalanche breakdown that would degrade the I B and I OS specifications. Decreasing the value of for gains above limits the maximum input overload protection to ± V. External series resistors could be added to guard against higher voltage levels at the input, but resistors alone increase the input noise and degrade the signal-to-noise ratio, especially at high gains. Protection can also be achieved by connecting back-to-back. V Zener diodes across the differential inputs. This technique does not affect the input noise level and can be used down to a gain of with minimal increase in input current. Although voltage-clamping elements look like short circuits at the limiting voltage, the majority of signal sources provide less than ma, producing power levels that are easily handled by low-power Zeners. Simultaneous connection of the differential inputs to a low impedance signal above V during normal circuit operation is unlikely. However, additional protection involves adding Ω current-limiting resistors in each signal path prior to the voltage clamp, the resistors increase the input noise level to just. nv/ Hz (refer to Figure ). Input components, whether multiplexers or resistors, should be carefully selected to prevent the formation of thermocouple junctions that would degrade the input signal. * OPTIONAL PROTECTION RESISTORS, SEE TEXT. V LINEAR INPUT RANGE, V MAXIMUM W* W*.V W ZENERS AMP V DIFFERENTIAL PROTECTION TO V V OUT Figure. Input Overvoltage Protection for Gains to, POWEUPPLY CONSIDERATIONS Achieving the rated performance of precision amplifiers in a practical circuit requires careful attention to external influences. For example, supply noise and changes in the nominal voltage directly affect the input offset voltage. A PSR of db means that a change of mv on the supply, not an uncommon value, will produce a µv input offset change. Consequently, care should be taken in choosing a power unit that has a low output noise level, good line and load regulation, and good temperature stability.

16 AMP V IN k AMP k V V R OUT TRIM R COMPLIANCE, TYPICALLY V LINEARITY ~.% OUTPUT RESISTANCE AT ma ~M POWER BANDWIDTH ( db) ~khz INTO LOAD R I OUT R I OUT = V IN( S ) R R = FOR I OUT = ma V IN = mv FOR ma FULL SCALE Figure. High Compliance Bipolar Current Source with -Bit Linearity ALL RESISTORS % METAL FILM k V TO V.k AMP R R.k R R OUT TRIM REF- V R R ZERO TRIM R I OUT ma TO ma V COMPLIANCE OF I OUT, V WITH V SUPPLY (OUTPUT w.r.t. V) DIFFERENTIAL INPUT OF mv FOR ma SPAN OUTPUT RESISTANCE ~M AT I OUT = ma LINEARITY.% OF SPAN Figure. -Bit Linear ma Transmitter Constructed by Adding a Voltage Reference. Thermocouple Signals Can Be Accepted Without Preamplification.

17 AMP F V k AMP N N V OUT ( V INTO ) GND VOLTAGE GAIN, G = POWER BANDWIDTH ( db), khz QUIESCENT CURRENT, ma FULL OUTPUT INTO V Figure. Adding Two Transistors Increases Output Current to ± A Without Affecting the Quiescent Current of ma. Power Bandwidth is khz. V IC V k k k k Q, Q...J Q, Q, Q...J IC...CMP- IC...OPGZ k k k Q Q Q Q Q V IOS NULL k AMP V OOS NULL V OUT GND V k.k IC G G G G k k V LINEARITY~.%, G = AND ~.%, G = AND GAIN ACCURACY, UNTRIMMED~.% SETTLING TIME TO.%, ALL GAINS, LESS THAN s GAIN SWITCHING TIME, LESS THAN s TTL COMPATIBLE INPUTS Figure. The AMP Makes an Excellent Programmable-Gain Instrumentation Amplifier. Combined Gain-Switching and Settling Time to Bits Falls Below µs. Linearity Is Better than Bits over a Gain Range to.

18 AMP k AMP V *MATCHED TO.%.k *k pf OP *k V V R ( S VOLTAGE GAIN, G = ) MAXIMUM OUTPUT, V p-p INTO khz, V p-p INTO, G = R L DIFFERENTIAL OUTPUT OUTPUT COMMON-MODE ( V MAX) Figure. A Differential Input Instrumentation Amplifier with Differential Output Replaces a Transformer in Many Applications. The Output will Drive a Ω Load at Low Distortion, (.%). V V IN REF V F POWER BANDWIDTH ( db)~khz TOTAL HARMONIC V p-p INTO // pf R AMP V OUT F R.k C L R L NC NC V CLOSED-LOOP VOLTAGE GAIN MUST BE GREATER THAN FOTABLE OPERATION NC = NO CONNECT VOLTAGE GAIN, G = R ( ) R R Figure. Configuring the AMP as a Noninverting Operational Amplifier Provides Exceptional Performance. The Output Handles Low Load Impedances at Very Low Distortion,.%.

19 AMP NC NC R k V IN R. F RS.k R AMP REF V OUT R V p-p INTO // pf. TOTAL HARMONIC DISTORTION: khz, V OUT = V p-p G = TO R = R GAIN (G) R = R // R R G G = G = AND V V F Figure. The Inverting Operational Amplifier Configuration has Excellent Linearity over the Gain Range to, Typically.%. Offset Voltage Drift at Unity Gain Is Improved over the Drift in the Instrumentation Amplifier Configuration. V V IN R.k pf. F REF F POWER BANDWIDTH ( db)~khz TOTAL HARMONIC V p-p INTO // pf NC = NO CONNECT R k AMP V OUT NC V F R.k C L R L NC Figure. Stability with Large Capacitive Loads Combined with High Output Current Capability make the AMP Ideal for Line Driving Applications. Offset Voltage Drift Approaches the TCV IOS Limit, (. µv/ C).

20 AMP.k k k k G G G G e OUT e n (G =,, ) = G AMP k.k.m.k F G G,, F / OP / OP OUTPUT F.k e e OUT n (G = ) = G k Figure. Noise Test Circuit (. Hz to Hz) V IN V p-p T.k.% HSCH- V OUT G G k.% k.% k.% G.k.% G.%.% k.% k.% k.% G G G G.% AMP Figure. Settling-Time Test Circuit

21 AMP V DG ANALOG SWITCH k AMP k VOLTAGE GAIN, G = ( ).k V OUT ma, DAC- R. F TTL INPUT "OFFSET".k V TTL INPUT "ZERO" V Figure. Instrumentation Amplifier with Autozero V k RS AMP k V OUT V Figure. Burn-In Circuit

22 AMP OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Lead Cerdip (Q-). (.) MIN. (.) MAX. (.) MAX. (.). (.). (.). (.) PIN. (.) MAX. (.) BSC. (.). (.). (.). (.). (.). (.). (.) MIN SEATING PLANE. (.). (.). (.). (.) Cb / -Terminal Ceramic Leadless Chip Carrier (E-A). (.). (.). SQ (.) MAX SQ. (.). (.). (.). (.). (.). (.). (.). (.) R TYP. (.) REF. (.) REF. (.). (.). (.) BSC. (.) BSC BOTTOM VIEW. (.) BSC. (.) MIN. (.). (.). (.) BSC TYP -Lead SOIC (R-). (.). (.). (.). (.) PIN. (.) BSC. (.). (.). (.). (.). (.). (.) SEATING PLANE. (.). (.). (.). (.). (.). (.). (.). (.) PRINTED IN U.S.A.