TMC2250A Matrix Multiplier 12 x 10 bit, 50 MHz

Transcription

1 Matrix Multiplier x bit, 50 MHz Features Four user-selectable filtering and transformation functions: Triple dot product ( x ) matrix multiply Cascadeable 9-tap systolic FIR filter Cascadeable x -pixel image convolver Cascadeable x 2-pixel image convolver 50 MHz (20ns) pipelined throughput -bit input and output data, -bit coefficients 6-bit cascade input and output ports in all filter modes Onboard coefficient storage, with three-cycle updating of all nine coefficients Applications Image filtering and manipulation Video effects generation Video standards conversion and encoding/decoding Three-dimensional image manipulation Medical image processing Edge detection for object recognition FIR filtering for communications systems Description The is a flexible high-performance nine-multiplier array VLSI circuit which can execute a cascadeable 9-tap FIR filter, a cascadeable x 2 or x -pixel image convolution, or a x color space conversion. All configurations offer throughput at up to the maximum guaranteed 50 MHz clock rate with -bit data and -bit coefficients. All inputs and outputs are registered on the rising edges of the clock. The x matrix multiply or color conversion configuration can perform video standard conversion (YIQ or YUV to RGB, etc.) or three-dimensional perspective translation at real-time video rates. The 9-tap FIR filter configuration, useful in Video, Telecommunications, and Signal Processing, features a 6-bit cascade input to allow construction of longer filters. The cascadeable x and x 2-pixel image convolver functions allow the user to perform numerous image processing functions, including static filters and edge detectors. The 6-bit cascade input port facilitates two-chip 50 MHz cubic convolution ( x -pixel kernel). The is fabricated in a sub-micron CMOS process and operates at clock speeds of up to 50 MHz over the full commercial (0 C to 70 C) temperature and supply voltage ranges. It is available in 0-pin Plastic Pin Grid Array (PPGA) packages, 0-lead Ceramic Pin Grid Array package (CPGA), 0-lead PQFP to PPGA package (MPGA) and 0-lead Plastic Quad FlatPack (PQFP). All input and output signals are TTL compatible. REV..0.2 /25/00

2 PRODUCT SPECIFICATION Functional Description The is a nine-multiplier array with the internal bus structure and summing adders needed to implement a x matrix multiplier (triple dot product) a cascadeable 9-tap FIR filter, a x -pixel convolver, or a x 2-pixel convolver all in one monolithic circuit. With a 50MHz guaranteed maximum clock rate, this device offers video and imaging system designers a single-chip solution to numerous common image and signal-processing problems. The three data input ports (A, B, C) accept -bit two's complement integer data, which is also the format for the output ports (X, Y, Z) in the matrix multiply mode (Mode 00). In the filter configurations (Modes 0,, and ) the cascade ports assume -bit integer, -bit fractional two's complement data on both input and output. The coefficient input ports (KA, KB, KC) are always -bit two's complement fractional. Table details the bit weighting of the input and output data in all configurations. Operating Modes The can implement four different digital filter architectures. Upon selection of the desired function by the user (MODE -0 ), the device reconfigures its internal data paths and input and output buses appropriately. The output ports (XC, YC and ZC) are configured in all filter modes a 6-bit Cascade In and Cascade Out ports so that multiple devices can be connected to build larger filters. These modes are described individually below. The I/O function configurations for all four modes are shown in Table. Definitions The calculations performed by the in each mode are also shown below, utilizing the following notation: A(), B(5), C(2), CASIN() Indicates the data word presented to that input port during the specified clock rising edge(x). Applies to all input ports A -0, B -0, C -0, and CASIN 5-0. KA(), KB() Indicates coefficient data stored in the specified one of the nine onboard coefficient registers KA through KC, as shown in the block diagram for that mode, input during or before the specified clock rising edge (x). X(), Y(), Z(6), CASOUT (6) Indicated data available at that output port t DO after that specified clock rising edge (x). Applies to all output ports X -0, Y -0, Z -0, and CASOUT 5-0. Numeric Format Table 2 shows the binary weightings of the input and output ports of the. Although the internal sums of products could grow to 2 bits, in the matrix multiply mode (Mode 00) the outputs X, Y and Z are rounded to yield -bit integer words. Thus the output format is identical to the input data format. In the filter configurations (Modes 0,, and ) the cascade output is always half-lsb rounded to 6 bits, specifically integer bits and fractional guard bits, with no overflow "headroom". The user is of course free to half-lsb round the output word to any size less than 6 bits by forcing a into the bit position of the cascade input immediately below the desired LSB. In all modes, bit weighting is easily adjusted if desired by applying the same scaling correction factor to both input and output data words. If the coefficients are rescaled, the relative weightings of the CASIN and CASOUT ports will differ accordingly. Data Overflow As shown in Table 2, the 's matched input and output data formats accommodate 0dB (unity) gain. Therefore, the user must be aware of input conditions that could lead to numeric overflow. Maximum input data and coefficient word sizes must be taken into account with the specific algorithm performed to ensure that no overflow occurs. Table. Data Port Formatting by Mode Mode Inputs Inputs/Output Outputs A -0 B -0 C -0 KA 9-0 KB 9-0 KC9-0 XC -0 YC -8 Y 7- YC-0 ZC A -0 B -0 C -0 KA 9-0 KB 9-0 KC9-0 X -0 Y -8 Y 7- Y -0 Z -0 0 A -0 B -0 NC KA 9-0 KB 9-0 KC9-0 CASIN 5- CASIN -0 NC CASOUT -0 CASOUT 5- A -0 B -0 C -0 KA 9-0 KB 9-0 KC9-0 CASIN 5- CASIN -0 NC CASOUT -0 CASOUT 5- A -0 B -0 NC KA 9-0 KB 9-0 KC9-0 CASIN 5- CASIN -0 NC CASOUT -0 CASOUT 5-2 REV..0.2 /25/00

3 PRODUCT SPECIFICATION Table 2. Bit Weightings for Input and Output Data Words Bit Weights Inputs All Modes Data A, B, C Coefficients KA, KB, KC -I I I 9 I 8 I 7 I 6 I 5 I I I 2 I I 0. Note: A minus sign indicates a two s complement sign bit. -K 9. K 8 K 7 K 6 K 5 K K K 2 K K 0 Modes 0, -CI 5 CI CI CI CI CI CI 9 CI 8 CI 7 CI 6 CI 5 CI. CI CI 2 CI CI 0, CASIN Internal Sum X 20 X 9 X 8 X 7 X 6 X 5 X X X X X X 9. X 8 X 7 X 6 X 5 X X X 2 X X 0 Outputs Mode 00 X, Y, Z Modes 0,, CASOUT -O O O 9 O 8 O 7 O 6 O 5 O O O 2 O O 0. - CO CO CO CO CO CO CO CO CO CO CO.COCO CO CO CO REV..0.2 /25/00

4 PRODUCT SPECIFICATION REV..0.2 /25/00 Pin Assignments 0 Pin Plastic Quad Flat Pack (MQFP), KE Package XC6 XC5 XC XC XC2 XC XC0 YC YC YC9 VDD YC8 Y7 Y6 Y5 Y YC0 VDD YC YC2 YC ZC0 ZC ZC2 ZC ZC ZC ZC6 ZC7 ZC8 ZC9 ZC ZC KC0 KC KC2 KC KC KC5 KC6 VDD KC7 KC8 KC9 KB0 KB KB2 KB KB KB5 KB6 KB7 KB8 KB9 KA Pin Name Pin Name KA KA2 KA KA KA5 KA6 KA7 KA8 KA9 CWE CWE0 A0 A A2 A A A5 A6 A7 A8 A9 A A B0 B B2 CLK B B B5 B6 B7 B8 B9 B B C0 C C2 C VDD C C5 C6 C7 C8 C9 C C MODE MODE0 XC XC XC9 VDD XC8 XC Pin Name Pin Name

5 PRODUCT SPECIFICATION Pin Assignments (continued) 0 Pin Plastic Pin Grid Array, H5 Package and 0 Pin Ceramic Pin Grid Array, G Package and 0 Pin Plastic Quad Flatpack to 0-Pin Pin Grid Array (MPGA) KEY Top View Cavity Up A B C D E F G H J K L M N Pin Name Pin Name A A2 A A A5 A6 A7 A8 A9 A A A A B B2 B B B5 B6 B7 B8 B9 B B B B C C2 C C XC7 XC9 XC MODE0 C C8 C7 C5 C C B B7 B XC XC5 XC8 XC MODE C9 C6 C C2 B B9 B6 B2 XC XC2 XC6 VDD C5 C6 C7 C8 C9 C C C C D D2 D D D D E E2 E E E E F F2 F F F F G G2 G C VDD C0 B8 B5 B B YC XC0 XC0 CLK B0 A YC9 YC A A9 A8 Y7 YC8 VDD A7 A6 A5 Y5 Y6 Pin Name Pin Name G G G H H2 H H H H J J2 J J J J K K2 K K K K L L2 L L L5 L6 L7 L8 L9 A A2 A Y YC0 VDD A0 A YC YC2 KA8 CWE CWE0 YC ZC0 ZC KA KA7 KA9 ZC ZC ZC6 KC0 VDD KB0 KB L L L L M M2 M M M5 M6 M7 M8 M9 M M M M N N2 N N N5 N6 N7 N8 N9 N N N N KB8 KA KA5 KA6 ZC2 ZC7 ZC9 ZC KC2 KC KC6 KC9 KB2 KB5 KB9 KA2 KA ZC5 ZC8 ZC KC KC KC5 KC7 KC8 KB KB KB6 KB7 KA0 REV..0.2 /25/00 5

6 PRODUCT SPECIFICATION Pin Descriptions Pin Number Pin Name CPGA/PPGA/ MPGA MQFP Power V DD F, H, L7, C8,, 20, 6, C 2, 8 E, G, J, L, L6, H, C7, C5 Clock 8, 6, 2,, 2, 72, 6, Function Supply Voltage Ground Pin Description The operates from a single +5V supply. All pins must be connected. The operates from a single +5V supply. All pins must be connected. CLK D 88 System Clock The operates from a single system clock input. All timing specifications are referenced to the rising edge of clock. Controls MODE,0 B, A, Mode Control The will switch to the configuration selected by the user (as shown in Table ) on the next clock. This registered control is usually static; however, should the user wish to switch between modes, the internal pipeline latencies of the device must be taken into account. Valid data will not be available at the outputs in the new configuration until enough clocks in the new mode have passed to flush the internal registers. CWE,0 J, J 70, 7 Coefficient Write Enable Input/Output A -0 E, D, E, E, F, F, F, G, G, G, H, H B -0 B, A, B, C, A, B, C, A, C, B, C, D C -0 A5, C6, B6, A6, A7, B7, A8, B8, A9, B9, A, C9 8, 8, 82, 8, 80, 79, 78, 77, 76, 75, 7, 7 97, 96, 95, 9, 9, 92, 9, 90, 89, 87, 86, 85,, 9, 8, 7, 5,,,, 0, 99, 98 Data Input A Data Input B Data Input C Data presented to the coefficient input ports (KA, KB, and KC) will update three of the internal coefficient storage registers, as indicated by the simultaneous Coefficient Write Enable select, on the next clock. See Table and the Functional Block Diagram. Data presented to the -bit registered data input ports A, B, and C are latched into the multiplier input registers for the currently selected configuration (Table ). In all modes except Mode 00, new data are internally right-shifted to the next filter tap on each rising edge of CLK. 6 REV..0.2 /25/00

7 PRODUCT SPECIFICATION Pin Descriptions (continued) Pin Name CPGA/PPGA/ MPGA KA 9-0 K, J, K, L, L, K, M, M, L, N KB 9-0 M, L, N, N, M, L9, N, M9, N9, L8 69, 68, 67, 66, 65, 6, 6, 62, 6, 60 59, 58, 57, 56, 55, 5, 5, 52, 5, 50 KC 9-0 M8, N8, N7, M7, N6, M6, N5, M5, N, L5 9, 8, 7, 5,,,, 0, 9, 8 XC -0 B, A, A2, B, 5, 6, A, C, B2, B, 7, 9, D, C2, C, D2 0,, 2,,, 5, 6, 7 Coefficient Input A, A2, A Coefficient Input B, B2, B Coefficient Input B, B2, B CASIN 5- / Output X YC -8 D, E2, E, F2 9,,, CASIN -0 / Output Y -0 Y 7- F, G2, G, H, 5, 7, 8 Output 7- only YC -0 K, J2, J, H2 2, 22,, 9 CASOUT -0 / Output Y -0 ZC -0 M, N, M, N2, M2, L, N, L2, K, M, L, K2 Pin Number MQFP 7, 6, 5,, 2,, 0, 29, 28, 27, 26, 25 Function CASOUT 5- / Output Z -0 Pin Description Data presented to the -bit registered coefficient input ports KA, KB and KC are latched three at a time into the internal coefficient storage register set indicated by the Coefficient Write Enable CWE,0 on the next clock, as shown in Table. In all modes except Mode 00, the x port and four bits of the Y output port are reconfigured as the 6-bit registered Cascade Input port CASIN 5-0. Data presented to this input will be added to the weighted sums of the data words which were presented to the input ports (A, B and C). In the matrix multiply mode, data are available at the -bit registered output ports X, Y AND Z t DO after every clock. These ports are reconfigured in the filtering modes as 6-bit Cascade Input and Output ports.casout 5-0 In all modes except Mode 00, the Z port and four bits of the Y output port are reconfigured as the 6-bit registered Cascade Output port CASOUT 5-0. Notes:. The output ports X, Y, Z and CASOUT, and input port CASIN are internally reconfigured by the device as required for each mode of the device. The multiple-function pins have names which are combinations of these titles, as appropriate. 2. The output drivers on pins XC -0 and YC -8 are not necessarily disabled until after the first rising edge of CLK following power-up. If these pins are to be tied to other output drivers, to each other, or to ground or V DD, the user should ensure that a clock pulse arrives within a few seconds of power-up, to avoid bus contention. Table. Configuration Mode Word MODE,0 Configuration Mode 00 x Matrix Multiply 0 9-Tap One Dimensional FIR x -Pixel Convolver x 2 -Pixel Convolver Table. Coefficient Write Enable Word CWE,0 Coefficient Set Selected 00 Hold all registers 0 Update KA, KB, KC Update KA2, KB2, KC2 Update KA, KB, KC REV..0.2 /25/00 7

8 PRODUCT SPECIFICATION Table 5. Coefficient Input Ports Input Port KA KB KC Registers Available KA, KA2, KA KB, KB2, KB KC, KC2, KC x Matrix Multiplier (Mode 00) This mode utilizes all six input and output ports in the basic configuration to realize a "triple dot product", in which each output is the sum of all three input words in that column multiplied by the appropriate stored coefficients. The three corresponding sums of products are available at the outputs five clock cycles after the input data are latched, and three new data words half-lsb rounded to bits are then available every clock cycle. X(5)=A()KA()+B()KB()+C()KC() Y(5)=A()KA2()+B()KB2()+C()KC2() Z(5)=A()KA()+B()KB()+C()KC() CLK CWE 0 00 KA, KB, KC K_ K_2 K_ DATA IN A, B, C MODE CONTROL X OUT Y OUT Z OUT 00 KA + KB + KC KA 2 + KB 2 + KC 2 KA + KB + KC Figure. x Matrix Multiplier Impulse Response (Mode 00) 8 REV..0.2 /25/00

9 PRODUCT SPECIFICATION A KA KA2 KA KA B KB KB2 KB KB C KC KC2 KC KC RND RND RND (MSB) (MSB) (MSB) 5 X 5 Y 5 Z Figure 2. x Matrix Multiplier Configuration (Mode 00) REV..0.2 /25/00 9

10 PRODUCT SPECIFICATION 9-Tap FIR Filter Mode (0) The architecture for this configuration is shown in Figure. The user loads the desired coefficient set, presents input data to ports A and B simultaneously (most applications will wire the A and B inputs together), and receives the resulting 9- sample response, half-lsb rounded to 6 bits, 5 to clock cycles later. A new output data word is available every clock cycle. The figure shows that the input data are automatically rightshifted by one position through the row of multiplier input registers on every clock in anticipation of a new input data word. CASOUT() = A(9)KA(9)+A(8)KA2(8)+A(7)KA(7) +B(6)KB(9)+B(5)KB2(8)+B()KB(7) +B()KC(9)+B(2)KC2(8)+B()KC(7) +CASIN() Latency: Impulse in to center of 9-tap response =9 registers. Cascade In to Cascade Out= registers. CLK CWE 0 KA, KB, KC K_ K_2 K_ DATA IN A, B.0 MODE CONTROL 0 CASIN Q CASOUT KA KA2 KA KB KB2 KB KC KC2 KC Q Figure. 9-Tap FIR Filter Impulse Response (Mode 0) REV..0.2 /25/00

11 PRODUCT SPECIFICATION A KA KA2 KA KA B KB 6 KB2 6 KB KB C KC KC2 KC KC CASIN (0-5) 6 6 (MSB) 000 HALF LSB ROUNDING 5 2, 5, 8,, 5, 6 8, 9,, - 6 (MSB) 6 Z = CASOUT (0-5) Figure. 9-Tap FIR Filter Configuration (Mode 0) REV..0.2 /25/00

12 PRODUCT SPECIFICATION x Pixel Convolver (Mode ) This filter configuration accepts a pixel-square neighborhood, side-loaded three pixels at a time through input ports A, B and C, and multiplies the 9 most recent pixel values by the coefficient set currently stored in the registers. These products are summed with the data presented to the cascade input, and a new -cycle impulse response, rounded to 6 bits, is available at the output port 5 to 7 clocks later, with a new output available on every clock cycle. The input pixel data are automatically shifted one location to the right through the three rows of multiplier input registers on every clock in anticipation of three new input data words, effectively sliding the convolutional window over one column in an image plane. CASOUT(7)= A()KA()+A(2)KA2(2)+A()KA() +B()KB()+B(2)KB2(2)+B()KB() +C()KC()+C(2)KC2(2)+C()KC() +CASIN() Latency: Impulse in to center of -tap response = 6 registers. Cascade In to Cascade Out= registers. CLK CWE 0 KA, KB, KC K_ K_2 K_ DATA IN A, B, C.0 MODE 0 CASIN Q7 CASOUT ΣK ΣK2 ΣK Q7 ΣKj = KAj + KBj + KCj Figure 5. x -Pixel Convolver Impulse Response (Mode ) REV..0.2 /25/00

13 PRODUCT SPECIFICATION A KA KA2 KA KA B KB KB2 KB KB C KC KC2 KC KC CASIN (0-5) 6 6 (MSB) 000 HALF LSB ROUNDING 5 2, 5, 5, (MSB) 6 Z = CASOUT (0-5) Figure 6. x -Pixel Convolver Configuration (Mode ) REV..0.2 /25/00

14 PRODUCT SPECIFICATION x 2-Pixel Cascadeable Convolver (Mode ) Similar to Mode, the x 2 -Pixel convolver allows the use to perform full-speed cubic convolution with only two devices and the TMCA Pipeline Delay Register to synchronize the cascade ports (see the Applications Discussion section). Pixel data are side-loaded into ports A and B, multiplied by the onboard coefficients, summed with the cascade input, and half-lsb rounded to 6 bits. The four-cycle impulse response emerges at the cascade output port 5 to 8 clock cycles later. A new output word is available on every clock cycle. Note that Multiplier KC2 is not used in this mode and that its stored coefficient is ignored. As shown below, the column of input pixel data is automatically shifted one location to the right through the two rows of multiplier input registers on every clock in anticipation of two new input data words, effectively sliding the convolutional window over one column in an image plane. CASOUT(8)= A()KA()+A()KA2()+A(2)KA(2) +A()KB()+B()KB()+B()KB2() +B(2)KB(2)+B()KC(2)+CASIN(5) CLK CWE 0 00 KA, KB, KC K_ K_2 K_ DATA IN A, B.0 MODE CASIN Q8 KA + KB KA + KB CASOUT Q8 KA2 + KB2 KC + KC Figure 7. x 2-Pixel Convolver Impulse Response (Mode ) REV..0.2 /25/00

15 PRODUCT SPECIFICATION A KA KA2 KA KA 2 B KB KB2 KB KB C 0 5 KC KC2 KC KC CASIN (0-5) 6 6 (MSB) 000 HALF LSB ROUNDING 2, 5, 5, 6 6, (MSB) 6 Z = CASOUT (0-5) Figure 8. x 2-Pixel Convolver Configuration (Mode ) REV..0.2 /25/00 5

16 PRODUCT SPECIFICATION CLK tcy 2 5 tpwh CWE tpwl KA, KB, KC td X, Y, Z CASOUT ts th PREVIOUS NEW tho Figure 9. Input/Output Timing Diagram V DD V DD p p Digital Input Digital Output n n Figure. Equivalent Digital Input Circuit Figure. Equivalent Digital Output Circuit Absolute Maximum Ratings (beyond which the device may be damaged) Parameter Min Typ Max Unit Supply Voltage V Input Voltage -0.5 V DD V Applied Voltage V DD V Externally Forced Current, ma Short Circuit Duration (single output in HIGH state to ground) sec Operating, Ambient Temperature -20 C Junction Temperature 0 C Storage Temperature C Lead Soldering Temperature ( seconds) 00 C Notes:. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range.. Forcing voltage must be limited to specified range.. Current is specified as conventional current flowing into the device. 6 REV..0.2 /25/00

17 PRODUCT SPECIFICATION Operating Conditions Parameter Min Nom Max Units V DD Power Supply Voltage V f CLK Clock Frequency 0 MHz -2 0 MHz - 50 MHz t PWH CLK pulse width, HIGH 6 ns t PWL CLK pulse width, LOW 8 ns t S Input Data Setup Time 6 ns t H Input Data Hold Time 2 ns V IH Input Voltage, Logic HIGH 2.0 V V IL Input Voltage, Logic LOW 0.8 V I OH Output Current, Logic HIGH -2.0 ma I OL Output Current, Logic LOW.0 ma T A Ambient Temperature, Still Air 0 70 C Electrical Characteristics Parameter Conditions Min Typ Max Units I DD Total Power Supply V DD = Max, C LOAD = 25pF, f CLK = Max Current 5 ma -2 0 ma - 55 ma I DDU Power Supply Current, V DD = Max, OE = HIGH, f CLK =Max Unloaded 0 ma -2 5 ma - 50 ma I DDQ Power Supply Current, Quiescent V DD = Max, CLK = LOW ma C PIN I/O Pin Capacitance 5 pf I IH Input Current, HIGH V DD = Max, V IN = V DD ±5 µa I IL Input Current, LOW V DD = Max, V IN = 0 V ±5 µa I OZH Hi-Z Output Leakage V DD = Max, V IN = V DD ± µa Current, Output HIGH 2 I OZL Hi-Z Output Leakage Current, Output LOW 2 V DD = Max, V IN = 0 V ± µa I OS Short-Circuit Current ma V OH Output Voltage, HIGH I OH = Max, V DD = Min 2. V V OL Output Voltage, LOW I OL = Max, V DD = Min 0. V Notes:. Except pins XC -0, YC Pins XC -0, YC -8. REV..0.2 /25/00 7

18 PRODUCT SPECIFICATION Switching Characteristics Parameter Conditions Min Typ Max Units t DO Output Delay Time C LOAD = 25 pf 5 ns t HO Output Hold Time C LOAD = 25 pf ns Application Notes Performing Large-Kernel Pixel Interpolation The Cascade Input and Output Ports of the allow the user to stack multiple devices to perform larger interpolation kernels with no decrease in pixel throughput. Figure illustrates a basic application utilizing Mode to realize a x -pixel kernel, also called Cubic Convolution. This example utilizes the TMC20A Variable-Length Shift Register to compensate for the internal latency of each. Alternatively, some applications may utilize RAM, FIFO's, or other methods to store multiple-line pixel data. In these cases the user may compensate for latency by simply offsetting the access sequencing of the storage devices. A B A X 2 B CASOUT 6 C D X TMCA A CASIN X 2 B CASOUT 6 OUTPUT Related Products Figure. Figure. Performing Cubic Convolution with Two 's TMC20 Image Resampling Sequencer TMC202A Image Manipulation Sequencer TMC229A Video Mixer TMC222B Half-Band Filter 8 REV..0.2 /25/00

19 PRODUCT SPECIFICATION Mechanical Dimensions 0-Lead CPGA Package Symbol Inches Millimeters Min. Max. Min. Max. A A A øb øb2.050 NOM..27 NOM. D D.200 BSC 0.8 BSC e.0 BSC 2.5 BSC L L M N 0 0 P Notes 2 2 SQ Notes:. Pin # identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish.. Dimension "M" defines matrix size.. Dimension "N" defines the maximum possible number of pins. 5. Orientation pin is at supplier's option. 6. Controlling dimension: inch. A2 A A L øb øb2 D P e Top View Cavity Up D Pin Identifier REV..0.2 /25/00 9

20 PRODUCT SPECIFICATION Mechanical Dimensions 0-Lead PPGA Package Symbol Inches Millimeters Min. Max. Min. Max. A A A øb øb2.050 NOM..27 NOM. D D.200 BSC 0.8 BSC e.0 BSC 2.5 BSC L L M N 0 0 P Notes 2 2 SQ Notes:. Pin # identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish.. Dimension "M" defines matrix size.. Dimension "N" defines the maximum possible number of pins. 5. Orientation pin is at supplier's option. 6. Controlling dimension: inch. A2 A A L øb øb2 D P e Top View Cavity Up D Pin Identifier 20 REV..0.2 /25/00

21 PRODUCT SPECIFICATION Mechanical Dimensions 0-Lead Metric Quad Flat Package to Pin Grid Array Package (MPGA) Symbol Inches Millimeters Min. Max. Min. Max. A A A A.050 TYP..27 TYP. øb øb2.050 NOM..27 NOM. D D e L.200 BSC 0.8 BSC.0 BSC 2.5 BSC M N 0 0 Notes 2 2 SQ Notes: Pin # identifier shall be within shaded area shown. Pin diameter excludes solder dip finish. Dimension "M" defines matrix size. Dimension "N" defines the maximum possible number of pins. Orientation pin is at supplier's option. Controlling dimension: inch. A A A L A2 øb2 øb e D e CADEKA D Pin Identifier REV..0.2 /25/00

22 PRODUCT SPECIFICATION Mechanical Dimensions 0-Lead MQFP Package Symbol Inches Millimeters Min. Max. Min. Max. A.5.92 Notes A.0.25 A B , 5 C D/E D/E e.05 BSC.80 BSC L N 0 0 ND 0 0 α ccc Notes:. All dimensions and tolerances conform to ANSI Y.5M Controlling dimension is millimeters.. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be.08mm (.00in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot.. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness..20 (.008) Min. E D D PIN IDENTIFIER e 0.06" Ref (.60mm) L 0 Min.. (.005) R Min../.0 R.005/.0 C α E Lead Detail See Lead Detail A A2 Base Plane A B Seating Plane -Cccc LEAD COPLANARITY C 22 REV..0.2 /25/00

23 PRODUCT SPECIFICATION Ordering Information Product Number Temperature Range Speed Grade Screening Package Package Marking GC 0 C to 70 C 0 MHz Commercial 0 Pin Ceramic Pin Grid Array 2250AGC GC2 0 C to 70 C 0 MHz Commercial 0 Pin Ceramic Pin Grid Array 2250AGC2 GC 0 C to 70 C 50 MHz Commercial 0 Pin Ceramic Pin Grid Array 2250AGC H5C 0 C to 70 C 0 MHz Commercial 0 Pin Plastic Pin Grid Array 2250AH5C H5C2 0 C to 70 C 0 MHz Commercial 0 Pin Plastic Pin Grid Array 2250AH5C2 H5C 0 C to 70 C 50 MHz Commercial 0 Pin Plastic Pin Grid Array 2250AH5C H6C 0 C to 70 C 0 MHz Commercial 0 Lead Metric Quad Flatpack to Pin Grid Array H6C2 0 C to 70 C 0 MHz Commercial 0 Lead Metric Quad Flatpack to Pin Grid Array H6C 0 C to 70 C 50 MHz Commercial 0 Lead Metric Quad Flatpack to Pin Grid Array KEC 0 C to 70 C 0 MHz Commercial 0 Lead Plastic Quad Flatpack 2250AKEC KEC2 0 C to 70 C 0 MHz Commercial 0 Lead Plastic Quad Flatpack 2250AKEC2 KEC 0 C to 70 C 50 MHz Commercial 0 Lead Plastic Quad Flatpack 2250AKEC N/A N/A N/A /25/00 0.0m 002 Stock#DS A

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