A Nondestructive Self-Reference Scheme for Spin- Transfer Torque Random Access Memory (STT-RAM)

Transcription

1 A Nondestructive Self-eference Scheme for Spin- Transfer Torque andom Access Memory (STT-AM Yiran Chen, Hai (Helen Li*, Xiaobin Wang, Wenzhong Zhu, Wei Xu and Tong Zhang *ECE Department PolyTech nstitute of NYU Brooklyn, NY, USA Seagate Technology, Bloomington, MN, USA {yiran.chen, xiaobin.wang, wenzhong, ECSE Department ensselaer Polytechnic nstitute Troy, New York {xuw, Abstract We proposed a novel self-reference sensing scheme for Spin-Transfer Torque andom Access Memory (STT-AM to overcome the large bit-to-bit variation of Magnetic Tunneling Junction (MTJ resistance. Different from all the existing schemes, our solution is nondestructive: The stored value in the STT-AM cell does NOT need to be overwritten by a reference value. And hence, long write-back operation (of the original stored value is eliminated. The robustness analyses of the existing scheme and our proposed nondestructive scheme are also presented. The measurement results from a 16kb testing chip successfully confirmed the effectiveness of our technique. Keywords-spin-transfer torque; STT-AM; self-reference. NODUCTON The demands of high capacity nonvolatile memory exponentially increase due to the fast growth of the pervasive computing and handheld industry. Nevertheless, it is known that Flash memory (NAND and NO faces significant scaling challenges at 32nm technology node and beyond [1]. Magneto-resistive andom Access Memory (MAM is a promising candidate for next-generation nonvolatile memory: MAM features non-volatility, fast read/write speed (<1ns, virtually unlimited programming endurance (>1 15 cycles and zero standby power [2]. n MAM, Data storage is realized by switching the resistance of magnetic tunneling junction (MTJ between high-resistance state ( 1 and low-resistance state (. However, in conventional MAM that uses currentinduced magnetic field to flip the magnetization of MTJ [3][4], scaling the amplitude of the switching magnetic field at the scaled technologies is very challenging. A new MAM design, called Spin-Transfer Torque AM (STT-AM was recently invented [5][6][7]. STT-AM uses electrical current to flip the magnetization of MTJ. Because the switching current is proportional to the area of MTJ, STT- AM has a better scaling property than conventional MAM. However, STT-AM technology suffers from some yieldlimiting factors, such as the large MTJ resistance variation: For example, MTJ resistance increases by 8% when the thickness of oxide barrier in the MTJ changes from 14Å to 14.1 Å [8]. The MTJ resistance variation will be aggravated by the further reduction of oxide barrier thickness and the large MTJ geometry variation in scaled technology. Large MTJ resistance variation could lead to the false detection of read operation: when the low (high resistance state of an MTJ is higher (lower than the reference value, the content of the memory cell is always detected as 1 ( [9]. Hence, some self-reference schemes are proposed [7][1]: 1 sense the state of an MTJ and store the result (i.e., as a voltage level of a capacitor; 2 write a reference value to the MTJ; 3 sense the corresponding reference state of the MTJ and compare it to the stored result in step 1 to get the original MTJ state; 4 write back the original state to the MTJ. We note that such a self-reference scheme is destructive because the original MTJ state destroyed when writing the reference value into the MTJ. The original MTJ state could be lost if power is shut down before the write back operation completes. This raises the concerns about the chip reliability from non-volatility point of view. Also, the long read latency and the high power consumption of conventional self-reference scheme (mainly due to the two write steps are commercially impractical. n this paper, we propose a novel nondestructive selfreference scheme for STT-AM design. Although the original state of an MTJ still needs to be read twice, there is no need to write any reference value into the MTJ. Consequently, the long write back operation is avoided. Compared to the conventional self-reference scheme, our technique significantly improves the memory reliability and reduces the read latency. The organization of this paper is as follows: Section gives the basics of STT-AM and conventional self-reference scheme; Section describes our proposed nondestructive selfreference scheme; Section V presents the robustness analysis B Free Layer MgO eference Layer A (a B Free Layer MgO eference Layer A (b WL Figure 1. MTJ structure. (a Anti-parallel (high resistance state. (b Parallel (low resistance state. (c 1T1J STT-AM cell structure. BL SL (c /DATE1 21 EDAA

2 MTJ esistance (Ω ns pulse 24 DC extrapolation 22 2 H L Sensing Current (µa 1 Figure 2. The measured static - curve of an MgO-based MTJ. comparison between our nondestructive self-reference scheme and the conventional destructive one. Section V shows the experimental results. Section V concludes our work.. PELMNAY A. MTJ (Magnetic Tuneling Junction Basics An MTJ includes two ferromagnetic layers and one oxide barrier layer, e.g., MgO. When the magnetization directions of the two ferromagnetic layers are parallel (anti-parallel, MTJ is in low (high resistance state, as shown in Figure 1. n STT- AM design, the magnetization direction of one ferromagnetic layer (reference layer is fixed while the magnetization direction of the other ferromagnetic layer (free layer can be changed by passing a switching current polarized by the magnetization of reference layer [5]. Figure 2 illustrates the measured - sweep curve of an MgO-based MTJ with 9nm 18nm cell size, under a voltage pulse with 4ns pulse width. Some points missing from the 4ns pulse measurement are extrapolated based on DC (static measurement. When applying a positive voltage on point B in Figure 1, MTJ enters the positive voltage region in Figure 2 and switches from high resistance state to low resistance state. When applying a positive voltage on point A, MTJ enters the negative voltage region and switches the other way. Let L and H denote the low and the high MTJ resistances, respectively. We define the Tunneling Magneto esistance atio as TM = ( H - L / L. n addition, H, L and TM also depend on the read current (or voltage, as shown in Figure 2. n general, a larger TM makes it easier to distinguish the two resistance states of an MTJ. MgO-based MTJ s are widely used in present-day STT-AM design because of the higher TM (>1% than other materials, i.e., AlO (<3%. B. STT-AM Cell Basics The most popular STT-AM cell design is one-transistorone-mtj (or 1T1J structure [5][6] as shown in Figure 1(c, where one MTJ is connected to one NMOS transistor in series. The interconnects connected to MTJ, to the source (drain of NMOS transistor and to the gate of NMOS transistor are called as bit-line (BL, source-line (SL and word-line (WL, respectively. MTJ is usually modeled as a variable resistor in circuit schematic, as shown in Fig. 1(c [11]. n a conventional voltage sensing scheme for a STT-AM cell [9]. ead current is applied to generate the BL voltage: Low resistance state : V High resistance state : V BL,L BL,H = ( L = ( H or. Here L and H are the low and the high MTJ resistance at read current, respectively. is the resistance of NMOS transistor. V BL,L and V BL,H are the BL voltages when the MTJ is at low resistance state and high resistance state, respectively. By comparing BL voltage to a reference voltage V EF between V BL,L and V BL,H, the MTJ resistance state can be readout. f a V EF is shared by multiple STT-AM cells, it needs to satisfy: ( V V Min( BL, L EF VBL,H (1 Max < <. (2 Here Max(V BL,L and Min(V BL,H denote the maximal V BL,L and the minimal V BL,H generated by all involved STT-AM cells, respectively. Unfortunately, Max(V BL,L < Min(V BL,H may not hold true when the bit-to-bit variation of MTJ resistance is large. C. Conventional Self-reference Scheme 1 Operation of conventional self-reference To overcome the bit-to-bit variation of MTJ resistances, a so called self-reference sensing scheme was proposed [1], as shown in Figure 3: The drains of two switch transistors SLT1 and are connected to BL while the sources of them are connected to voltage storage elements, i.e., capacitors C1 and C2, respectively. The top connect points of C1 and C2 are also connected to a voltage sense amplifier. The operation of conventional self-reference scheme is: First read: A read current is applied to generate BL voltage V BL1, which is stored in C1. V BL1 can be either V BL,L1 or V BL,H1, which are the BL voltages when the MTJ is at the low resistance state or the high resistance state, respectively; Erase: Value is written into the same bit; Second read: Another read current (> is applied and generates BL voltage V B, which is stored in C2. Here is carefully chosen to make sure: V < V < V. (3 BL, L1 B BL,H1 The original value of STT-AM bit can be readout by comparing V BL1 and V B. Write back: The value readout in the previous step needs to be written back to the STT-AM bit. 2 ead current optimization Eq. (3 can be rewritten as: ( < < ( + + (4 L1 T Here L1 and are the resistances of MTJ at the low resistance state, at and, respectively. H1 is the resistance of MTJ at high resistance state, at. T and are the resistances of NMOS transistor, at and, respectively. We define the largest allowable read current that does not disturb the MTJ state as max. As we shall explain in Section V-A, we choose = max to maximize the sense margin. H1 T

3 VDD D_EN1 D_EN2 BL SLT1 V BL1 V B C1 C2 + - MTJ NMOS Transistor WL Decoder BL SL SLT1 C1 SenEn V BL1 + - V B V BO Output U D Data_Latch MTJ NMOS Transistor owdec ( ColDec SLT1 ( - The optimal that ensures the equal sense margins when the MTJ is at both high- and low-resistance states (or V BL,L1 V B = V B V BL,H1 can be calculated by solving: = + 2 ( ( Hmax + Lmax + 2T. (5 Here Hmax (or Lmax denotes the resistance difference when an MTJ at the high (or low resistance state is read at a close-to-zero read current and max, as shown in Figure 4.. NONDESUCTVE SELF-EFEENCE SCHEME A. Theory of Nondestructive Self-reference Scheme We noticed that the current dependence of the high and the low resistance states of an MTJ are quite different: the current roll-off slope of the high resistance state is much steeper than that of the low resistance state, as shown in Figure 2. This special characteristic of MgO-based MTJ s is the motivation of our nondestructive self-reference scheme. The conceptual schematic of our nondestructive selfreference scheme is shown in Figure 5. A switch transistor Hmax Output Figure 3. Conventional self-reference sensing scheme for STT-AM. H H1 L1 Lmax L ( max Figure 4. - curve in self-reference schemes. Figure 5. Schematic of nondestructive self-reference circuitry. SLT1 is connected to BL as well as the corresponding voltage storage element C1. The other switch transistor is connected to a voltage divider. Two inputs of a voltage sense amplifier are connected to the top connect point of C1 and the output of the voltage divider (V BO, respectively. The voltage ratio of the voltage divider α =V BO /V B. The operation of nondestructive self-reference scheme is: First read: A read current is applied to generate BL voltage V BL1, which is stored in C1. V BL1 can be either V BL,L1 or V BL,H1, which are the BL voltages when the MTJ is at the low resistance state or the high resistance state, respectively; Second read: Another read current (usually max, as we shall show in Section V-A is applied and generates BL voltage V B. We define the read current ratio β = /. Sensing: V BL1 and V BO are compared by the voltage sense amplifier. f V BL1 is significantly larger than V BO, the original value of STT-AM bit is 1 (high resistance state. Otherwise, the original value of STT-AM bit is (low resistance state. The explanation is as follows: f the original value of STT- AM bit is 1, we have: V V BL1 B = V = V BL,H1 BL, f we set α = 1/β, then V BO BL,O = = = V = α V = B ( H1 T =. (6. (7 Here H1 and are the resistances of MTJ at high resistance state, under read current and, respectively; and V BL,H1 and V BL, are the corresponding BL voltages, respectively. V BL,O is the output of voltage divider when MTJ is at high resistance state, under. f we assume T = =, then the sense margin for 1 is ( V (8 BL, H = VBL,H1 VBL,O = H1 > because H1 is significantly larger than.

4 Similarly, if the original value of STT-AM bit is, we have the sense margin for BL, L BL,L1 BL,O ( V = V V = (9 because L1 is close to (see Figure 2. Here V BL,L1 and V BL1, are the BL voltages when the MTJ resistance equals L1 or, respectively. V BL,O is the output of voltage divider when MTJ is at low resistance state, under. Compared to conventional self-reference scheme, our new self-reference scheme is nondestructive because it eliminates the erase and write back steps. The total read latency and power consumption are dramatically reduced accordingly. For simplicity, here we ignored the leakage current of the voltage divider and the resistance variation of. Usually we choose α =.5 (a symmetric structure of voltage divider to minimize the impact of process variation on our design. B. ead Current atio Optimization n practice, designing a circuit to detect two values, e.g., V BL,L1 and V BL,O, being equal is very difficult. nstead, we carefully chose to ensure V BL,H1 > V BL,O > V BL,O > V BL,L1. STT-AM bit is 1 when V BL1 > V BO, otherwise it is. The optimal β that ensures the equal sense margins when MTJ is at both high- and low-resistance states (or V BL,H1 V BL,O = V BL,O V BL,L1 can be calculated by solving: 1 = α β + V. + 2 L1 1 β ( Hmax + Lmax 1 + 2T OBUSTNESS ANALYSS. (1 There are three main factors significantly affect the effectiveness of the nondestructive self-reference schemes: the variation of read current ratio β, the shift of the NMOS transistor resistance under and, and the variation of voltage ratio α. We use the variation range of the above three factors for a nonzero sense margin of a STT-AM bit to measure the robustness of STT-AM self-sensing scheme. A. obustness Analysis of ead Current atio β 1 ead current selection of conventional self-reference The variation of β comes from the process variation of read current driver circuit. Based on Eq. (4, the read current ratio of conventional self-reference scheme needs to satisfy: ( L1 + ( H < < 1+, (11 where = T. Since the NMOS transistor works at linear region, approximately T = =. We have: ( L1 ( H1 1+ < β < 1+. (12 For multiple STT-AM bits, a valid β exists only if: L1 < H1 Max Min. (13 Eq. (13 shows that the conventional self-reference scheme is also more or less affected by the bit-to-bit variation of MTJ resistance, if multiple STT-AM bits are considered. 2 ead current selection of nondestructive self-reference The selection of read currents in our nondestructive selfreference scheme needs to ensure: < ( α +, (14a H1 T < ( +, (14b < ( α +. (14c L1 T Eq. (14b is always true. f we assume T = =, a solution of β can be found as long as: Here = L H 1+ < α β < 1+. (15 1 L = L1 = Lmax 1 and H = H1 β 1 1. A valid selection of β exists only if: β Hmax Lmax Hmax <. (16 Eq. (16 is always true for a normal MgO-based MTJ. For multiple STT-AM bits, a valid β exists only if: Lmax < Hmax Max Min. (17 Normally the left side of Eq. (17 is close to zero since Lmax. ncreasing the maximum read current can effectively increase the right side of Eq. (17 by reducing and increasing Hmax simultaneously. B. obustness Analysis of NMOS Transistor esistance Even working at the linear region, the resistance of the NMOS transistor in a 1T1J STT-AM cell still shifts under different read currents. n other word, >. 1 variation in conventional self-reference ecall Eq. (11, needs to satisfy: ( β 1 ( ( H1 < ( β 1 ( L < 2 variation in nondestructive self-reference From Eq. (14a and (14c, needs to satisfy: ( αβ 1 ( H < ( αβ 1 ( L <. (18. (19

5 TABLE. ELECCAL PAAMETES OF MTJ AND NMOS ANSSTO* MTJ parameters 25Ω 122Ω Hmax 6Ω Lmax 1Ω 917Ω Ι max(ι 2µA Parameters for conventional self-reference scheme H Ω L Ω H 18.2Ω L 1.8Ω β 1.22 Max. Sense Margin (mv 76.6 Parameters for nondestructive self-reference scheme H Ω L Ω H 317.8Ω L 5.3Ω β 2.13 Max. Sense Margin (mv 12.1 * Calculated based on the - curve of the typical device shown in Figure 2. C. obustness Analysis of voltage ratio α Process variation also results in the deviation of the voltage ratio α of voltage divider away from the designed value. We assume is the deviation of voltage ratio from the designed value. eplacing α in Eq. 14(a (c by α (1+, we have the range of for the correct read operation as: 1 L1 1 1 < < αβ αβ Here we assume T = =. H1 1. (2 We note that the capacitance variation of C1 and C2 does not affect the operation of conventional self-reference scheme. V. EXPEMENTAL ESULTS n our testing chip design, an auto-zero sense-amplifier with a built-in data latch is used to eliminate the influence of device mismatch in sense amplifier. The sizes of SLT1 and are carefully tuned to minimize the leakage current. There are 128 STT-AM bits on each bitline. The impedance of the voltage divider is ~ tens MΩ, which is significantly higher than that of STT-AM memory cell. Then the impact of the leakage current through the voltage divider is minimized. The measured parameters of a typical MTJ device (see Fig. 2 and the NMOS transistor are used in our simulations, as shown in TABLE. The maximum read current is set to 2µA, which is 4% of the switching current of MTJ (~5µA with 4ns write pulse width. The designed voltage Sense Margin (mv SM-Con SM1-Con SM-Nondes SM1-Nondes Valid β ratio for Con scheme -2 Valid β ratio for Nondes scheme / atio (β Figure 6. Selection of read current ratio β= /. Sense Margin (mv SM-Con SM1-Con SM-Nondes SM1-Nondes Allowable for Con scheme 8 4 Allowable for Nondes scheme (Ω Figure 7. obustness for NMOS transistor resistance. ratio α is set to.5, to minimize the impact of device mismatch and process variation. Figure 6 shows the relationship between the read current ratios β and the corresponding sense margins of two selfreference schemes. We assume there are neither NMOS transistor resistance shifting ( = nor voltage ratio variation ( =. SM and SM1 denote the sense margin of bits or 1, respectively. -Con and -Nondes denote the conventional self-reference scheme and our nondestructive scheme, respectively. Figure 7 shows the allowable variation of NMOS transistor resistance for two self-reference schemes and the corresponding sense margins. Here we assume α and β are at their designed values (see TABLE. The designed value of is set to 917Ω. ±13Ω variation tolerance range means 14.2% of, which is far beyond the normal process variation. Figure 8 shows the allowable variation of voltage ratio in our nondestructive self-reference scheme and the corresponding sense margins. Here we assume α is.5 and =. Based on our experience, the variation control of voltage ratio α is very difficult. n the design of our testing chip, the current ratio β of read current driver can be adjusted in testing stage to compensate the voltage ratio α variation. The robustness analyses of two self-reference schemes are summarized in TABLE. Figure 9 shows the timing diagram of our nondestructive self-reference scheme. Different read currents are applied to STT-AM cell by turning on STL1 or ST, respectively. The signal sensing is triggered by signal SenEn and the output of sense amplifier is latched by enabling signal Data_latch. Figure 1 shows the simulation results of our nondestructive self-reference scheme. The circuitry is implemented with TSMC.13µm technology. The leakage current of other Sense Margin (mv SM-Nondes SM1-Nondes Allowable α variation for Nondes scheme -1-6% -5% -4% -3% -2% -1% % 1% 2% 3% 4% 5% Voltage atio Variation Figure 8. obustness for voltage ratio.

6 TABLE. OBUSTNESS OF TWO SELF-EFEENCE SCHEMES Conventional Nondestructive Max. β Min. β ~1 2 Max. +468Ω +13Ω Min. -468Ω -13Ω Max. N/A +4.13% Min. N/A -5.71% unselected memory cells has been considered in our simulation. The whole read operation can complete in about 15ns. A 16kb testing chip is fabricated with TSMC.13µm technology. The measured sense margins of conventional sensing scheme, conventional destructive self-reference sensing scheme and nondestructive self-reference sensing scheme with optimized test configurations are shown in Figure 11. Assuring a sense margin about 8mV of the auto-zero sense amplifiers, about 1% of bits failed to be readout by conventional sensing scheme. However, both destructive and nondestructive selfreference schemes successfully sensed all measured bits. Additional capacitor at the end of BL increases the C delay and consequently, elongates the read latency. A high impedance voltage divider, however, does not change the Elmore delay of BL. Therefore, our 2 nd read usually is faster than that of conventional self-reference scheme. To achieve even faster output, a pre-charge stage may be needed. Nondestructive self-reference scheme has relatively tighter constraints on the device variations than that of conventional self-reference scheme. However, our technique has much faster read speed by eliminating two write steps (erase and writeback and shortening the 2 nd read step. The reliability of STT- AM is improved by maintaining the non-volatility. The sense margin and the robustness of nondestructive self-reference scheme can be improved by increasing the maximum allowable read current max (. The methods to increase max without affecting the memory reliability are beyond the scope of this research and will be discussed in the future work. V. CONCLUSON We proposed a novel self-reference read scheme of STT- AM to overcome the large bit-to-bit variation of MTJ resistance. Compared to conventional destructive selfreference scheme, our scheme does not need to erase the original value of STT-AM bit and eliminates the write back step. The non-volatility of STT-AM is maintained and the read latency is significantly reduced. The robustness analysis shows that our scheme requires restrict control on the device Figure 9. Timing diagram of nondestructive self-reference scheme. Figure 1. Simulation result of nondestructive self-reference scheme. variation and mismatch, with relatively small sense margin. EFEENCES [1] K. Kim and G. Jeong, Memory Technologies for Sub-4nm Node, Proc. of EEE nternational Electron Devices Meeting (EDM, Dec. 27, pp [2] nternational Technology oadmap for Semiconductor, 27. [3] M. Motoyoshi, et al., A Study for.18µm High-density MAM, Proc. VLS Symposium, 24, pp [4] Y. K. Ha, et al., MAM with novel shaped cell using synthetic antiferromagnetic free layer, Proc. VLS Symposium, 24, pp [5] M. Hosomi, et al., A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-AM, Proc. nternational Electron Device Meeting Tech. Dig., 25, pp [6] T. Kawahara, et al., 2Mb Spin-Transfer Torque AM (SPAM with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current ead, Proc. EEE nternational Solid-State Circuits Conference, Tech. Dig., 27, pp [7] H. Tanizaki, A High-density and High-speed 1T-4MTJ MAM with Voltage Offset Self-eference Sensing Scheme, Proc. EEE Asian Solid-State Circuits Conference, 26, pp [8] S. Tehrani et al., ecent Developments in Magnetic Tunnel Junction MAM, EEE Trans. Magn., vol. 36, pp , Sept. 2. [9] H. Li, et al., An Overview of Nonvolatile Memory Technology and The mplication for Tools and Architectures, Design, Automation & test in Europe Conference and Exhibition, Apr. 29, pp [1] G. Jeong et al., A.24-µm 2.-V 1T1MTJ 16-kb Nonvolatile Magnetoresistance AM With Self-eference Sensing Scheme, EEE Jour. of Solid-State Circuits, vol. 38, No. 11, Nov. 23, pp [11] Y. Chen et al., Design Margin Exploration of Spin-Torque Transfer AM (SPAM, Proc. ntl. Symp. On Quality Electronic Design, 28, pp Sense Margin for "" (mv Fail Pass Conv. Sensing Conv. Self-reference Nondestructive Self-reference Sense Margin for "1" (mv Figure 11. Sense margins for all sensing schemes