Phase Shifter Driver/Linearizer

Transcription

1 page 1 of 13 Revised December 27, 24 Phase Shifter Driver/Linearizer Phase shifter range has been chosen for this design to be ±7º at 79⅓ MHz = 2856 MHz/36 = GHz/144 A setting precision of ½ psec =>.139º or ~ 14º/2 1, so 1-bits covering the range of ±7º will give adequate precision. The general phase shifter set-up is shown below. A fraction of the input signal is coupled out, phase shifted and recombined with the main signal. 79 MHz Phase Shifter Schematic June 8, 24 IN ZDFC-1-2 CPL OUT 2 ZFSC-2-1W S 7 db 1 Lorch Phase Shifter VP S All connections are SMA adapters except indicated one which is a Tensolite length,.48 nsec delay Control Voltage V c Figure 1: 79⅓ MHz Phase Shifter Configuration Measurements with this configuration give a maximum sensitivity to the control voltage of 4 /V. Using this, the control voltage must be settable to 3.5 mv for ½ psec. For a DAC with 5 V full range this requires between 1 and 11 bits for the control.

2 page 2 of 13 Revised December 27, 24 EPROM s V s ADC A High D h DAC V d G + V c Low D l V off Figure 2: Phase Shifter Control Board Topology Topology Input V s from control system ranges from V sl to V sh If necessary there is an amplifier and added offset to match this to the ADC voltage range. The ADC output is latched and becomes the EPROM address. The address is Vs VsL An = Amax (1.1) V V This address is input into 2 EPROM's * which generate an address for the DAC, D, taking the non-linearity of the phase shifter into account. One EPROM generates the LSB's of D and the other generates the MSB's of D. D = D A (1.2) sh ( ) The DAC has a voltage range V dl to V dh. The DAC output voltage is D Vd = VdL + ( VdH VdL) (1.3) D max The DAC output is amplified with gain G and an offset V off is added to give the control voltage V c. Vc = Voff + GVd (1.4) * Two EPROM's are used because it is assumed that they will have 8-bit outputs so they can be programmed with the ARDB EPROM programmer. sl

3 page 3 of 13 Revised December 27, 24 Strategy Implemented in MATLAB script phaseshifter_design 1) Measure phase θ vs control voltage V c for a phase shifter configured as in Figure 1 using LabView program seventy_nine_mhz_daq, which is a DAQ interface for the program seventy_nine_mhz 2) Determine the phase offset, θ, as the phase at the maximum amplitude point. The phasors in the two inputs of the ZFSC-2-1W are aligned at this point. 1 Data & Selected Data 5 θ θ 5 Data Selected Data V c 12 Selected Data 1 Vc θ θ Figure 3: (Top) Raw data and selected data in a limited phase range. (Bottom) The selected data with V c as the dependent variable. * 3) Plot θ θ vs V c (Figure 3 top). Truncate the data for a limited phase range of close to the desired range of 14. 4) Treat θ θ as the independent variable, and express the input from the control system in terms of it * The sample figures are based on data taken for phase shifter AE1 and for a 12-bit ADC (AD788CN ) with V sh = 5V, V sl = -5V and a 12-bit DAC (AD8582) with V dh = 4.95 V and V dl =. Data file is AE1_41118_7 and the results file is AE1_linearized_41119_2.

4 page 4 of 13 Revised December 27, 24 θ θ VsH + VsL Vs = ( VsH VsL) + (2.1) θ 2 where θ is the full phase range. Convert this to ADC address by eq. (1.1). Amax An A θ = θ max + (2.2) θ 2 5) Fit the resultant curve with a polynomial as shown in Figure 4 to give the desired control voltage, which can be expressed in terms of the DAC output voltage N N n Vc Voff GVd pna n= 1 = + = (2.3) 12 Selected Data & Fit, < Residual > = V c Data Fit with n fit = residual ADC address Figure 4: Sample of data and fit for V c as a function of the ADC address 6) The DAC voltage and DAC address are V N c Voff 1 N n Vd = = pna Voff G G (2.4) n= 1 and N Dmax N n VdL D= pna Voff G (2.5) n= 1 VdH VdL 7) G is given by the requirement that the full range of voltages be covered Vc( A= Amax ) Vc( A= ) Vc( Vs = VsH ) Vc( Vs = VsL) G = = (2.6) V V V V dh dl dh dl

5 page 5 of 13 Revised December 27, 24 and the offset voltage is given by the requirement that Voff = Vc ( A= ) G* VdL = Vc ( Vs = VsL ) G* VdL (2.7) 8) Program the EPROM's using these values for V off and G and the polynomial coefficients, p n. 3 (AE lvm) DAC Address for Gain = 1.779, V off = Low Bytes V c (V s = 5V) = , V c (V s = +5V) = High Byte Address Figure 5: Low and High bytes for EPROM. Example of results For the phase shifter analyzed above, EPROM's were programmed with the data as indicated in Figure 5 and the gain and offset were adjusted by 1) setting V s = -5V and adjusting the offset to give V c = 4.177V 2) setting V s = +5V and adjusting the gain to give V c = 11.76V

6 page 6 of 13 Revised December 27, Phase Characteristic, < Residual > = θ Residual V s (V) Figure 6: Results for Phase Shifter AE1 The next pages show the results for the assembled AE1 and AE3 chassis

7 page 7 of 13 Revised December 27, 24 AE1 Characterization File = AE1_41118_7.lvm, Final results = AE1_assembled_41227_1.lvm) 9 Phase Characteristic, < Residual > = θ 8 data θ = 1.493V s Residual V (V) s

8 page 8 of 13 Revised December 27, 24 AE3 Characterization File = AE3_41214_3.lvm, Final results = AE3_assembled_41227_1.lvm) 9 Phase Characteristic, < Residual > = θ 8 data θ = V s Residual V (V) s

9 page 9 of 13 Revised December 27, 24 Labview Programs seventy_nine_mhz_daq and seventy_nine_mhz 6722 Board (-5V to + 1 V) - TENMA +5V Supply + Output to Phase Shifter ( to +15 V) Connection between NI 6722 board and 79 1/3 MHz phase shifter control 9/22/24 Figure: Connection between NI 6722 board and 79 1/3 MHz phase shifter control for measurement of phase shifter characteristic in the "+5V Boost" mode This program is used to measure the characteristic of the 79 MHz phase shifter. There are two modes of operation. In the "+5V Boost" mode, the output of channel ao of the 6722 board is connected to a TENMA supply as indicated above to change the output range of - 5 V to +1 V to to +15 V needed to drive the phase shifter. In the "No Boost Supply" mode the of channel ao of the 6722 board is to be used directly The control voltage is read through GPIB on channel 11 of an Agilent 3497A multiplexed multimeter. The RF phase and amplitude are measured with an HP 8753D network analyzer set up to measure S21 with a central frequency of MHz and span of 1 MHz. The results are an lvm file with the columns 1) time into measurement cycle 2) V s set point value (refer to figure 2) 3) measured V s 4) measured V c 5) measured amplitude in db 6) measured phase

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