description CLR CLK RCO A B C ENP GND ENT LOAD CLR CLK V CC Q A Q B A B NC C Q C Q D ENT RCO ENP GND LOAD

Transcription

1 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 Internal Look-head ircuitry for Fast ounting arry Output for n-it ascading Synchronous ounting Synchronously Programmable Package Optio Include Plastic Small-Outline () and Shrink Small-Outline () Packages, eramic hip arriers (FK), Standard Plastic (N) and eramic (J) IPs description These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting desig. The SN54LS162 is a 4-bit decade counter. The LS161, LS163, S161, and S163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when itructed by the count-enable (, ) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. buffered clock () input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. ecause presetting is synchronous, setting up a low level at the load (LO) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163...J PKGE SN74LS161, SN74S161, SN74S OR N PKGE SN74LS163...,, OR N PKGE (TOP VIEW) SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S FK PKGE (TOP VIEW) The clear function for the LS161 and S161 devices is asynchronous. low level at the clear () input sets all four of the flip-flop outputs low, regardless of the levels of the, LO, or enable inputs. The clear function for the SN54LS162, LS163, and S163 devices is synchronous, and a low level at sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applicatio without additional gating. and inputs and a ripple-carry () output are itrumental in accomplishing this function. oth and must be high to count, and is fed forward to enable., thus enabled, N GN N V GN N LO V Q Q Q Q LO N No internal connection Q Q N Q Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PROUTION T information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2000, Texas Itruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFIE OX LLS, TEXS

2 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 description (continued) produces a high-level pulse while the count is maximum (9 or 15, with Q high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Traitio at or are allowed, regardless of the level of. These counters feature a fully independent clock circuit. hanges at control inputs (,, or LO) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditio meeting the stable setup and hold times. The SN54LS161, SN54LS162, SN54LS163, SN54S161, and SN54S163 are characterized for operation over the full military temperature range of 55 to 125. The SN74LS161, SN74LS163, SN74S161, and SN74S163 are characterized for operation from 0 to 70. logic symbols LS161 N S161 INRY OUNTERS WITH IRET LER LS163 N S163 INRY OUNTERS WITH SYNHRONOUS LER LO TRIV16 T=0 M1 M2 G3 G4 5/2,3,4+ 3T=15 15 LO TRIV16 5T=0 M1 M2 G3 G4 5/2,3,4+ 3T= , 5 [1] [2] [4] [8] Q Q Q Q , 5 [1] [2] [4] [8] Q Q Q Q SN54LS162 EE OUNTER WITH SYNHRONOUS LER LO TRIV10 5T=0 M1 M2 G3 G4 5/2,3,4+ 3T= , 5 [1] [2] [4] [8] Q Q Q Q These symbols are in accordance with NSI/IEEE Std and IE Publication Pin numbers shown are for the,, J, and N packages. 2 POST OFFIE OX LLS, TEXS 75265

3 logic diagram (positive logic) SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 LO 9 SN54LS Q Q Q Q 1 6 Pin numbers shown are for the J package. POST OFFIE OX LLS, TEXS

4 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 logic diagram (positive logic) LO LS163 and S Q Q Q Q 1 6 Pin numbers shown are for the,, J, and N packages. LS161 and S161 synchronous binary counters are similar; however, is asynchronous. 4 POST OFFIE OX LLS, TEXS 75265

5 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 typical clear, preset, count, and inhibit sequences SN54LS162 The following sequence is illustrated below: 1. lear outputs to zero (SN54LS162 is synchronous) 2. Preset to 7 3. ount to 8, 9, 0, 1, 2, and 3 4. Inhibit LO ata Inputs Q ata Outputs Q Q Q sync lear Sync lear Preset ount Inhibit POST OFFIE OX LLS, TEXS

6 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 typical clear, preset, count, and inhibit sequences LS161, S161, LS163, and S163 The following sequence is illustrated below: 1. lear outputs to zero ( LS161 and S161 are asynchronous; LS163 and S163 are synchronous.) 2. Preset to binary ount to 13, 14, 15, 0, 1, and 2 4. Inhibit LO ata Inputs Q ata Outputs Q Q Q sync lear Sync lear Preset ount Inhibit 6 POST OFFIE OX LLS, TEXS 75265

7 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V V to 7 V Input voltage range, V I V to 7 V Package thermal impedance, θ J (see Note 1): package /W package /W N package /W Storage temperature range, T stg to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JES 51. recommended operating conditio SN54LS161 SN54LS162 SN54LS163 SN74LS161 SN74LS163 MIN NOM MX MIN NOM MX V Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current m IOL Low-level output current 4 8 m T Operating free-air temperature UNIT electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PRMETER TEST ONITIONS SN54LS161 SN54LS162 SN54LS163 SN74LS161 SN74LS163 MIN TYP MX MIN TYP MX VIK V = 4.5 V, II = 18 m V VOH V = 4.5 V to 5.5 V, IOH = 0.4 m V 2 V 2 V VOL V =45V 4.5 IOL = 4 m IOL = 8 m II V = 5.5 V, VI = 7 V m IIH V = 5.5 V, VI = 2.7 V µ IIL V = 5.5 V, VI = 0.4 V m IO V = 5.5 V, VO = 2.25 V m I V = 5.5 V m ll typical values are at V = 5 V, T = 25. The output conditio have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. UNIT V POST OFFIE OX LLS, TEXS

8 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 timing requirements over recommended operating conditio (unless otherwise noted) (see Figure 1) SN54LS161 SN54LS162 SN54LS163 SN74LS161 SN74LS163 MIN MX MIN MX fclock lock frequency MHz tw Pulse duration high or low LS161 low 20 15,,, LO LS161 tsu Setup time, before SN54LS162, LS163, UNIT LS161 inactive SN54LS162, LS163 low high th Hold time, all synchronous inputs after 0 0 switching characteristics over recommended operating conditio (unless otherwise noted) (see Figure 1) PRMETER FROM TO SN54LS161 SN74LS161 (INPUT) (OUTPUT) MIN MX MIN MX fmax MHz ny Q ny Q UNIT switching characteristics over recommended operating conditio (unless otherwise noted) (see Figure 1) PRMETER FROM (INPUT) TO (OUTPUT) SN54LS162 SN54LS163 SN74LS163 UNIT MIN MX MIN MX fmax MHz ny Q POST OFFIE OX LLS, TEXS 75265

9 recommended operating conditio SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 SN54S161 SN54S163 SN74S161 SN74S163 UNIT MIN NOM MX MIN NOM MX V Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current 2 2 m IOL Low-level output current m T Operating free-air temperature electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PRMETER TEST ONITIONS SN54S161 SN54S163 SN74S161 SN74S163 MIN TYP MX MIN TYP MX VIK V = 4.5 V, II = 18 m V VOH V = 4.5 V to 5.5 V, IOH = 2 m V 2 V 2 V VOL V = 4.5 V, IOL = 20 m V LO II V = 5.5 V, VI = 7 V m ll others LO IIH V = 5.5 V, VI = 2.7 V µ ll others LO IIL V = 5.5 V, VI = 0.4 V 1 1 m ll others IO V = 5.5 V, VO = 2.25 V m I V = 5.5 V m ll typical values are at V = 5 V, T = 25. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. UNIT POST OFFIE OX LLS, TEXS

10 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 timing requirements over recommended operating conditio (see Figure 1) SN54S161 SN54S163 SN74S161 SN74S163 UNIT MIN MX MIN MX fclock lock frequency MHz tw tsu Pulse duration Setup time, before high or low S161 low 10 8,,, 10 8 LO 10 8, 10 8 S161 inactive 10 8 S163 low high (inactive) 10 9 th Hold time, all synchronous inputs after 2 0 switching characteristics over recommended operating conditio (see Figure 1) PRMETER FROM TO SN54S161 SN74S161 (INPUT) (OUTPUT) MIN MX MIN MX fmax 65* 75 MHz (with LO high) (with LO low) ny Q * On products compliant to MIL-PRF-38535, this parameter is not production tested ny Q switching characteristics over recommended operating conditio (see Figure 1) PRMETER FROM TO SN54S163 SN74S163 (INPUT) (OUTPUT) MIN MX MIN MX fmax 65* 75 MHz (with LO high) (with LO low) ny Q * On products compliant to MIL-PRF-38535, this parameter is not production tested UNIT UNIT 10 POST OFFIE OX LLS, TEXS 75265

11 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 PRMETER MESUREM INFORMTION SERIES 54LS/74LS N 54S/74S EVIES V S1 7 V From Output Under Test L = 50 pf (see Note ) 500 Ω Test Point From Output Under Test L = 50 pf (see Note ) 500 Ω Test Point From Output Under Test L = 50 pf (see Note ) 500 Ω 500 Ω Test Point LO IRUIT FOR I-STTE TOTEM-POLE OUTPUTS LO IRUIT FOR OPEN-OLLETOR OUTPUTS LO IRUIT FOR 3-STTE OUTPUTS Timing Input 1.5 V 3 V 0 V High-Level Pulse 1.5 V 1.5 V 3 V 0 V ata Input tsu th 1.5 V 1.5 V 3 V 0 V Low-Level Pulse tw 1.5 V 1.5 V 3 V 0 V VOLTGE WVEFORMS SETUP N HOL TIMES VOLTGE WVEFORMS PULSE URTIONS Output ontrol (low-level enabling) Waveform 1 S1 losed (see Note ) Waveform 2 S1 Open (see Note ) tpzl tpzh 1.5 V 1.5 V 1.5 V tphz 1.5 V tplz VOLTGE WVEFORMS ENLE N ISLE TIMES, 3-STTE OUTPUTS 3 V 0 V 3 V VOL 0.3 V VOH 0.3 V 0 V Input In-Phase Output Out-of-Phase Output (see Note ) 1.5 V 1.5 V 3 V 0 V VOH 1.5 V 1.5 V VOL VOH 1.5 V 1.5 V VOLTGE WVEFORMS PROPGTION ELY TIMES VOL NOTES:. L includes probe and jig capacitance.. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control.. When measuring propagation delay items of 3-state outputs, switch S1 is open.. ll input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2, duty cycle = 50%. E. The outputs are measured one at a time with one input traition per measurement. Figure 1. Load ircuits and Voltage Waveforms POST OFFIE OX LLS, TEXS

12 SN54LS161, SN54LS162, SN54LS163, SN54S161, SN54S163 SN74LS161, SN74LS163, SN74S161, SN74S163 SYNHRONOUS 4-IT EE N INRY OUNTERS SS276 EEMER 1994 REVISE JULY 2000 n-bit synchronous counters PPLITION INFORMTION This application demotrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit (see Figure 3) can be used to implement a high-speed n-bit counter. The SN54LS162 counts in. The LS161, S161, LS163, and S163 devices count in binary. When additional stages are added, the f max decreases in Figure 2, but remai unchanged in Figure 3. lear (L) ount (H) isable (L) LO LS T=0 TR M1 G3 3T=MX G4 5/T,3,4+ lear (L) ount (H) isable (L) lock LO LS T=0 TR M1 G3 3T=MX G4 5/T,3,4+ Load (L) ount (H) isable (L) lock 1,5 Q Q Q Q Load (L) 1,5 Q Q Q Q LO T=0 TR M1 G3 3T=MX G4 5/T,3,4+ LO T=0 TR M1 G3 3T=MX G4 5/T,3,4+ 1,5 Q Q Q Q 1,5 Q Q Q Q LO T=0 TR M1 G3 3T=MX G4 5/T,3,4+ LO T=0 TR M1 G3 3T=MX G4 5/T,3,4+ 1,5 Q Q Q Q 1,5 Q Q Q Q LO T=0 TR M1 G3 3T=MX G4 5/T,3,4+ LO T=0 TR M1 G3 3T=MX G4 5/T,3,4+ 1,5 Q Q Q Q 1,5 Q Q Q Q To More Significant Stages fmax = 1/( to ) + ( to ) (N 2) + ( tsu) Figure 2. Ripple-Mode arry ircuit To More Significant Stages fmax = 1/( to ) + ( tsu) Figure 3. arry Look-head ircuit 12 POST OFFIE OX LLS, TEXS 75265

13 PKGE OPTION ENUM 10-Jun-2014 PKGING INFORMTION Orderable evice Status (1) Package Type Package rawing Pi Package Qty Eco Plan (2) Lead/all Finish (6) MSL Peak Temp (3) Op Temp ( ) TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to SNJ54LS 161FK evice Marking E TIVE IP J 16 1 T 42 N / for Pkg Type -55 to E SNJ54LS161J F TIVE FP W 16 1 T 42 N / for Pkg Type -55 to F SNJ54LS161W TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to SNJ54LS 163FK E TIVE IP J 16 1 T 42 N / for Pkg Type -55 to E SNJ54LS163J F OSOLETE FP W 16 T all TI all TI -55 to 125 JM38510/ TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to 125 JM38510/ JM38510/38001E TIVE IP J 16 1 T 42 N / for Pkg Type -55 to 125 JM38510/ 38001E JM38510/ TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to 125 JM38510/ JM38510/38002E TIVE IP J 16 1 T 42 N / for Pkg Type -55 to 125 JM38510/ 38002E M38510/ TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to 125 JM38510/ M38510/38001E TIVE IP J 16 1 T 42 N / for Pkg Type -55 to 125 JM38510/ 38001E M38510/ TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to 125 JM38510/ M38510/38002E TIVE IP J 16 1 T 42 N / for Pkg Type -55 to 125 JM38510/ 38002E SN54LS161J TIVE IP J 16 1 T 42 N / for Pkg Type -55 to 125 SN54LS161J (4/5) Samples SN54LS163J TIVE IP J 16 1 T 42 N / for Pkg Type -55 to 125 SN54LS163J SN54S163J OSOLETE IP J 16 T all TI all TI -55 to 125 ddendum-page 1

14 PKGE OPTION ENUM 10-Jun-2014 Orderable evice Status (1) Package Type Package rawing Pi Package Qty Eco Plan SN74LS161 TIVE SOI Green (RoHS & no Sb/r) SN74LS161R TIVE SOI Green (RoHS & no Sb/r) SN74LS161RE4 TIVE SOI Green (RoHS & no Sb/r) SN74LS161N TIVE PIP N Pb-Free (RoHS) (2) Lead/all Finish (6) MSL Peak Temp (3) Op Temp ( ) U NIPU Level UNLIM 0 to 70 LS161 U NIPU Level UNLIM 0 to 70 LS161 U NIPU Level UNLIM 0 to 70 LS161 evice Marking U NIPU N / for Pkg Type 0 to 70 SN74LS161N SN74LS161N3 OSOLETE PIP N 16 T all TI all TI 0 to 70 SN74LS161NSR TIVE SO NS Green (RoHS & no Sb/r) SN74LS163 TIVE SOI Green (RoHS & no Sb/r) SN74LS163R TIVE SOI Green (RoHS & no Sb/r) SN74LS163RE4 TIVE SOI Green (RoHS & no Sb/r) SN74LS163N TIVE PIP N Pb-Free (RoHS) U NIPU Level UNLIM 0 to 70 LS161 U NIPU Level UNLIM 0 to 70 LS163 U NIPU Level UNLIM 0 to 70 LS163 U NIPU Level UNLIM 0 to 70 LS163 U NIPU N / for Pkg Type 0 to 70 SN74LS163N SN74LS163N3 OSOLETE PIP N 16 T all TI all TI 0 to 70 SN74LS163NSR TIVE SO NS Green (RoHS & no Sb/r) SN74S161N TIVE PIP N Pb-Free (RoHS) SN74S161NSR TIVE SO NS Green (RoHS & no Sb/r) SN74S163 TIVE SOI Green (RoHS & no Sb/r) SN74S163N TIVE PIP N Pb-Free (RoHS) SN74S163NE4 TIVE PIP N Pb-Free (RoHS) U NIPU Level UNLIM 0 to 70 LS163 U NIPU N / for Pkg Type 0 to 70 SN74S161N U NIPU Level UNLIM 0 to 70 74S161 U NIPU Level UNLIM 0 to 70 S163 U NIPU N / for Pkg Type 0 to 70 SN74S163N U NIPU N / for Pkg Type 0 to 70 SN74S163N SNJ54LS161FK TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to SNJ54LS 161FK (4/5) Samples ddendum-page 2

15 PKGE OPTION ENUM 10-Jun-2014 Orderable evice Status (1) Package Type Package rawing Pi Package Qty Eco Plan (2) Lead/all Finish (6) MSL Peak Temp (3) Op Temp ( ) evice Marking SNJ54LS161J TIVE IP J 16 1 T 42 N / for Pkg Type -55 to E SNJ54LS161J SNJ54LS161W TIVE FP W 16 1 T 42 N / for Pkg Type -55 to F SNJ54LS161W SNJ54LS163FK TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to SNJ54LS 163FK SNJ54LS163J TIVE IP J 16 1 T 42 N / for Pkg Type -55 to E SNJ54LS163J SNJ54S161FK TIVE L FK 20 1 T POST-PLTE N / for Pkg Type -55 to 125 SNJ54S 161FK SNJ54S161J TIVE IP J 16 1 T 42 N / for Pkg Type -55 to 125 SNJ54S161J (4/5) Samples SNJ54S163J OSOLETE IP J 16 T all TI all TI -55 to 125 (1) The marketing status values are defined as follows: TIVE: Product device recommended for new desig. LIFEUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRN: Not recommended for new desig. evice is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: evice has been announced but is not in production. Samples may or may not be available. OSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/r) - please check for the latest availability information and additional product content details. T: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise coidered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/r): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of romine (r) and ntimony (Sb) based flame retardants (r or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Seitivity Level rating according to the JEE industry standard classificatio, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple evice Markings will be iide parentheses. Only one evice Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire evice Marking for that device. ddendum-page 3

16 PKGE OPTION ENUM 10-Jun-2014 (6) Lead/all Finish - Orderable evices may have multiple material finish optio. Finish optio are separated by a vertical ruled line. Lead/all Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and isclaimer:the information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers coider certain information to be proprietary, and thus S numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to ustomer on an annual basis. OTHER QULIFIE VERSIONS OF SN54LS161, SN54LS163, SN54S161, SN54S163, SN74LS161, SN74LS163, SN74S161, SN74S163 : atalog: SN74LS161, SN74LS163, SN74S161, SN74S163 Military: SN54LS161, SN54LS163, SN54S161, SN54S163 NOTE: Qualified Version efinitio: atalog - TI's standard catalog product Military - QML certified for Military and efee pplicatio ddendum-page 4

17 PKGE MTERILS INFORMTION 14-Jul-2012 TPE N REEL INFORMTION *ll dimeio are nominal evice Package Type Package rawing Pi SPQ Reel iameter (mm) Reel Width W1 (mm) 0 (mm) 0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74LS161R SOI Q1 SN74LS161NSR SO NS Q1 SN74LS163R SOI Q1 SN74LS163NSR SO NS Q1 SN74S161NSR SO NS Q1 Pack Materials-Page 1

18 PKGE MTERILS INFORMTION 14-Jul-2012 *ll dimeio are nominal evice Package Type Package rawing Pi SPQ Length (mm) Width (mm) Height (mm) SN74LS161R SOI SN74LS161NSR SO NS SN74LS163R SOI SN74LS163NSR SO NS SN74S161NSR SO NS Pack Materials-Page 2

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