Article Modeling, Analysis, and Realization of Permanent Magnet Synchronous Motor Current Vector Control by MATLAB/Simulink and FPGA

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1 Article Modeling, Analyi, and Realization of Permanent Magnet Synchronou Motor Current Vector Control by MATAB/Simulink and FPGA Chiu-eng ai *, Yao-Ting Tao and Chia-Che Tai Department of Electrical Engineering, National Chin-Yi Univerity of Technology, Taichung 41170, Taiwan; (Y.-T.T.); (C.-C.T.) * Correpondence: chiukl@ncut.edu.tw; Tel.: Received: 13 September 017; Accepted: 8 October 017; Publihed: 8 October 017 Abtract: n thi paper, we preent the modeling, analyi, and realization of current vector control for a permanent magnet ynchronou motor (PMSM) drive uing MATAB/Simulink and a field programmable gate array (FPGA). n AC motor drive ytem, mot of the current vector control are realized by digital ignal proceor (DSP) becaue of their complete and compact hardware function. However, the performance of drive ytem realized by low-cot DSP are limited by the hardware tructure and computation capacity, which may lead to the difficulty of reaching a fat enough repone, above all, for thoe motor with a mall electrical time contant. Therefore, we ue FPGA to peed up the calculation about the current vector control to attain a fat repone. Simulation and practical experimental reult are ued to verify the correctne and performance of the deigned full hardware ytem. eyword: vector control; DSP; FPGA; permanent magnet ynchronou motor; MATAB 1. ntroduction The rapid development of high-performance and low-cot digital ignal proceor (DSP) ha encouraged reearcher to deign motor drive with DSP. The functionality of a DSP i dependent on the demand for the particular reuirement and proceing peed. Since motor control uing DSP ha been widely developed by reearcher and indutry, C manufacturer have, thu, deigned and produced pecific DSP for motor control, uch a the T TMS30F8 erie DSP, Microchip dpc, etc. Thoe motor control cheme with DSP a the controller have advantage, uch a imple circuitry, oftware control, and flexibility in adaptation to variou motor control reuirement and application. However, it i important to have an inner current control loop with a hort time contant in order to obtain a rapid dynamic repone on velocity or poition control. To thi reuirement tated above, the calculation time to decide the deired witching pattern with the pace vector pule width modulation (SVPWM) trategy i reueted a hort a poible. Under thi conideration, the inherent propertie of DSP with euential proceing and oftware execution may make the ytem hardly reach the deired performance on the current loop control with high ampling freuency, e.g., 40 khz or above, epecially for a fixed-point DSP, or the developed algorithm without upport by the build-in hardware of DSP. Therefore, a DSP with a floating point proceor and high freuency clock i developed and ued; however, thi carrie a high price. Current feedback can be accomplihed by Hall enor or reitor, and ometime the analog inuoidal ignal i proceed by a low pa filter to remove the component, including thoe from modulation. However, phae lag and amplitude attenuation of the winding current from the Hall enor and the low pa filter hould be taken into conideration when the ytem i operated at high ampling freuency, which i cloed to the bandwidth of Hall current enor or low pa filter. Machine 017, 5, 6; doi: /machine

2 Machine 017, 5, 6 of 15 MATAB/Simulink, produced by the MathWork, nc., i often ued to the analyi and imulation for control purpoe, and the controller deign of modern power electronic and motor drive ytem by field programmable gate array (FPGA) ha become more and more important. Thu, MATAB/Simulink ha been ued a an alternative method to automatically generate a readable and portable EEE tandard compliant hardware decription language (HD) to realize the deired ytem which i generally and formerly built by DSP [1]. Sytem deign with MATAB/Simulink make complicated deign eaier. The deigner can eaily build and imulate their hardware control ytem by olving the conventional control problem with MATAB/Simulink. Of coure, ome, or even many, modification are needed to realize the developed hardware ytem on a elective FPGA. However, for reearcher, the hardware circuit deign tarting from MATAB/Simulink i another choice to horten the developing time. An FPGA i fully cutomizable, allowing a completely flexible deign which i cutom-made for the particular type of control technology. Furthermore, an FPGA i field programmable, and further functionalitie can be added anytime and anywhere when they are neceary []. FPGA-baed digital controller have, thu, been implemented uccefully in motor drive, uch a induction motor (M) [3], permanent magnet ynchronou motor (PMSM) [4 7], tepping motor [8], bruhle DC motor [9], and witched reluctance motor []. Additionally, FPGA are alo ued in the implementation of controller, uch a PD controller [10], fuzzy controller [4,11], tracking controller [8], and for the realization of SVPWM module [6]. n thi tudy, the procedure of deigning an FPGA-baed current vector control for a PMSM drive ytem i demontrated. The reuirement of the deign include the fat winding current repone, the realizable intellectual property (P) for vector control, and the complete interface and peripheral. At firt, the ytem i deigned via MATAB/Simulink on the ytem level, imulated by ModelSim, produced by Mentor Graphic Corporation, to evaluate the correctne, and converted into the Verilog HD code a a vector control P. Next, ome modification are made for the developed P ytem in order to be realizable by the pecific elected FPGA. To finih the deign of the hardware ytem, the interface for an analog to digital converter (ADC), digital to analog converter (DAC), erial/parallel converter, uadrature encoder pule (QEP) counter, SVPWM module, and digital filter for peed moving average and for encoder ignal are included in the deign. Finally, the deigned overall hardware circuit are applied to the PMSM drive ytem to practically evaluate the performance of the FPGA-baed ytem by howing the inuoidal teady-tate repone. Thi paper i organized a follow. n Section, the mathematical decription regarding the electrical circuit of PMSM motor are given. The imulated and experimental ytem deigned and created by MATAB/Simulink are hown in Section 3. n Section 4, the imulated reult baed on the ytem created in Section 3, and the experimental reult baed on the FPGA, power module, and PMSM motor are demontrated. Finally, the concluion are given in Section 5.. The Electrical Model of Permanent Magnet Synchronou Motor The typical mathematical model of a PMSM i decribed in the d-axi ynchronou rotating reference frame a follow [4]: where di dt di d R = id + ω e i + 1 vd (1) dt R = v and v d are the d- and -axi voltage; i the phae winding reitance; i d d d 1 λ f ωe id + v ωe d i and i d are the d- and -axi current; d and are the d- and -axi inductance, and () R

3 Machine 017, 5, 6 3 of 15 d = = ; ω e i the rotating peed of magnet flux; and λ f i the permanent magnet flux linkage. Generally, the current control of PMSM i baed on the vector control approach, and the generated torue,, can be repreented a: T e T e 3P = λ f i 4 Δ = i 3P where P i the pole number, and λ 4 generated torue i proportional to the -axi current under decoupling control. t t = f i the torue contant. (3) how that the 3. Analyi and Deign for PMSM Drive Sytem Baed on MATAB/Simulink 3.1. The Block Diagram of PMSM Drive Sytem A complete velocity control model created in MATAB/Simulink i hown in Figure 1, which include the three P controller (block A for peed control, block B for d-axi current control, and block C for -axi current control), the decoupling control (block D), the 3ϕ / ϕ coordinate tranformation (block E and F), and the PMSM model. n the tudy, we mainly conider the current loop controller deign, epecially the -axi one. The tructure of the enhanced current control loop i baed on a tandard field-oriented control, and the two voltage, v d and v in Euation (1) and (), for d- and -axi circuit are, repectively, determined from the two P controller (block B and C). Since the decoupling control i aumed, the parameter of the current loop P controller are deigned eparately. (3) Figure 1. The block diagram of imulated ytem for PMSM peed control. n thi tudy, the controller for current loop are excluively realized by FPGA. n order to reach the goal of fat current repone, all the component delay of the current loop are taken into conideration. The main delay are from the 1-bit ADC, the uadrature encoder pule (QEP) counter, and the SVPWM module, etc. The block diagram of vector control repreented by Verilog HD i hown in Figure, where the in/co look up table (UT), the two P controller, the four coordinate tranformation module and the SVPWM module are included. n Figure, ince the rotor i a permanent magnet, the d-axi command i et to zero. Additionally, the -axi command which i proportional to the deired torue i from the P controller of velocity control. The block named a encoder_cnt i the QEP counter, which provide the information of the rotor poition for

4 Machine 017, 5, 6 4 of 15 poition and velocity feedback, a well a coordinate tranformation. The input ignal of QEP are named a Z, P_A, and CW, which come from the encoder on the motor. n Figure, the blue block are operated at a 0 khz clock. 3.. The Deign of Hardware P Controller Figure. The block diagram of the current vector control. The P controller realized by FPGA firt come from the continuou ytem: C ( ) = i p + (4) where p and i are the parameter of the P controller. Euation (4) i digitalized by the backward difference method: 1 1 z = (5) T where T i the ampling time. To ubtitute Euation (5) into Euation (4), the reulting digital P controller i a follow: C ( z) = T 1 z i p + 1 (6) n Euation (6), the -control i with the iteration operation, and one limiter i added to the accumulator output to prevent aturation. Since the ampling freuency for current control loop i normally in the cale of 10 khz 0 khz, the ampling time i uite mall. Thu, to conider the reolution of parameter and avoid the truncated error, the variable are repreented in 3-bit number. The realized hardware P controller are hown in Figure 3 where the command (cmd) and ytem feedback (fb) are the input. The data bu i programmed a 3 bit, in which 15 bit for the integer part, 16 bit for the fractional part, and one bit for the ign bit. Additionally, in Figure 3, the

5 Machine 017, 5, 6 5 of 15 proce of the error ignal i in parallel (the P and action) to enhance the performance and reduce the calculation time. Figure 3. The realization of the hardware P controller The Clarke, Park, nvere Park, and nvere Clarke Tranformation To implement the function of Clarke, Park, nvere Park, and nvere Clarke tranformation, the in(θ) and the co(θ) table are created. Each of the element of the table i repreented a 3-bit number, with three bit for the integer part, 8 bit for the fractional part, and one bit for the ign bit. The index θ i from the encoder counter which i alo programmed a a 3-bit number The SVPWM Model The SVPWM module i built to obtain the deired voltage by outputting ix gate driver ignal, A1, A, B1, B, C1, and C, a hown in Figure, and more detail are hown in Figure 4. The period of SVPWM i et a 50 μ with a ymmetrical tructure, and the dead-time i et a 1 μ. n Figure 4, the control voltage, V d and V from P controller, are ued to generate the correponding witching pattern [6], example are hown in Figure 5, where Figure 5a indicate that the deired vector voltage i in Sector 1, and can be yntheized by the vector V 0, V 1, V, and V 7. The turn-on euence are hown in Figure 5b, where the active vector are V 1 and V, non-effective vector are V 0 and V 7, and: T + = T 0 + Ta Tb (7) where T 0 i the duration for the ytem in zero vector V (000) 0 and V 7 (111), T a for vector V (100) 1 and T b for vector V (110) in the condition of Figure 5b. The total active time i ( T + a T b ), and the duty cycle for thi condition i defined a: Ta + Tb Duty Cycle (%) = 100% T (8)

6 Machine 017, 5, 6 6 of 15 1 Vd fix3_en15 V fix3_en15 Sn: N : Vd fix3_en8 1/z fix3_en8 V Ta fix3_en8 C1 Rate Tranition4 C1 fix3_en8 fix3_en8 Tb 1/z C C fix3_en8 fix3_en8 Sn fcn C3 C3 fix3_en8 fix3_en8 To C4 Rate Tranition3 time_c C4 1/z fix3_en8 vector_time Rate Tranition ufix11 ufix3_en8 count -- Ta Tb uint8 time_int To fcn time_cnt time_int time_int Sn fcn pwm ufix1 1 A ufix1 A B ufix1 C B 3 C 3 N uint8 HD Counter Gain 1/z uint8 Rate Tranition1 Figure 4. The SVPWM module. The SVPWM ytem i conidered a having the larget hardware delay in the block diagram of Figure, and the value i 50 μ (0 khz ampling freuency). β V (1,1,0) V ref T T a V 1 T T b V (a) Sector1 V 1 (1,0,0) α T 0 Ta Tb T 0 T 0 Tb Ta T 0 V 7 V V 1 V 0 T T (b) Figure 5. The generation of pattern. V ref by SVPWM. (a) A vector voltage in Sector 1; and (b) the witching We deigned all the component eparately, and added D-F-F for thoe block marked by 1 μ for the ake of ynchronization. They are hown in Figure 6. Additionally, the ADC need 4 μ to convert the analog current ignal into digital value. By Figure 6, the total computation time to determine the duty cycle (Euation (8)) for the SVPWM module are 8 μ, which are

7 Machine 017, 5, 6 7 of 15 horter than the 50 μ of the SVPWM period. Thu, the total propagation time from the ADC to the entry of the SVPWM block could be omitted, i.e., the run time of 50 μ of the SVPWM period i ufficient to accomplih all of the calculation. n the tudy, the object i to obtain a cloed-loop current control ytem with bandwidth higher than 1 khz, which i euivalent to having a cloed-loop pole greater than 680 rad/. To thi reuirement, the electrical time contant of the motor tator winding, the choice of the current enor, the proceing of the current ignal, and the execution period of SVPWM to generate the control voltage are epecially taken into conideration. Among them, the SVPWM module i the greatet obtacle in the control loop due to the fact that it need the longet time to complete a cycling operation. The deign procedure are a follow. Modelim (Verilog HD code) * i P v v d 1u e to MATAB (1+50)u 6 to 3 SVPWM nverter i i d to e 1u 1u 3 to (1+4)u A/D converter * = i d 0 P in/co UT QEP 3 PMSM Figure 6. The vector control ytem to how the propagation delay. Auming the ytem i under decoupling control, the -axi euivalent cloed-loop control can be implified a hown in Figure 7. The tranfer function of -axi circuit i implified a: H )= Δ 1 and the cloed-loop relation of Figure 7 could be repreented a: * where to be determined. H 1 ( = (9) V + R p + i p = Δ ( ) = = * (10) R p i R p i p + i the -axi current command. n (10), there are one zero at i / ) i ( p and two pole * i v i Figure 7. The euivalent block diagram of the -axi cloed-loop current control. With the conideration to get a wide bandwidth repone, a large proportional gain of choen, and the ratio i made: p i

8 Machine 017, 5, 6 8 of 15 i p 0 (11) n Euation (11), the parameter p and i of the P controller are alo programmed a 3-bit number. With the etting, we could eaily obtain the deired reolution for the parameter of the controller. According to the aumption of Euation (11), Euation (10) can be implified a: Since the value of rewritten a: p * (1) R p i p / i greater than the value of i /, Euation (1) can be further p + R + p = + R + * (13) p p Regarding Euation (1) and (13), they how that the parameter p can mainly be ued to determine the bandwidth of the -axi circuit. Additionally, the control parameter of the d-axi can be obtained in the ame manner. The characteritic of Euation (1) i a econd-order band-pa filter, which ha the lower 3 db freuency and upper 3 db freuency. However, ince the lower 3 db freuency i mall enough to be omitted, the bandwidth of Euation (1) i very cloe to that of Euation (13). Due to the fact that the electrical circuit i operated at a higher freuency (the ampling freuency, f ), the approximation of Euation (13) i valid. t i noted that the hardware control ytem for the PMSM current vector control decribed in the paper may alo be ued for the current vector control of induction motor, except the command of the d-axi current, which will not be et to zero due to the tructure of the rotor. 4. Simulation, Experiment, and Dicuion Simulation and experiment are both done to how the performance of the deigned hardware control ytem. The characteritic of the PMSM motor are hown in Table 1. The number of pole i 10; the tator reitance and inductance are, repectively, 3.5 Ω and 13 mh [1]. The electrical time contant i about 3.71 m. A cloed-loop control with P controller a the kernel i ued to compenate the ytem, and the expected cloed-loop bandwidth i eual to, or greater than, 1 khz. To reach the goal, the p of the peed P controller i firt deigned according to Euation (13), and choen a p = 100 for thi ytem. The bandwidth of the euivalent current loop ytem i f 3dB = 500 Hz. The parameter of P controller are p = 100 and i = 0. 00, the ampling freuency i et a f = 0 khz, which i eight time the deired ytem bandwidth, and thi fit the criterion of digital ignal proceing. With the above-mentioned parameter, we have the euivalent ytem:

9 Machine 017, 5, 6 9 of * + (14) Table 1. The parameter of PMSM motor (FRS A). Pole 10 R 3.5 (Ω) 13 (mh) 4 J m (kg m 10 ) 0.70 m( Nm ec) (wb) T c(nm) 1.7 B 0 φ The correponding freuency repone of Euation (14) i hown in Figure 8 with MATAB, and the bandwidth i about.5 khz, which i greater than the deired 1 khz. A tated in the lat ection, Euation (1) i a band-pa ytem, and the freuency repone i hown in Figure 9. t i noted that, in the region of low freuency, the repone of Figure 8 i different from the one of Figure 9. Neverthele, the ytem i operated at f = 0 khz, which i far away from the lower 3 5 db freuency, which i about 5 10 rad/, and the repone for both ytem are very imilar. Figure 8. The freuency repone of Euation (14). The waveform of the command i from a previouly-built dicrete-type inuoidal ignal, which i programmed and tored in the memory of the FPGA, and all the data are 3-bit number. The FPGA ued to implement the ytem i made with an Altera Corp. model Cyclone EP3C10E144C8. Since the main object are focued on the inner current cloed-loop control to yield a fat repone with the dedicated ytem by SVPWM, the reult regarding the current loop of the -axi are the main component to be hown.

10 Machine 017, 5, 6 10 of The Simulation Reult Figure 9. The freuency repone of Euation (1). The imulation i firt performed on the MATAB/Simulink platform. Figure 10 and 11 are the imulation reult with the control block diagram a hown in Figure 1. To prevent aturation of the P controller and the PMSM drive, the amplitude of current command i et to 1 A. n the following, the reult for the command at 100 Hz and 1 khz inuoidal input are demontrated, repectively. Figure 10 how the reult at 100 Hz, where i cmd and id cmd are, repectively, the 100 Hz inuoidal command input, and i fb and id fb are the current feedback. The repone and command of the two figure are very cloe to each other. n Figure 10a, there i only a mall DC offet between the two trace, and in Figure 10b, the d-axi current i very mall, except for the tranient duration at tart. Furthermore, we et 1 khz inuoidal command a the input, and the current amplitude i alo approximately 1 A. Figure 11 i the imulated reult. A the point marked on Figure 11a of the -axi repone, the time delay i = ; it i euivalent to a phae lag15.1. Additionally, the difference of the amplitude between i cmd and i fb i very mall. Since the phae delay i le than 45, and nearly no amplitude drop off, the -axi euivalent circuit under feedback control, thu, ha a bandwidth greater than 1 khz. Figure 11b how that the d-axi current i till mall, except for the tranient duration hown in the reult of Figure 10b. (a)

11 Machine 017, 5, 6 11 of 15 (b) Figure 10. The imulated reult with 100 Hz inuoidal command. (a) -axi current command and repone; and (b) d-axi current command and repone. (a) (b) Figure 11. The imulated reult with 1 khz inuoidal command. (a) -axi current command and feedback; and (b) d-axi current command and feedback.

12 Machine 017, 5, 6 1 of The Experimental Setup and Reult The hardware etup for the implementation of the experiment i hown in Figure 1. t include an Altera FPGA-baed control board, a 1-bit erial ADC and erial DAC board, power module board, brake, and PMSM. Analog current of phae A and B are ened by reitor on the power module board without filtering, and are converted into digital value by erial ADC, AD7866, with unipolar multi-channel voltage input. The ADC are operated at a 50 khz ampling freuency, it feed back the digital value of the winding current to the controller in the FPGA by way of the erial to parallel interface. Additionally, the DAC are ued to convert the dicrete-type control variable (current of * i and i ) into analog waveform with the tranfer gain of 0.5 V/A, and hown on the digital ocillocope. Finally, we copy the waveform on the ocillocope and plot them in MATAB. Furthermore, the PMSM motor i haft-connected to a brake, and rotor i locked by the brake when operating with high-freuency command input. The current command ued in the imulation are alo ued for the experiment, and only the reult of the -axi current are hown. Figure 13 how the reult with an amplitude of 1 A and a freuency of 100 Hz. t how that the deigned repone nearly matche the command without phae delay and amplitude attenuation, i.e., it ha good tracking when it i operated at 100 Hz. t i worth noticing that the trigger time of Figure 13 i et at the center of the creen due to the fact that the data in the figure i from the digital ocillocope. Figure 14 i the reult with command 1 khz. Two point, ( ) and ( ), are choen to evaluate the phae delay and the correponding reult i Thi how that the repone ha only a light drop-off in amplitude and a mall phae delay compared to the command. Upon comparing the imulated and experimental reult, it i alo found that they are uite imilar to each other. Finally, the experimental reult how that the hardware ytem ha attained the expected performance with a bandwidth greater than 1 khz. Brake and load Power Module FPGA Board PMSM motor ADC and DAC Figure 1. The etup of the experimental ytem.

13 Machine 017, 5, 6 13 of 15 Figure 13. The experimental reult with a 100 Hz inuoidal input. 5. Concluion Figure 14. The experimental reult with a 1 khz inuoidal input. n thi paper, we have hown the analyi and hardware current loop controller deign with FPGA for a PMSM driver. The deign conider the executing and computation delay of the hardware ytem. The developing procedure tart from the ytem deign with MATAB/Simulink, and the built model i verified by Modelim. Moreover, the reulting Verilog HD code are modified to fit the elected FPGA. Finally, the developed ytem i realized on an Altera Cyclone FPGA, and evaluated by the PMSM drive ytem. The imulated and practical experimental reult how that the developed current loop vector control ytem with MATAB/Simulink ha been uccefully realized, and alo reveal a high dynamic repone. The bandwidth i greater than 1 khz. The etup ytem alo uccefully operate the current ytem reaching to khz a hown in Figure 15, where the repone ha a phae delay i approximately The digital hardware circuit for the controller deign are complicated when they are developed directly from the electronic deign automation (EDA) ytem. On the other hand, when the deign i tarted from platform like MATAB/Simulink, abvew, or other imilar tool, they make the deign eay. Of coure, it i neceary to optimize the created hardware circuit to make it an uable P.

14 Machine 017, 5, 6 14 of A/Div Figure 15. The experimental reult with a khz inuoidal command. Author Contribution: Chiu-eng ai and Yao-Ting Tao conceived and deigned the experiment; Yao-Ting Tao and Chia-Che Tai performed the experiment; Chiu-eng ai, Yao-Ting Tao, and Chia-Che Tai analyzed the data; and Chiu-eng ai and Yao-Ting Tao wrote the paper. Conflict of nteret: The author declare no conflict of interet. Reference 1. Siwakoti, Y.P.; Town, G.E. Deign of FPGA-Controlled Power Electronic and Drive Uing MATAB Simulink. n Proceeding of the EEE/ECCE, Melbourne, VC, Autralia, 3 6 June 013; pp , doi: /ecce-aia Stumpf, A.; Elton, D.; Devlin, J.; ovatt, H. Benefit of an FPGA baed SRM controller. n Proceeding of the EEE 9th Conference on ndutrial Electronic and Application (CEA), Hangzhou, China, 9 11 June 014; pp Rohit, B.C.; Patil, M.D.; Shah, D.; adam, A. FPGA mplementation of SVPWM Control Techniue for Three Phae nduction Motor Drive Uing Fixed Point Realization. n Proceeding of the 014 nternational Conference on Circuit, Sytem, Communication and nformation Technology Application, Mumbai, Maharahtra, ndia, 4 5 April 014; pp ung, Y.-S.; Tai, M.-H. FPGA-Baed Speed Control C for PMSM Drive with Adaptive Fuzzy Control. EEE Tran. Power Electron. 007,, ung, Y.-S.; Huang, P.-G; Chen, C.-W. Development of a SOPC for PMSM Drive. n Proceeding of the 47th EEE nternational Midwet Sympoium on Circuit and Sytem, Hirohima, Japan, 5 8 July 004; pp Quynh, N.V.; ung, Y.-S. FPGA-Realization of Fuzzy Speed Controller for PMSM Drive without Poition Senor. n Proceeding of the CCAS, Nha Trang, Vietnam, 5 8 November 013; pp. 78 8, doi: /ccas Zhang, G.Z.; Zhao, F.; Wang, Y.X.; Wen, X.H.; Cong, W. Analyi and Optimization of Current Regulator Time Delay in Permanent Magnet Synchronou Motor Drive Sytem. n Proceeding of the 013 nternational Conference on Electrical Machine and Sytem, Buan, orea, 6 9 October 013; pp Zhang, C.J.; Wu, X.J.; Zuo, X.Y. FPGA Soft-Core Baed Step Motor Driving. n Proceeding of the 010 nternational Conference on Electrical and Control Engineering, Wuhan, China, 5 7 June 010; pp Horvat, R.; Jezernik,.; Curkovic, M. An Event-Driven Approach to the Current Control of a BDC Motor Uing FPGA. EEE Tran. nd. Electron. 014, 61, ocur, M.; ozak, S.; Dvorcak, B. Deign and mplementation of FPGA-Digital Baed PD Controller. n Proceeding of the 15th nternational Carpathian Control Conference, Velke arlovice, Czech Republic, 8 30 May 014; pp

15 Machine 017, 5, 6 15 of Quang, N..; ung, Y.-S.; Ha, Q.P. FPGA-Baed Control Architecture ntegration for Multiple-Axi Tracking Motion Sytem. n Proceeding of the EEE/SCE, yoto, Japan, 0 December 011; pp , doi: /s Data heet of FRS400506A. Available online: ut_motor_brakeand_feather_key/0373 (acceed on 3 October 017). 017 by the author. icenee MDP, Bael, Switzerland. Thi article i an open acce article ditributed under the term and condition of the Creative Common Attribution (CC BY) licene (