NAC Measurement Technique on High Parallelism Probe Card with Protection Resistors

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, 2016 ISSN(Print) ISSN(Online) NAC Measurement Technique on High Parallelism Probe Card with Protection Resistors Gyu-Yeol Kim and Wansoo Nah Abstract In this paper, a novel time-domain measurement technique on a high parallelism probe card with protection resistors installed is proposed. The measured signal amplitude decreases when the measurement is performed by Needle Auto Calibration (NAC) probing on a high parallelism probe card with installed resistors. Therefore, the original signals must be carefully reconstructed, and the compensation coefficient, which is related to the number of channel branches and the value of protection resistors, must be introduced. The accuracy of the reconstructed signals is analyzed based on the varying number of channel branches and various protection resistances. The results demonstrate that the proposed technique is appropriate for evaluating the overall signal performance of probe cards with Automatic Test Equipment (ATE), which enhances the efficiency of probe card performance test dramatically. Index Terms Probe card, protection resistor, short defect isolation, automatic test equipment, channel sharing I. INTRODUCTION Semiconductor companies have been striving to reduce the cost of testing to manage the enormous growth of mobile solution devices. To reduce these costs and the period of a cycle, it is preferable to increase the Manuscript received Feb. 11, 2016; accepted Jul. 21, 2016 School of Electronic and Electrical Engineering, College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea {gyulkim, wsnah}@skku.edu parallel test capacity of the probe card rather than to purchase the expensive Automatic Test Equipment (ATE) [1-3]. The capacity of a high parallelism probe card is typically over 1,000 Device Under Test (DUT) at one time, and a large number of probes (about 60 thousands), are installed on a high parallelism probe card [4]. In addition, for mass production, several thousands of high parallelism probe cards are used. To minimize yield loss or efficiency degradation due to the poor quality of the high parallelism probe card, the evaluation technique of probe cards is an important technology for systematic management in the semiconductor device industry, i.e. chip makers. To effectively evaluate the performance of high parallelism probe cards, these techniques must be considered based on productivity [5]. There have been two techniques used for testing probe card measurements. One is the Special Jig method [6, 7], and the other one is the Needle Auto Calibration (NAC) technique [8, 9]. The special Jig method is an accurate measurement technique, but it is limited to co-evaluation with ATE due to the limited connection between ATE and the probe card through these jigs. Moreover, the productivity of Special Jig method is usually poor. The other method is the NAC probing technique. The co-evaluation with ATE and its high productivity are advantages, but the weakness of this technique could be the limitation of calibration for frequency domain measurements. This limitation could be overcome in part by introducing de-embedding techniques as described in [9]; however, when using the NAC technique for a high parallelism probe card, there is another drawback: the attenuation of signal amplitude due to the introduction of

2 642 GYU-YEOL KIM et al : NAC MEASUREMENT TECHNIQUE ON HIGH PARALLELISM PROBE CARD WITH PROTECTION protection resistors, which are used for short failure isolation. In this paper, to overcome this drawback, an NAC measurement technique on high parallelism probe card was characterized, and an amplitude compensation method for NAC measurements is proposed, which dramatically enhances the efficiency of probe card testing. ATE Connections PCB Relay PCB Caps Interposer Micro-Spring Decoupling Caps (a) II. PROTECTION RESISTORS OF A HIGH PARALLELISM PROBE CARD The levels of difficulty in probe card manufacturing processes are becoming increasingly more challenging due to the increase in the number of probe pins and the decrease in pad pitches and sizes. Thus, the probe card type has evolved from the cantilever type to the microelectro-mechanical systems (MEMS) type, as depicted in Fig. 1(a) [10-12]. As shown in Fig. 1, a high parallelism probe card typically consists of a printed circuit board (PCB), a multi-layered ceramic (MLC) substrate, and interposers. Moreover, to implement a high parallelism capacity of the probe card under the limited hardware resources of ATE, power and DC channels are split through several relay components, such as the Photo Metal-OxideSemiconductor (MOS) and Complementary MetalOxide-Semiconductor (CMOS) switches. The AC channels, such as clock, address, DQ, and command pins, are split without relays for better signal integrity (SI) [13]. AC signals in branched channels typically have two drawbacks. Firstly, signal integrity (SI) degrades as the number of split channels increases due to the increase of impedance mismatching and cross talk [14, 15]. Secondly, if one of the split lines has a short-circuit defect, all shared (branched) lines could malfunction as illustrated in Fig. 2, because there are no relays used in the AC channels, which could isolate the short-circuit defect. Therefore, the failed line should be effectively isolated from the rest of the DUTs to direct the right signals to the normal lines that are located around the failed line. To solve this problem, resistors can be placed into each split channel, as shown in Fig. 3. These are referred to as protection resistors (PRs) [14, 16]. Note that this isolation technique is different from the isolation circuits of manifold junction type multiplexers in band pass filters [17]. ATE Connections Stiffener Stiffener Relays (CMOS, FPGA, Photo-MOS) (b) MEMS Probe MLC Capacitors Protection resistors PCB (c) Fig. 1. High parallelism probe card. A probe card consists of a PCB, stiffener, relays, interposers, multi-layered ceramic substrate, and an MEMS probes (a) Structure of high parallelism probe card, (b) Top view of high parallelism probe card, (c) Bottom view of high parallelism probe card.

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, A Seed DUT Fig. 2. An example of a merged failure of a 14-branch probe card. Thirteen DUTs (brown DUTs) failed due to the one shorted defect die (a seed DUT in the picture in red). Fig. 4. Picture of MEMS Probe arrays of which the beam length is about 1600 um long. The red-colored inset is an enlarged view of the tip area of MEMS probe. The tip size is about 8.5 um by 8.5 um with a 60 um pitch, as shown in blue. Fig. 3 shows that it is possible in a six-branched AC channel to isolate short defects using protection resistors because the transferred voltage level increases from the grounded level in case 2 (Red) to the somewhat decreased amplitude in case 3 (Pink), even if it happens to have short defects. The transferred voltage, V PR, is represented as (1), V PR = V ATE R æ R è æ R è ö ø PR ç N SHORT ö ø PR ATE + ç N SHORT (1) (a) where V ATE is the input voltage of ATE Driver, R ATE is the output resistance of ATE Driver, R PR is the resistance of protection resistors, N SHORT is the number of shorted channel. III. NAC PROBING TECHNIQUE ON A HIGH PARALLELISM PROBE CARD WITH PROTECTION RESISTORS (b) Fig. 3. Short defect isolation using protection resistors (a) An example of a six-branched channel with six protection resistors, (b) Simulated Eye diagram of DUT1: Case1 (Blue) with no short defect, Case2 (Red) with one short defect in DUT6 without PRs and Case3 (Pink) with one short defect in DUT6 with PRs. To characterize the whole electrical characteristics of a probe card, MEMS probes (needles) should be included in the measurement; however, as shown in Fig. 4, it is difficult to probe the MEMS probe due to its small size (length: ~1600µm and tip: ~8.5µm by 8.5µm). Moreover, the pitches between signal and ground MEMS probes vary from 50µm to several hundred micrometers due to the irregular pad arrangement; however, these difficulties

4 644 GYU-YEOL KIM et al : NAC MEASUREMENT TECHNIQUE ON HIGH PARALLELISM PROBE CARD WITH PROTECTION Fig. 6. Insertion Loss of the NAC plate. S21 of an NAC plate is about -0.3 db at 1 GHz. Fig. 5. Geometrical dimension of an NAC plate with three pads. Pad pitch is 8,000 µm horizontally and 2,000 µm vertically. do not affect the NAC probing technique because probing is automatically executed by a prober machine [9], and the feasible probing pitch is as wide as 560µm, as shown in Fig Specification and Frequency Characteristics of the NAC Plate The NAC plate has three pads; pad pitch is 8,000µm horizontally and 2,000µm vertically as shown in Fig. 5. The core of each pad is made of tungsten carbide for strengthening its durability, and it is surrounded by a type of glass insulator. The probing needle is set in contact with the core of a pad. Other pins with ground needles are set in contact with the top surface of the NAC plate, which is plated in nickel to implement a two-wire transmission line structure. The S21 of an NAC plate is about -0.3 db at 1 GHz as shown in Fig. 6, which is a good characteristic for the measurement of a high parallelism probe card. 2. NAC Measurement System Fig. 7 shows the configuration of an NAC measurement on a high parallelism probe card. The analyzing structure consists of an NAC plate connected to a Tektronix DSA70404 oscilloscope through an RF Fig. 7. Configuration of the NAC measurement system to evaluate the performance of a probe card with ATE(T5380). The NAC plate is installed in the P12XLm Prober. cable. The ATE, T5380 Model of Advantest, is used as the input source. The signal specification of the ATE is: the maximum frequency of MHz, the rise time of 250 ps, the resolution of 7.32 ps, and the driver skew of ±135 ps. 3. Amplitude Attenuation by Protection Resistors Fig. 8 shows the measured waveforms by the NAC plate at 50 MHz and 2 V input voltage with and without branched channels. The circuit diagrams of the two NAC measurement cases are shown in Fig. 9. In the case of PIN2, a three-branch channel, the needle of the PR1branch is measured by an NAC plate, and the other two needles of the PR2 and PR3 branchs are grounded because those pins are in contact with the surface of an

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, in (2); however, with branched channels, a compensation coefficient (β) is required to predict the output voltage, VOUT2, as in (3) to (5). The compensation coefficient, which is used for reconstructing the measured waveform by the NAC measurement to its original waveform, is shown in (6). Contact resistance is neglected because it could be controlled under one Ohm through needle polishing and the value of the PRs is large at 200 Ohms or 300 Ohms, VOUT 1 = VATE Fig. 8. Measured signals from the NAC measurement. PIN1 is un-branched, and PIN2 is a three-branched channel of Fig. 9. ROSC RATE + ROSC (2) REQ = ( ( RPR + ROSC ) RPR R PR ) = = RPR * ( RPR + ROSC ) N * RPR + ( N - 1) ROSC 3RPR + 2 ROSC (b) Fig. 9. Two cases of NAC measurement (a) Pin1 with nobranched channel, (b) Pin2, which has a three-branched channel with protection resistors installed. NAC plate that is grounded, as shown in Fig. 9(b). This configuration describes the case of two short-defects on an NAC measurement. In this case, the amplitude of the measured signal is attenuated, but its rise time does not change [18] because only the total resistance changes. The voltage attenuation of each channel is dependent on the number of channel branches and PR values as described in (2) ~ (6). (2) shows the simple relationship between the two voltages without branched channels and (3) to (5) represent the modified voltages on branched channels. The output voltage, VOUT1, can be easily predicted by the ratio of the two resistors, as can be seen REQ RATE + REQ REQ (4) ROSC RPR + ROSC (5) RATE + REQ RPR + ROSC VATE = VOUT 2 REQ ROSC (6) VOUT 2 = VATE b= (3) RPR * ( RPR + ROSC ) VEQ = VATE (a) N =3 RATE + REQ where VATE is the input voltage of the ATE Driver, RATE is the output resistance of the ATE Driver, RPR is the resistance of the protection resistors, ROSC is the resistance of the termination resistor in the oscilloscope, N is the number of channel branches, REQ is the equivalent resistance of the two PRs and one PR plus ROSC. IV. RESULTS AND DISCUSSIONS 1. Short Defect Isolation of Protection Resistors Short defect isolation of protection resistors works well when the transferred amplitude (VPR) of (1), which is related to the input voltage, the resistance of protection resistors, and the number of short defects, is higher than the input threshold voltage (VIH) of DUT. The input voltage margin (VIM) is calculated as in (7). VIM is expected to be proportional to the value of the protection

6 646 GYU-YEOL KIM et al : NAC MEASUREMENT TECHNIQUE ON HIGH PARALLELISM PROBE CARD WITH PROTECTION Table 1. Input voltage margin of four cases with RPR=200 Ω, RATE=50 Ω, VATE=2.2 V, and VIH=1.2 V Expected VIM Measured VIM RPR NSHORT VPR 200 Ω V 0.56 V 0.6 V 200 Ω V 0.27 V 0.3 V 200 Ω V 0.06 V 0.0 V 200 Ω V V -0.2 V Fig. 11. Equivalent circuit of DQ channel with protection resistors under the read operation with no-short-defect. The termination voltage of ATE, VT, was set as the half voltage of VDDQ. ZPC and ZATE are the characteristic impedances of channel of probe card and ATE, respectively. In DC analysis, the effect of ZPC and ZATE could be ignored. Fig. 10. An enlarged picture of an evaluation probe card: PR 200 Ω, PR 300 Ω, and PR 400 Ω. (a) Without PR (b) With PR resistor and to be inversely proportional to the number of short defects. Fig. 12. Shmoo of the read data of the DQ channel with VDDQ=1.3 V, VT=0.65 V, RON=75 Ω, RT=50 Ω, and PR=200 Ω. VIM = VPR - VIH short defect, the amplitude of the data out signal at the comparator of ATE decreases due to the protection resistor and the on-resistance of the DQ buffer of a device as (8), as shown in Fig. 11. Fig. 12 shows that the amplitude of data-out decreases about 200 mv from 910 mv to 710 mv. Therefore, for the branched I/O channel, the protection resistors are not effective in isolating the short defects. (7) Table 1 shows that the results of the input level margin evaluation with an evaluation probe card, as shown in Fig. 10, which implements various protection resistors and short defects are well correlated with the measured and the expected input voltage margin of (1). In the case of 200 Ω of protection resistors, it could properly isolate up to two short defects. 2. Limitation of Protection Resistors It has been shown that implementing protection resistors into branched AC channels is quite effective in isolating short defects; however, this solution may not be appropriate for a DQ pin with Write and Read operation. In Write mode, protection resistors act well as previously described, but in Read mode, even though there is no VOUT _ PR _ DQ = (VDDQ - VT ) RON RT + VT + RPR + RT (8) 3. Effectiveness of the NAC Probing Measurement Fig. 13 depicts three measured signals by an NAC plate on three un-branched channels with different protection resistors: 200 Ω, 300 Ω, and 400 Ω are inversely proportional to the resistance of protection

7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, Fig. 13. Measured voltage with three PR values: 200 Ω, 300 Ω, and 400 Ω on un-branched channels with 2 V and a 100 MHz signal. The amplitude of the measured signal using the NAC probing technique is inversely proportional to the resistance of protection resistors. Fig. 15. Comparison of the measurement (recovered signal) and the simulation model of the probe card at 2 V and a 100 MHz signal. Fig. 14. Recovered waveforms of Figure 13; β of PR 200 Ω, PR 300 Ω and PR 400 Ω are six, eight and ten as (7) with N=1, R OSC =50 Ω, R ATE =50 Ω. resistors as described in (5). With R OSC =50 Ω, R ATE =50 Ω and N=1, the V OUT of PR 200 Ω is calculated as 0.33 V, the V OUT of PR 300 Ω is 0.35 V and the V OUT of PR 400 Ω is 0.20 V by using (3) ~ (5). These signals can also be recovered well using the compensation coefficient (β) of (6), as shown in Fig. 14, in which three PR cases are calculated with six, eight, and ten. This illustrates the effectiveness of the signal compensation method on the attenuated measurement signal using the NAC probing technique on a high parallelism probe card with protection resistors. 4. Time-domain Evaluation with an NAC Probing Measurement Using the NAC probing technique on a high parallelism probe card, it is possible to verify the Fig. 16. Comparison of the two recovered signals of probe cards Vendor A and Vendor B at 1.14 V and 200 MHz signal of the T5380 Test System. Without the compensation technique, the absolute performance comparison of the two probe cards from different vendors could be impossible. accuracy of the simulation model of the probe card channel, as shown in Fig. 15. Moreover, the electrical characteristics of the probe cards of different vendors can be effectively compared, as shown in Fig. 16. This proposed time domain measurement technique is inevitable not only for the qualification of new probe cards but also for the inspection process at reception. V. CONCLUSIONS In this paper, a novel time-domain measurement technique, known as the NAC probing technique, on a high parallelism probe card with protection resistors is described. Using protection resistors in a branched AC channel, it is possible to isolate short-defects even when there are several short defects due to the input level

8 648 GYU-YEOL KIM et al : NAC MEASUREMENT TECHNIQUE ON HIGH PARALLELISM PROBE CARD WITH PROTECTION margins acquired; however, in the case of the branched I/O channel, a protection resistor is not appropriate for the short defect isolation solution because the data out signal decreases by its resistive circuit configuration even though there is no short defect. The signals obtained in the proposed NAC probing technique were decreased due to the protection resistors; it has been shown that the amplitude attenuation is effectively reconstructed through compensation coefficients, which are related to the number of channel branches and other factors. It has been concluded that the overall signal transfer characteristics of all wafer test infrastructures could be evaluated quite effectively in the time domain using the proposed method. ACKNOWLEDGMENT This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(msip) (No. 2016R1A2B ). REFERENCES [1] J. Rivoir, Parallel Test Reduces Cost of Test More Effectively Than Just a Cheap Tester, IEEE/SEMI Int l Electronics Manufacturing Technology Symposium, July, [2] M. Huebner, Highest Parallel Test for DRAM Enabled through Advanced TRE, IEEE SW Test Workshop, June, [3] K. Eom, D. Han, Y. Lee, H. Kim, S. Kang, Efficient Multi-site Testing Using ATE Channel Sharing, Journal of Semiconductor Technology and Science., vol 13, June, [4] The International Technology Roadmap for Semiconductors: Test and Test Equipment Section.. [5] F. C. Gale, Productivity Factors in Measurement Technology, IEEE Trans. Instrumentation and Measurement., vol 33, no. 3, pp , Sep.,1984. [6] H.J. Kim, J.K. Yu, J. Kim, J.B. Oh, H.D. Lim, W. Nah, Prediction of Signal Transfer Characteristic of Probe Card Using Electro-Magnetic Solvers, IEEE Int l symposium on Antenna, Propagation and EM theory, Nov., [7] D.Y. Kim, J. Byun, S.H. Lee, S.J. Oh, K.S. Kang, H.Y. Lee, Signal Integrity Improvements of a MEMS Probe Card Using Back-Drilling and Equalizing Techniques, IEEE Trans. Instrumentation and Measurement., vol 60, no. 3, pp , March, [8] I. Hitoshi, N. Atshshi, I. Naoka, O. Kotaro, Cantilever Type Probe Card for At-Speed Memory Test on Wafer, IEEE VLSI Test Symposium, May, 2005 [9] G.Y. Kim, E.J. Byun, K.S. Kang, Y.H. Jun, B.S. Kong, Wafer-Level Chacterization of Probecards using NAC Probing, IEEE International Test Conference, 2008 [10] J.H. Lee, B.H. Jo, A Comparison of Scrub Marks & Contact Resistance Between Cantilever Type and New MEMS Type Probe Cards, IEEE SW Test Workshop, June, 2003 [11] T. Homorodi, R. Martin, High Parallelism Memory Test Advances based on MicroSpring Contact Technology, IEEE SW Test Workshop, June, 2001 [12] B.H. Kim, J.B. Kim, J.H. Kim, A Highly Manufacturable Large Area Array MEMS Probe Card Using Electroplating and Flipchip Bonding, IEEE Trans. Ind. Electron., vol 56, no. 4, pp , April, 2009 [13] M. Huebner, Highest Parallel Test for DRAM Enabled through Advanced TRE, IEEE SW Test Workshop, June, 2009 [14] Y.H. Liu, N. Kawamata, K. Taoka, High Throughput Challenges for 300mm Wafer Testing, IEEE SW Test Workshop, 2003 [15] M. Sindhadevi, M. Kanagasabai, H. Arun, A. K. Shrivastav, Signal Integrity Analysis of High Speed Interconnects In PCB Embedded with EBG Structures, Journal of Electrical Engineering & Technology, vol 10, Jan [16] C. A. Miller, M. E. Chraft, R. J. Henson, Intelligent Probe Card Architecture, U.S. Patent , Dec., 2007 [17] H. Lee, T. Itoh, Isolation Circuits Based on Metamaterial Transmission Lines for Multiplexers, Journal of Electromagnetic Engineering and Science, vol 13, Sep [18] H. Johnson and M. Graham, High-Speed Signal Propagation, Advanced Black Magic, Prentice Hall, 2003

9 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, Gyu-Yeol Kim was born in Geojae, Korea, in He received his B.S. degree in electrical engineering from Kyunghee University, Suwon, Korea, in 2000 and his M.S. degree in electrical engineering from Sungkyunkwan University, Suwon, Korea, in He is currently working toward a Ph.D. degree in electrical engineering at Sungkyunkwan University. His current research interests include memory probe card design and signal integrity (SI) and power integrity (PI) in memory probe cards. Since 2000, he has been with Samsung Electronics, where he is a Research Engineer of wafer test and probe cards. He became a Member of IEEE Industrial Electronics Society in 2014 and a Member of IEEE Instrumentation and Measurement Society in Wansoo Nah received his B.S., M.S., and Ph.D. degrees from the Electrical Engineering Department of Seoul National University, Korea, in 1984, 1986, and 1991, respectively. Since 1995, he has been with Sungkyunkwan University in Korea, where he is currently a professor in the College of Information and Communication Engineering. He was a guest researcher at the Super-conducting Super Collider Laboratory (SSCL) in the United States from 1991 to He was also a senior researcher at Korea Electrical Research Institute (KERI) in Chang-won, Korea, from 1991 to His primary interests are electromagnetic interference / compatibility (EMI/EMC) analysis, and signal/power integrity (SI/PI)-aware electric/electronic circuit analysis and design.