Millimeter Wave Electronics. Spring Assignment Week 7-8 Power Amplifier Design. Due: Tuesday, June 10, 9:45 11:45 a.m.

Transcription

1 EE-711 Millimeter Wave Electronics Spring 24 Assignment Week 7-8 Power Amplifier Design Due: Tuesday, June 1, 9:45 11:45 a.m. Bo Zhao Ping Chen

2 1. Requirements and parameters Zg and Z L impedance of 5 Ohm. Frequency of operation: 6.2 GHz; Substrate e r =3.27; thickness: 15 mils; Strip thickness:.15 mil; sigma: 5.813e7; tand:.1; Design the necessary input and output matching networks. You can try either distributed elements or use lumped elements. Simulate your final amplifier circuitry in ADS. Draw a scaled drawing of the layout including the bias networks. Present in class your design and simulated results and layout. 2. Design procedure and results A) FET DC Bias point and bias circuits We choose HP-ATF26884 as our transistor. Fig. 1 is the DC I-V Curves, and fig. 2 gives the ADS suggested bias point for class A power amplifier. We choose our bias point at V DS = 3. V, I DS = 18 ma and V GS = -.6 V. 5 Device I-V Curves 4 VGS=. VGS=-.2 DC.IDS.i, ma VGS=-.4 VGS=-.6 VGS=-.8 VGS=-1. VGS=-1.2 VGS=-1.4 VGS=-2. VGS=-1.8 VGS= VDS= 3. VDS DC.IDS.i=.18 VGS=-.6 Fig. 1 Fig. 2

3 The biasing and decoupling circuit is shown in Fig. 3. sc_atc_7_cdr11bp_f_ C8 PART_NUM=ATC7A621FCA15 62pF sl_act_ais1812_m_ L4 PART_NUM=AIS1812-1RM 1 uh sc_atc_7_cdr11bp_f_ C5 PART_NUM=ATC7A621FCA15 62pF V_DC SRC2 Vdc=3. V P1 pf _hp_atf26884_ A16 sc_atc_7_cdr11bp_f_ C7 PART_NUM=ATC7A621FCA15 62pF sl_act_ais1812_m_ L3 PART_NUM=AIS1812-1RM 1 uh P2 sc_atc_7_cdr11bp_f_ C6 PART_NUM=ATC7A621FCA15 62pF (a) V_DC SRC1 Vdc=-.6 V Fig. 3 (b) Here we use a 62 pf block capacitor and 1 uh RF chokes to ensure proper isolation of bias circuit at 6.2 GHz. This also gives us better gain and noise figure compared to other values. B) S-parameter simulation S-Parameters, Noise Figure, Gain, Stability, Circles, and Group Delay versus Frequency Term Term1 Z=Z amplifier X1 Term Ter Z=Z S-PARAMETERS S_Param SP1 Start=4 GHz Stop=8 GHz Step=.1 GHz CalcNoise=yes Set System Impedance Z: Var VAR VAR1 Z=5 Set S-parameter analysis frequency range. If an S-parameter file without noise data is used, the noise simulation results will be invalid. Options Options1 Temp=16.85 Tnom=25 OPTIONS Computation of Stability factors and circles: Meas Meas meas1 Fig. 4 S-parameter simulation schematic

4 Fig. 4 is the S-parameter simulation results. From which we can see the transistor is potentially unstable. Maximum Available Pow er Gain, db Matching For Gain Simultaneous Match Zsource. + j. Zsource Zload DUT* Simultaneous Match Zload. + j. Stability Factor.76 System Impedance 5. Matching For Noise Figure, db.936 Zopt for j17.9 Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF j19.8 Pow er Gain w ith these Source and Load Reflection Coefficients Source Reflection Coefficient for Minimum NF.759 / Zopt Conjugate match Zload if source impedance is Zopt DUT* *DUT= Device Under Test (simulated circuit or dev ice) (a) output then conjugately matched), and GHz = and Noise Figure with Z 6.2GHz nf (2)= Fig. 4 (b) Now we want to design the two stage amplifiers. 1) First stage pre-amplifier We want the first stage amplifier to have minimum noise figure. From fig 4(a), we have, Г S = Z opt * = j17.9, and Г L with be conjugate matched to Z out = 9.5 j19.8. By doing this, we can reach the minimum noise figure of.936 db and power gain G T = db. 2) Second stage power amplifier For second stage amplifier, the noise figure is less important. So we want to design it for

5 maximum available gain and balance between gain, stability and noise figure. In fig. 5 we can see the blue available power gain circles and brown noise figure circles. For the Г S on each circle, it will give same available power gain or noise figure. The red circle is the source stability circle. And since S11<, the region outside the source stability circle is stable. When we move Г S to the point marked as GammaS in fig 5(a), we can get high gain and still good noise figure. Then we can calculate Г out and have load impedance conjugate matched with this. Since the Г out and Г L are conjugate matched, the transducer power gain will equal to available power gain around 14 db. Available Gain & Noise Circles, Source Stability Circle Source Gamma. Corresponding Load Gamma, (Black Dot) Noise_circleMin Noise_circles GammaLopt GAcircles Source_stabcir[mRF,::] rhos GammaS ns figure=1.136 gain= ns figure=1.336 gain= ns figure=1.536 gain= gain=1.593 indep(rhos) (. to 2.) indep(source_stabcir[mrf,::]) (. to 51.) cir_pts (. to 51.) indep(gammalopt) (139. to 139.) indep(noise_circlemin) (. to 51.) Fig 5(a) Noise Figure (db) with Source Impedance at marker GammaS Source Impedance at marker GammaS Optimal load impedance for Transducer Power Gain, db power transfer when source when these source and impedance at marker GammaS load impedances are used is presented to input j j Fig 5(b)

6 C) Input and output matching networks From part B), we know both Г s and Г L for the pre-amplifier and second stage transistor. With this information, it s easy to design input and output matching networks using single-stub microstrip line. The results are showed in fig 6 (low noise pre-amplifier) and fig 7 (second stage power amplifier). Here we give both schematic and S-parameter results. P2 P1 DA_SingleStubMatch1_MinNoiseAmp DA_SingleStubMatch1 F=6.2 GHz Zstub=5 Ohm Zline=5 Ohm Rg=5 Ohm Lg=1 nh Cg=1 pf Zg=(5+j*5) Ohm RL=1 Ohm LL=1 nh CL=1 pf ZL=(7.74-j*17.9) Ohm amplifier X1 DA_SingleStubMatch2_MinNoiseAmp DA_SingleStubMatch2 F=6.2 GHz Zstub=5 Ohm Zline=5 Ohm Rg=5 Ohm Lg=1 nh Cg=1 pf Zg=(9.5-j*19.8) Ohm RL=5 Ohm LL=1 nh CL=1 pf ZL=(1-j*1) Ohm Fig. 6(a) pre-amplifier matching network schematic (single-stub transmission line) output then conjugately matched), and f req= 6.2GHz = and Noise Figure with Z 6.2GHz nf (2)= Fig. 6(b) pre-amplifier matching network simulation results (single-stub transmission line) Matching For Noise Figure, db.936 Conjugate Match Load Zopt for j85.7m Impedance if Source Reflection Coefficient is Sopt for Minimum NF 5. - j2.55m Power Gain with these Source and Load Reflection Coefficients Source Reflection Coeff icient for Minimum NF.1 / Zopt Conjugate match Zload if source impedance is Zopt DUT* *DUT= Device Under Test (simulated circuit or dev ice) Fig. 6(c) Noise figure do reach minimum noise figure

7 P1 MLIN TL1 MTEE Tee1 L= mil W1=35.3 mil W2=35.3 mil W3=35.3 mil MLOC TL3 L= mil amplifier X1 MSub MSUB MSub1 H=15 mil Er=3.27 Mur=1 Cond=5.813E+7 Hu=3.9e+34 mil T=.15 mil TanD=.1 Rough= mil MLIN TL2 L= mil MTEE Tee2 W1=35.3 mil W2=35.3 mil W3=35.3 mil MLOC TL4 L= mil P2 Fig. 6(d) pre-amplifier matching network schematic (single-stub microstrip line) output then conjugately matched), and GHz = and Noise Figure with Z 15 1 f req= 6.2GHz nf (2)= Fig. 6(e) pre-amplifier matching network simulation results (single-stub microstrip line) We can see the noise figure and gain degrade somehow, may need some small optimization. output then conjugately matched), and GHz = and Noise Figure with Z 2 m4 6.2GHz 1 nf (2)=1.184 m Fig. 7(a) second stage transistor matching network simulation results (single-stub transmission line)

8 output then conjugately matched), and GHz = and Noise Figure with Z GHz nf (2)= Fig. 7(a) second stage transistor matching network simulation results (single-stub microstrip line) D) Wilkinson power divider This is the one we designed before. The schematic and simulation results are shown in fig. 8. MSub MSUB MSub1 H=15 mil Er=3.27 Cond=5.813e7 MLIN T=.15 mil TL1 TanD=.1 L=1 mil P1 Var MCURVE MTEE VAR Curve1 Tee2 VAR1 MLIN L1= mil TL4 W=19.3 mil W1=19.3 mil L3=8.76 mil Angle=9 W2=35.3 mil L2=L1/ *2 Radius=L2 W3=19.3 mil L=1 mil P2 MTEE TFR Tee1 R1 W1=19.3 mil W=2 mil W2=19.3 mil L=4. mil W3=35.3 mil Rs=5. Ohm Freq= Hz MCURVE Curve2 W=19.3 mil Angle=9 Radius=L2 MTEE Tee3 W1=35.3 mil W2=19.3 mil W3=19.3 mil MLIN TL5 L=1 mil P3 Num=3 (a) (b) -1 m1 6.2GHz db(s(1,1))= db(s(3,3)) db(s(2,2)) db(s(1,1)) m1 db(s(3,2)) db(s(3,1)) db(s(2,1)) Fig. 8 Schematic, layout and simulation results of Wilkinson power divider

9 E) Final schematic and simulation As shown in fig. 9, some further work in layout need to be done. As can be seen in the layout, the transistor, block capacitor and feed inductor are all piled together. S-Parameters, Noise Figure, Gain, Stability, Circles, and Group Delay versus Frequency P1 Term Term1 Z=Z MinNoiseMatch X2 wilkinson_divider X1 MaxiumGainMatchNew X3 MaxiumGainMatchNew X4 wilkinson_divider X5 Term Ter P2 Z=Z S_Param SP1 Start=4.5 GHz Stop=7.5 GHz Step=.1 GHz CalcNoise=yes S-PARAMETERS Set System Impedance Z: Var VAR VAR1 Z=5 Set S-parameter analysis frequency range. If an S-parameter file without noise data is used, the noise simulation results will be invalid. OPTIONS Options Options1 Temp=16.85 Tnom=25 Computation of Stability factors and circles: Meas Meas meas1 SMT_Pad SMT_Pad Pad1 L=3 mil PadLayer="cond" SMO= mil SM_Layer="cond" PO=-1 mil "SMT_Pad" is used to generate layout artwork only. THIS COMPONENT IS NOT USED IN SIMULATION. If parasitic effects from the pads need to be included, they can be added as shunt capacitances or the pads can be modeled using MLOC open-circuit microstrip elements. (a) output then conjugately matched), and GHz -1 = and Noise Figure with Z m5 6.2GHz nf (2)=1.4 m (b) (c) (d) Fig 9 Schematic (a), simulation results (b), layout (c) of final amplifier (d) gives some detailed picture of pad, SMT capacitor, the FET transistor etc.