Original Procedure by University of South Florida, Modified by Baylor University.

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1 1 ELC 4384 RF/Microwave Circuits II Spring 2018 Final Design Project: Design, Simulation, and Testing of a Low-Noise Amplifier Due Thursday, April 26, 12:30 p.m. Note: This procedure has been adapted from the final design project created and written by Dr. Tom Weller at the University of South Florida for the RF/Microwave Circuits II course. Description This project will involve the design of a low-noise amplifier using a bipolar junction transistor. You will design matching and bias networks, likely using lumped element methods, to satisfy the specifications provided. The design method will be based on simulation in Agilent Advanced Design System (ADS) using parasitic models for the passive components and a nonlinear transistor model from Modelithics, Inc. You will begin by simulating a simple design and then increase the level of complexity in your simulations to include the parasitic component models and microstrip transmission-line elements. Each student will complete an individual design with different specifications from the other designs in the class. Following successful simulations of the design, the designs will be fabricated and laboratorytested. Special attention should be paid to ensuring measured-versus-simulated agreement between the simulation results and the laboratory measurements. Schedule and Deliverables The project will consist of three design reviews and a final report. The preliminary design review will consist of a brief presentation detailing the design meeting the specifications with ideal component values. For the critical design review, simulation results should be shown for all specifications for simulation schematics including all parasitic models and microstrip transmission-line elements. The final design review will involve the presentation of measurement and simulation data with respect to the specifications. The final report will consist of a presentation of the final design, along with comparisons between measured and simulated data. Tentative Schedule: Project Assigned: Tuesday, March 13 Preliminary Design Review: Tuesday, March 27 Critical Design Review: Thursday, April 12 Final Design Review: Thursday, April 26

2 2 Final Report Due: Thursday, April 26, 12:30 p.m. To assist in completing the design on time, the following schedule will be followed: Friday, April 13: Submit layout files to the TA for board milling and order components. Friday, April 13 Tuesday, April 17: TA milling of boards, receive components Tuesday, April 17 Thursday, April 19: Assemble and test amplifiers. Undergraduate and Graduate Student Differences of the Project Students taking the course for graduate credit are required to complete all steps: design, simulation, and measurement. Students taking the course for undergraduate credit are required to complete only the design and simulation. If you complete the measurement step, you can earn up to 20 percent extra credit (i.e. completion of the full project can give you up to 120/100 points). Project Details The transistor to be used for this project will be the Infineon BFP420 NPN BJT. A datasheet for this part will be made available to you. The design will be performed on a 31 mil FR4 substrate. The parameters of your substrate are shown as follows: PCB Board Parameters: Board Thickness (mils) Dielectric Loss Tangent Metal Thickness Constant (Copper, mils) FR Passive Components: Passive components are limited to resistors, capacitors, and inductors, and may be selected from only the following series: Modelithics P/N Body Style: Vendor Vendor P/N Value Range (EIA) (mm) CAP-ATC (1608) ATC 600S pf CAP-ATC (2012) ATC 600F 0.1 pf 240 pf IND-CLC (1005) Coilcraft 0402CS nh IND-MUR (1608) Coilcraft 0603CS nh 001 RES-KOA (2012) KOA Speer RK73B2A 0 22K Ohms

3 3 You may end up using arbitrary values for passive RLC components in your initial designs. However, for your final design, you must use only the discrete part values that are available for each component. For each model, the second page of the data sheet displays these available part values. The RLC component models are available from the Modelithics library installed within ADS in the Baylor computers. These models are part of the Modelithics CLR Library that Modelithics has donated to Baylor for our use. You must add these libraries to your simulation profile in order to use them, as will be demonstrated in class. The Infineon BJT model is available in the Modelithics NLT library, which is also a palette within ADS. Modelithics has donated their NLT library for our use. The model in the library includes the effects of the transistor package. Other details may be obtained by viewing the datasheet. LNA Design Specifications You will be assigned one of three design types. The specifications for each design type are given in the following table: Specification Design #1 Design #2 Design #3 Board Type FR4 FR4 FR4 Center Frequency (GHz) % Bandwidth Gain (db) 14 +/ / /- 1.5 Max Noise Figure (db) Input Return Loss (db) >10 >10 >12 Output Return Loss (db) >10 >10 >20 Stability Unconditional Unconditional Unconditional Z0 (Ohms) Design Code As a goal, all specifications should be met over the entire designated bandwidth. Feedback and/or resistive loading may be required in some cases to achieve unconditional stability. If you cannot meet one or more specifications, provide adequate justification regarding why you feel you were not able to meet the specifications, what trade-offs you felt you needed to make, and what approaches you attempted in order to solve the problem. In addition, if specifications are not met, the design should be optimized to give the largest value of the design factor D, defined for this project as where G D min F L out,min max

4 4 G min is the minimum gain (in db) in the specified frequency range L out, min is the minimum value of the output return loss (in db) in the specified frequency range F max is the maximum noise figure (in db) in the specified frequency range. Of course, the requirement of unconditional stability should be maintained while optimizing this metric. If you are close to meeting a specification and give a suitable justification regarding why you did not meet the specification, you will be less likely to lose points. It may be difficult to obtain unconditional stability and still meet the more important specifications of gain and noise figure. Your schematic (and eventual layout) must be configured with the input on the left, the output on the right, and the bias network connection on top. When you design the complete bias network that includes microstrip interconnects (see below), you should add a 20 mil-wide, 1 cm-long line extending upward from the last (or first depending on how you look at it) lumped component. Also, on the RF input and RF output ports of the amplifier, include 1-cm long, 50-Ohm lines that will run to the edge of the PC board. The DC supply must consist of a single, 3 V source. Project Report Requirements Your project report must contain the items listed below. You must use section headings as given below (for example: Section 2: Design Summary, etc.). All necessary schematics and data plots should be included, each with a caption containing an appropriate level of detail (e.g. Figure 1 is not adequate; the caption must describe what is shown in Figure 1) and referenced in the body of the report (do not just add a collection of plots without referring to them in your report). A large percentage of your total project grade depends on the quality of your reporting. For most plots, you should show data from 0.5 to 3 GHz and use markers as well as a drawn-in box to indicate the low and high end of your design frequency band. The report format is as follows: 1. Title Page (including your name) 2. Design Summary give a 1 to 2 paragraph summary of the project objectives, design approach, and results. Include a table with your design specifications. 3. Stability Analysis. In this section you should show the analysis of the transistor stability and the steps you have taken to achieve unconditional stability.

5 5 4. Gain, Noise Figure, and Input/Output Match Analysis. Describe the preliminary design, including the source and load reflection coefficients at the center frequency that you targeted for your amplifier. 5. Design Using Ideal Components. Performing all of the steps in this section is strongly suggested but not required. If you choose not to complete every step, then you still need to include the section heading and insert a comment that you elected not to complete this step. a. Input/Output Matching Network Design b. Bias Network Design a bias network using ideal RLC components and a single +3 V supply. c. Complete Schematic (with ideal bias network) d. Simulated Performance. Show at least one graph for each of the design specifications. e. Compliance Matrix. Show a table as above (for your design only) that indicates the design goals and the design performance actually achieved by your simulations. 6. Design Using Full Parasitic Models. It is strongly suggested that if you transition from ideal component models to the Modelithics RLC models (the suggested approach), you first perform a series 2-port S-parameter sweep of each model (and part value) you expect to use and compare the response to that of an ideal element. In general, because of parasitic effects, the value needed with a full parasitic model is less than that needed from an ideal model. a. Stability Analysis. Verify that the design is unconditionally stable when using the Modelithics CLR component models, all microstrip interconnects, and discontinuoities (bends, tee-junctions, crosses, vias, etc). b. Input/Output Matching Network Design. Show the design process and resulting design for the matching networks using the Modelithics RLC component models, microstrip interconnects, and discontinuities (bends, tee-junctions, crosses, vias, etc.) c. Bias Network. Design and simulate a single 3V supply bias network using the Modelithics RLC component models, interconnects, etc. d. Complete Schematic. Show the complete schematic for the amplifier with all microstrip elements and models in place. If the complete schematic is not legible when inserted into your report, break it into pieces so that the details are clearly visible. e. Simulated Performance. Show at least one graph for each of the design specifications. f. Compliance Matrix (Similar to previous section) g. Physical Layout. Use the Schematic Capture feature in ADS to generate a layout image and include this in your report. Note the overall x-y dimensions in the figure caption.

6 6 7. Measurement Results (required for graduate students, optional/extra credit for undergraduate students) a. S-Parameter Comparisons. Include plots that compare the measured and model simulation performance for S11, S12, S21, and S22 for the entire circuit. Comment on the results. b. Noise Figure. If noise figure measurements are made, the results should be included in the report. Comment on the differences between measurement and simulation. You do not need to put measured and model data on the same graph (for example, you could use Excel to plot the measured data if that is simpler). 8. Summary. Provide a short (1-2 paragraph) conclusion giving comments about your project. 9. ADS Project Directory. a. Submit a compressed (.zap or archived ) version of your ADS project directory. b. Please try to name your schematics in a logical way (for example, Input_Match_Ideal, Input_Match_Real, etc.) and include a list of important schematics and a brief (1- sentence) description as an Appendix to your report. c. You will not receive a grade if the project directory is not submitted.

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