Design of Frequency Synthesizer at 400 MHz Band

Transcription

1 Design of Frequency Synthesizer at 400 MHz Band PD Loop Filter F r V d V C VCO F VCO F VCO /N PLL IC 1/N Fig. 1 Block Diagram of Frequency Synthesizer. 1. VCO - Colpitts Type at VHF/UHF Band - Nonlinear Model of BJT available Harmonic Balance Analysis employed - Design by Nonlinear Analysis Method Output Power, Oscillation Frequency, Phase Noise and Harmonic Characteristics are predicted. BJT used in the design : 2SC4226

2 Tee10 Tee11 MLIN TL2 W=0.8 mm L=0.8 mm V_DC SRC1 Vdc=5 V sr_avx_cr_21_j_ R14 sr_avx_cr_21_j_ R15 R R13 PART_NUM=CR21-122J 1.2 kohm PART_NUM=CR21-821J 820 Ohm R=5.1 Ohm Term Term1 Num=1 Z=50 Ohm sl_tok_ll2012-f_k_ L9 PART_NUM=LL2012-FR22K 220 nh Tee12 MCROS Cros1 W4=0.8 mm Tee14 sc_mrt_mc_grh111c0g500_c_ C13 PART_NUM=GRH111C0G030C500 3pF sc_mrt_mc_grm36c0g050_d_ C23 PART_NUM=GRM36C0G100D050 10pF sl_tok_ll2012-f_k_ L10 PART_NUM=LL2012-FR22K 220 nhmlin TL5 W=0.8 mm L=0.8 mm sc_mrt_mc_grm39c0g050_j_ Tee16 C12 PART_NUM=GRM39C0G101J pF pb_nec_2sc4226_ Q1 Tee13 sr_avx_cr_21_j_ R5 PART_NUM=CR21-271J 270 Ohm Term Term2 Num=2 Z=50 Ohm sc_mrt_mc_grm36c0g050_d_ C19 PART_NUM=GRM36C0G100D050 10pF sc_mrt_mc_grm36c0g050_d_ C18 PART_NUM=GRM36C0G100D050 10pF Fig. 2 Designed Circuit for oscillation.

3 Fig.3 Simlated Impedance values. Negative resistance characteristics at 400 MHz are obtained. LC tank circuit : additional inductor of 12 nh as well as varactor diode

4 Simulated Results of VCO ; Fig. 4 Magnitude and Phase Characteristics. Oscillation condition at 400 MHz :, phase approximately 0 o.

5 sc_mrt_mc_grh110c0g050_d_ C11 PART_NUM=GRH110C0G100D050 10pF MLIN TL1 W=0.8 mm L=0.8 mm SRC SRC2 R=0.25 Ohm C=9 pf HARMONIC BALANCE HarmonicBalance HB2 Freq[1]=400 MHz Order[1]=7 PhaseNoise=yes OscMode=yes OscPortName="oscport1" Tee1 sl_tok_ll2012-f_k_ L5 PART_NUM=LL2012-F12NK 12 nh MSub MSUB MSub1 H=0.8 mm Er=4.3 Mur=1 Cond=1.0E+50 Hu=1.0e+033 mm T=0.02 mm TanD= Rough=0 mm OscPort oscport1 V= Z=1.1 Ohm NumOctaves=2 Steps=10 FundIndex=1 MaxLoopGainStep= sc_mrt_mc_grm36c0g050_d_ C19 PART_NUM=GRM36C0G100D050 10pF sr_avx_cr_05_j_ R8 PART_NUM=CR05-122J 1.2 kohm sl_tok_ll2012-f_k_ L9 PART_NUM=LL2012-FR22K 220 nh Tee6 Tee2 Tee7 sr_avx_cr_05_j_ R7 PART_NUM=CR05-821J 820 Ohm sc_mrt_mc_grh111c0g500_c_ C13 PART_NUM=GRH111C0G030C500 3pF sc_mrt_mc_grm36c0g050_d_ C23 PART_NUM=GRM36C0G100D050 10pF MCROS Cros1 W4=0.8 mm sc_mrt_mc_grm36c0g050_d_ C18 PART_NUM=GRM36C0G100D050 10pF Tee3 Tee4 MLIN TL3 W=0.8 mm L=0.8 mm sr_avx_cr_05_j_ R6 PART_NUM=CR05-5R1J 5.1 Ohm sl_tok_ll2012-f_k_ L10 PART_NUM=LL2012-FR22K 220 nh sc_mrt_mc_grm39c0g050_j_ C12 PART_NUM=GRM39C0G101J pF Tee8 V_DC SRC1 Vdc=5 V Tee9 Vout pb_nec_2sc4226_ Q1 sr_avx_cr_05_j_ sr_avx_cr_05_j_ R10 R11 PART_NUM=CR05-181J 180 Ohm PART_NUM=CR05-181J 180 Ohm Tee5 sr_avx_cr_21_j_ R5 PART_NUM=CR21-271J 270 Ohm sr_avx_cr_05_j_ R9 PART_NUM=CR05-300J 30 Ohm R R4 R=50 Ohm Fig. 5 Designed final VCO Circuit. Output Power ; 3 dbm, Phase Noise at 10 khz offset ; < -115 dbc/hz Frequency Range ; 380 MHz 430 MHz

6 Simulated Results ; (a) Phase Noise (b) Frequency and Output Power Fig. 6 Simulated Results by Harmonic Balance Analysis. Frequency Output Power Phase khz Simulated 400 MHz 3.07 dbm dbc/hz Measured 400 MHz 3.41 dbm dbc/hz Table 1. Comparison between Simulated and Measured Results.

7 Measured Power Spectrum ; Fig. 7 Phase 10 khz Offset.

8 Simulated and Measured Harmonic Characteristics ; Fig. 8 Simulated Harmonic Characteristics. Simulated results up to 7th Harmonics ; 1st 2nd 3rd 4th 5th 6th 7th Simulted(dBm) Measured(dBm) Table 2. Comparison of Harmonics.

9 Fig. 9 Measured Harmonic Characteristics.

10 2. PLL IC U2781B(Atmel) for UHF Applications U2781B : Dual Modulus Type, 3-wire bus(clock, Data, Enable) 3. Loop Filter Loop Filter : Passive or Active Type, Reject Spurious KF VCO R 3 C 1 C 2 C 3 R 2 Fig. 10 3rd Order Passive Loop Filter. ; rejects spurious by additional pole the loop bandwidth becomes narrower longer lock time resulted

11 Design Criteria of the loop Filter : 1) 400 MHz VCO ; gain of 16 MHz/V, 2) Loop Bandwidth ; 0.2 khz 3) Phase Margin = 56 o 4) Attenuation = 30 db 5) F r =12.5 khz Simulated Results : Fig. 11 Loop Filter for Simulation. Optimized Element Values C 1 = 220 nf + 22 nf, C 2 = 3.3 uf, C 3 = 100 nf + 33 nf, R 2 = 1 kω, R 2 = 3.3 kω

12 Fig.12 Simulated results for Loop Filter.

13 4. lock time Measured Lock Time ; ms hopped from 400 MHz to 405 MHz Fig. 13 Measured Lock Time.