IMPLEMENTATION OF A MOBILE 10 GHZ CONTINUOUS WAVE DOPPLER RADAR. A Project

Transcription

1 IMPLEMENTATION OF A MOBILE 10 GHZ CONTINUOUS WAVE DOPPLER RADAR A Project Presented to the faculty of the Department of Electrical and Electronics Engineering California State University, Sacramento Submitted in partial satisfaction of the requirements for the degree of MASTER OF SCIENCE in Electrical and Electronics Engineering by Mick Khamphithoun Chanthaseth SPRING 2015

2 2015 Mick Khamphithoun Chanthaseth ALL RIGHTS RESERVED ii

3 IMPLEMENTATION OF A MOBILE 10 GHZ CONTINUOUS WAVE DOPPLER RADAR A Project by Mick Khamphithoun Chanthaseth Approved by:, Committee Chair Dr. Milica Markovic, Second Reader Dr. Preetham Kumar Date iii

4 Student: Mick Khamphithoun Chanthaseth I certify that this student has met the requirements for format contained in the University format manual, and that this project is suitable for shelving in the Library and credit is to be awarded for the project., Graduate Coordinator Dr. Preetham Kumar Date Department of Electrical and Electronics Engineering iv

5 Abstract of 10 GHZ DOPPLER RADAR by Mick Khamphithoun Chanthaseth This project presents circuits necessary to create a mobile Continuous Wave Doppler radar for fall detection. A radar as an assistive device for the elderly will solve the main problem with current marketed devices because a radar does not require user interaction. Currently, most radars are large and are not practical for mobile use. The project involves design, fabrication, and testing of an oscillator, antennas, an amplifier, a power splitter, a mixer, and a low pass filter. The end products are components with sizes ranging from one inch by one inch to one inch by three inches, which makes it feasible to construct the mobile radar., Committee Chair Dr. Milica Markovic Date v

6 TABLE OF CONTENTS Page List of Tables... viii List of Figures... ix Chapter 1. INTRODUCTION Overview BACKGROUND THEORY Oscillator Negative Resistance Oscillator Power Divider High Gain Amplifier Transmitter and Receiver Antenna Low Noise Amplifier Mixer Low Pass Filter ADS AND HFSS SIMULATIONS Antenna Oscillator Amplifier Low Noise Amplifier (LNA) Maximum Gain Amplifier Power Divider vi

7 3.5 Mixer Low Pass Filter CIRCUIT FABRICATION AND MEASUREMENTS Antenna Oscillator Amplifier High Gain Amplifier Power Divider Mixer CONCLUSION REFERENCES vii

8 Tables LIST OF TABLES Page 1. Substrate Properties for Antenna Fabrication Antenna Bill of Materials Substrate Properties for Oscillator Fabrication Oscillator Bill of Materials Substrate Properties for Amplifier Fabrication LNA Bill of Materials Maximum Gain Amplifier Bill of Materials Power Divider Bill of Materials Mixer Bill of Materials Comparison of Simulated and Actual Results for Antenna Comparison of Simulated and Actual Results for Oscillator Comparison of Simulated and Actual Results for Max Gain Amplifier Comparison of Simulated and Actual Results for Power Divider viii

9 Figures LIST OF FIGURES Page 1. Radar Overview Quadrature Hybrid Circuit Diagram in ADS Far Field Region Gamma Compromise Printed Dipole Model D Radiation Pattern of Antenna Return Loss of Antenna VSWR of Antenna HFSS Antenna Parameters Schematic for Oscillator Bias Sweep Oscillator Bias Simulation Results Oscillator Bias Network with Simulation Results Schematic for Oscillator Feedback Inductor Sweep Stability Factor Mu as a Function of Base Inductor for Circuit in Figure Schematic for Oscillator Instability Sweep Smith Chart to Determine the Load and Terminal Impedances Schematic for Oscillation Test Using Ideal Equations Simulation Results for Oscillation Test Using Ideal Equations Schematic for Oscillation Test from Using Stubs Oscillation Test Results from Using Stubs.. 31 ix

10 21. Recalculations of Microstrip Components Simulation Results Schematic for Oscillator with Microstrip Lines Oscillator Simulation Results LNA Bias Circuit Amplifier S-Parameters before Matching Circuit Stability Plot before Adding the Stability Circuit LNA Stability Circuit LNA S-Parameters after Stability Circuit LNA Stability Max Gain Point and Lowest Noise Point Transistor Noise before Matching Circuits Matching Circuits Noise Factor Reduction after Matching Circuits Final Gain of LNA Schematic for Maximum Gain Amplifier Maximum Gain Amplifier S-Parameters after Being Matched Max Gain Amplifier Stability Plot Schematic for Ideal Power Divider Ideal Power Divider Simulation Results Power Divider Microstrip Model Power Divider Simulation Results Schematic for an Ideal Mixer Mixer Output from Different Input Frequencies.. 51 x

11 44. Schematic for Mixer Simulation Results for Mixer Circuit ADS Filter Design Guide Schematic for Lumped Elements Filter Low Pass Filter Simulation Results Layout of Signal and Ground Layers for Antenna Antenna Signal Path Antenna Ground Path Antenna Test Setup Antenna Test Results on Network Analyzer Layout of the Oscillator Fabricated Oscillator Oscillator Test Setup with Spectrum Analyzer Oscillator Test Results on Spectrum Analyzer High Gain Amplifier Layout Max Gain Amplifier Fabricated Circuit Amplifier Test Setup with Spectrum Analyzer Max Gain Amplifier at 5 GHz on Spectrum Analyzer Power Divider Layout Ohm Terminal Fabricated Power Divider Power Divider Test Setups with Network Analyzer Port 3 Test Connection xi

12 67. Port 2 Test Connection Forward Transmission at Port 3, S Forward Transmission at Port 2, S Return Loss at Port 1, S Layout of the Mixer Fabricated Mixer xii

13 1 Chapter 1 INTRODUCTION We often associate the term radar with the military and the term Doppler radar with the meteorologist, but there are many more applications to radars. The latest vehicles are equipped with radars as proximity sensors. Even some children s toys are equipped with radars to track position. Radar is an acronym for Radio-Detection-And-Ranging. It operates by transmitting a signal and analyzing the signal that reflects from an object. Through analysis, one could determine whether the object is a vehicle, a cloud, or other. This project demonstrates design of electronic circuits necessary to develop a device for mobile radar. This radar could be used to detect a falling person, specifically how close a person is to the ground. Devices such as accelerometers, radars, and cameras, are typical devices for fall detection. Accelerometers are mechanical devices that, in conjunction with electronics, sense movements. Accelerometers have short lifetime because of their mechanical nature. Another device for object detection is a camera. Cameras record movements, but they do not work well in low or no light setting. Another disadvantage is that even the slowest frame rate and the smallest resolution can overload a processor with complex algorithms. Radar is a better choice than a camera or an accelerometer because it does not need complex algorithms or moving parts. The radar in this project is a Continuous Wave Doppler radar. A Doppler radar detects a moving object by analyzing the frequency shift between the transmitted signal and the received signal. Components needed to construct a Doppler radar are an oscillator, amplifiers, power splitter, a mixer, and antennas. Design and implementation of these circuits are described in Chapters 3 and 4.

14 2 Radars for physiological uses are a timely topic. Some state-of-the-art topics in recent years are cooperative fall detection [13], comparison between frequencies for vital sensing [7], and RCS of human movements [8]. These topics arise from a common consensus that the population of senior citizens will increase in the future. In the paper Cooperative Fall Detection Using Doppler Radar and Array Sensor [13], Hong described using radar along with machine learning for fall detection. The radar used was a stationary Continuous Wave Doppler radar. Hong recognized that the percentage of senior citizens would double by the year 2050, and in Japan, there is a large percentage of seniors living alone. This population could benefit from fall detection technology. The research was conducted because there was not much information available on non-line-of-sight radars (NLOS). Most radars require line-of-sight (LOS) because the reception is best with LOS. To assist with NLOS losses, Hong used an antenna array, which increases gain for the receiver antenna. Antenna gains are proportional to aperture size; therefore, adding more antennas is equivalent to increasing the aperture size. Aside from the antenna array, Hong also used a Support Vector Machine (SVM) learning algorithm to categorize features of a fall. The advantage of Hong s system is that the radar could be stationary and not be placed directly on the subject, which could also be a disadvantage because sensing range is limited. Another disadvantage is that it requires post processing using machine learning. The SVM algorithm must be trained to learn what to categorize as a fall and what not to categorize as a fall. Another similar project is radar-based fall detection based on Doppler time frequency signatures for assisted living [14]. In this project, Wu experiments with Bayesian classification technique, rather than SVM, for a fall detection algorithm. Like the previous project, this project uses a stationary Continuous Wave Doppler radar. The Bayesian classification technique is used to categorize different types of falls. It uses Relevance Vectors Machine (RVM) rather than

15 3 Support Vectors, which reduces computation time and provides better results. From the return signal, Wu analyzes the Short-time Fourier transform of the returned signal and classifies its features through RVM. A couple of other projects are using radars for different purposes, but like fall detection, those other projects contribute to understanding human physiology. One compares sensing vitals at a couple of frequencies [7]. The other compares RCS at multiple frequencies [8]. Both of these projects experiment detecting heartbeats using the Continuous Wave Doppler radar. In the first project, Jun researches radar operating at 2.4 GGG and at 10 GGG combined with digital signal processing to detect heartbeats. In his paper, Yong-Jun shows advantages of operating at 10 GGG versus 2.4 GGG. Operating at 10 GGG gives better radar cross section (RCS), better gain, and shows better Doppler effects. In the second project, G. De Pasquale also develops models to detect the human heart using frequencies from 1 GGG to 10 GGG. Both works show that modern physiological science could benefit from radars. In the projects previously mentioned, the radars are all stationary radars. While these works focuses on signatures of the reflected signal, this project focuses on the hardware required to build a mobile radar. It could then be used in conjunction with software algorithms to classify falls. In this project, software and hardware available in the Microwave Laboratory at California State University, Sacramento is used. Software used for this project are Agilent s Advanced Design System (ADS) [18] and Ansys High-Frequency Structure Simulator (HFSS) [19]. Hardware used for this project is Roger s Duroid 4003C and 5880 laminates, Infineon BFP740 BJT transistor, Infineon BFP840 BJT transistor, and various passive lumped element components. For manufacturing, the T-TECH 9000 PCB router is used to mill the PCBs.

16 4 1.1 Overview This project demonstrates design of seven components that make up the radar: oscillator, power divider, high gain amplifier, low noise amplifier, transmitter antenna, receiver antenna, a mixer, and a low pass filter. Figure 1 shows a block diagram of the radar. All of the radars mentioned in the previous section, as well as in this project, are Continuous Wave Doppler radars. This type of radar transmits a signal at a single frequency and, if the target is moving, it receives a reflection of the same signal at slightly higher or lower frequency. From this frequency shift, the speed of the monitored object can be deduced. Another type of radar is the pulse Doppler radar. A pulse Doppler radar sends pulses and waits for the pulses to arrive at the receiver. The advantage to the pulse radar is the ability to detect a stationary object. The disadvantage is the complexity of the system because it needs post processing of the received signal to calculate time delays. The simplicity of the Continuous Wave Doppler radar, as opposed to the pulsed Doppler radar, makes it more favorable to construct. The block diagram of typical radar is shown in Figure 1. The output of the oscillator connects to a power splitter. A power splitter splits an input signal evenly to two output ports. The signals at the output ports have the same frequency but different phase shifts. One of the outputs connects to the transmitter, and the other output connects to the receiver. The transmitter consists of a power amplifier and an antenna. In this project, a small-signal high-gain amplifier is used. This amplifier would drive a power-amplifier in a future implementation of the radar. An amplifier is a transistor driven in linear stable mode and matched to amplify a signal at a specific frequency. The last component of the transmitter circuit is an antenna. An antenna radiates a signal from the transmitter circuit into free space. The signal reflects from an object and then it is detected by the receiver antenna. Throughout its travel path, the signal loses strength, but the signal is amplified by the low-noise receiving amplifier. The signal then mixes with a local signal

17 5 at the mixer. The output of the mixer is a signal at multiple frequencies; one of the frequencies is the difference between the transmitted frequency and the received frequency. A low pass filter is used to extract the difference frequency. The difference between two frequencies equates to the speed of the tracked object. The Doppler shift is calculated by f d = 2vf c c v (1.1) If a person fell from two meters, their speed, using kinematics, would be v f = v a(x x 0 ) Using equation 1.1, the Doppler frequency is v f = 2(9.8)(2) v f = 6.26 m/s f d = 2(6.26)(1010 ) 10 8 (6.26) = 1.3 kkk

18 6 Figure 1 - Radar Overview This project is organized as follows: Chapter 1 presents the motivation for the project, Chapter 2 presents the review of background theory, Chapter 3 contains design and computer simulations for the circuits, Chapter 4 contains the results from circuit fabrication and measurements, and chapter 5 concludes the project.

19 7 Chapter 2 BACKGROUND THEORY Microwave Engineering is the study of communication circuits within the frequencies ranging from 300 MHz to 300 GHz with corresponding wavelengths from one meter to one millimeter. To create a 10 GHz Doppler radar, oscillator, power splitter, amplifiers, antennas, mixer, and low pass filter design, are discussed. 2.1 Oscillator An oscillator is a device that generates an RF signal. Some popular oscillator design methods are Colpitts, Hartley, negative feedback, and crystal oscillator. The oscillator chosen for this project is a negative feedback oscillator. This configuration is best since the oscillation frequency for this project is 10 GHz. Lumped elements such as inductors and capacitors do not behave like ideal components at high frequencies [3]; therefore, the other choices for oscillator design are difficult to implement. The only capacitors and inductors used in this project are DC Block and RF Choke components. DC Block components are capacitors placed at the input and the output of a transistor circuit; Bypass Capacitor is another name for these components. Its purpose is to contain the DC current in the bias circuit, and to bypass the AC signal. RF Choke components are inductors placed on the DC bias to allow DC current to pass, but not AC current. The input and output capacitors must have resistance small enough to not disrupt the input and output impedances of the transistor circuit. Equations 2.1 and 2.2 show that high capacitor values correspond to lower capacitor impedance. Choosing a high value capacitor should work for all cases, but the caveat is the physical limitation of the capacitor [15]. Loop inductance associated with the connection terminals makes the capacitor look like an inductor at

20 8 high frequencies. The bypass capacitors chosen for the input and output should exceed the criteria in equations 2.1 and ππC ii R ii (2.1) 1 2ππC ooo R ouu (2.2) where C ii is the capacitor at the input circuit, R ii is the resistance at the input of the capacitor, C ooo is the capacitor at the output circuit, and R ooo is the resistance at the output of the capacitor. Frequency dictates inductance needed for RF chokes. Much like the capacitors, high inductor values are favored; however, larger inductances usually have larger parasitic capacitances. Equation 2.3 determines the inductance values. L = Z 2ππ (2.3) Negative Resistance Oscillator Oscillation occurs when a circuit is unstable. For oscillation to occur, input or output reflection coefficient Γ II oo Γ OOO should be greater than one. If Γ II is greater than one, then Γ OOO is greater than one too. Overlapping plot of Γ T and Γ ii on a Smith chart is used to determine the terminal and load impedances that generate instability [2]. Γ T is the reflection that the transistor wants to see at the output terminal, the connection at the collector. Γ ii is the reflection that is present at the input of the transistor; the connection at the base.

21 9 Kurokawa s [10] condition for stable oscillation is R II (A) X L (ω) A=A0 ω=ω 0 > 0 Where R II (A) is the input resistance as a function of the amplitude of the current through the transistor, A 0 is the amplitude of the current at the frequency of oscillation, X L (ω) is the reactance of the load as a function of the frequency of the current through the transistor, and ω 0 is the frequency of oscillation. R II and P is R II = R o 1 A A M P = 1 2 I 2 R II = 1 2 A2 1 A A M where P is the power generated by the transistor, A is the amplitude of the current through the transistor, A M is the maximum current through the transistor, and R 0 is the maximum input resistance of the transistor. The derivative of power should be zero for max power. = 1 2 A2 1 A = 0 A M 1 2 A2 1 A A2 = 0 2 A M A 2 A 3 = 0 2 A M A 2 A = A M 3 A M = A A = 2 3 A M (2.4)

22 10 For optimal load resistance: R L = R II, and R II = rrrr R L = R II 2 3 A M R L = R 0 1 A R A L = R 0 1 R M A L = R 0 M 3 R L = R 0 3 (2.5) The above equation means that if the load resistance is negative 1/3 of the maximum input resistance, the output power is maximized. 2.2 Power Divider A power divider splits the power exerted at one port into multiple paths. Many types of dividers exist, such as T-Junction, Resistive, Wilkinson, etc. The one used for this project is a Quadrature (90 ) Hybrid. The scattering matrix for a Quadrature Hybrid is 0 j [S] = 1 2 j j j 0 (2.6) Assuming that the intrinsic impedance of the ports is 50 Ω, Figure 2 displays a Quadrature Hybrid.

23 11 Figure 2 - Quadrature Hybrid Circuit Diagram in ADS The power from port one splits to port two and port three. The power at port two is half of port one and has a phase shift of negative 90. The power at port three is half of port one and has a phase shift of negative 180. The power at port two and port three is 90 apart. 2.3 High Gain Amplifier A high-gain amplifier at microwave frequencies is an amplifier that has its impedance matched at the input and output for maximum gain. The transistor gain is given in a datasheet as S 21. Matching the input of the transistor results in gain improvement at the input and matching the output of the transistor results in gain improvement at the output. The maximum unilateral transducer gain equations are given below. G IIIII = 1 1 S 11 2 (2.7) G OOOOOO = 1 1 S 22 2 (2.8) G 0 = S 21 2 (2.9)

24 12 TTTTT GGGG = G IIIII G 0 G OOOOOO (2.10) Before any of the matching circuit, the transistor must be biased. Subsequently, the transistor has to be stable for every frequency up to the transition frequency found in the datasheet. If the transistor is not stabilized in the entire frequency range, the transistor could oscillate when presented with a load at a frequency that makes it unstable. Oscillations could damage circuits as well as reduce gain in its operating points. There are a couple of parameters that ensure that the circuit is stable, which are Mu and MuPrime [13]. Δ = S 11 S 22 S 12 S 21 (2.11) 1 S 11 2 MM = S 22 S 11 Δ + S 21 S 12 (2.12) 1 S 22 2 MMMMMMM = S 11 S 22 Δ + S 21 S 12 (2.13) To have an unconditionally stable transistor, the values Mu and MuPrime must both be greater than one. In general, mu represents the distance between the center of the Smith Chart and the circle where the transistor is unstable. Mu represents the stability of the source, and MuPrime represents the stability of the load side. If Mu and MuPrime are less than one, the transistor has the potential to oscillate. 2.4 Transmitter and Receiver Antenna Antennas radiate signal energy into the air. The antenna for this project is a half-wave printed dipole antenna. The energy radiates from a dipole because the current from the signal path

25 13 and the ground path are separated and the currents are in the same direction. The antenna is designed in HFSS on a Duroid 4003C 32mil board. The radiation can be estimated with equations for a thin dipole where the cross area of each dipole is zero. In the following derivation [1], current components in the x and y directions are zero because the area of the dipole is assumed to be zero. There is only current in the z direction, given as follows: a z I 0 sin k l I e (x = 0, y = 0, z ) = 2 z, 0 z l 2 a z I 0 sin k l 2 + z, l 2 z 0 The previous equation describes the current as a function of z. l is the length of each dipole, k is the wave number, and I 0 is a constant describing the amplitude of the current. In a far field region, the received wave is a plane wave; it is the distance where r is approximately equal to R as shown in Figure 3. Equation 2.14 defines the far field distance. d fff fffff = 2D2 λ (2.14) where D is the largest dimension of the antenna, and λ is the wavelength. Figure 3 - Far Field Region In Figure 3, R is the distance from the transmitter antenna to the farthest end of the receiver antenna, and r is the distance from the transmitter antenna to the nearest point of the receiver antenna.

26 14 When the distance of the receiver is in the far field region, the electric field is in the form: l 2 E θ = de θ l 2 de θ jj ki e(x, y, z ) ssssss 4ππ = jj ke jjj 4ππ l 2 ssss I e(x, y, z )e jjz cccc dd l 2 E θ jj ki 0e jjj 2ππ cos kk 2 cccc cos kk 2 ssss H φ E θ η j I 0e jjj cos 2ππ kk 2 cccc cos kk ssss 2 The last couple of equations can be reduced to: E θ jj I 0e jjj 2ππ 2 cos cccc ssss π H φ j I 0e jjj 2ππ 2 cos cccc ssss π The previous equations describe the electric and magnetic fields. r is the distance from the dipole, η is the impedance of free space, θ is the elevation, and φ is the azimuth. The power density is: W aa = η I 0 2 π 2 8π 2 r2 cos cccc ssss 2 η I 0 2 8π 2 r 2 sin3 θ The radiation intensity is:

27 15 U = r 2 W aa = η I 0 2 π 2 8π2 cos cccc ssss 2 η I 0 2 8π 2 sin3 θ The radiation power is: The directivity is: P rrr = η I 0 2 π 4π cos2 cccc 2 dd ssss 0 π D 0 = 4π U mmm P rrr Low Noise Amplifier A low noise amplifier (LNA) is an amplifier that compromises between high gain and low noise operation of a transistor. The reflection coefficient at the input is Γ cccc, and the reflection coefficient at the output is Γ ooo. Γ cccc is the compromise reflection coefficient between maximum gain and minimum noise; Γ cccc is, typically, a point that lies on a straight line drawn on the Smith chart from the point of maximum gain and the point of minimum noise, as shown in Figure 4 labeled as m6.

28 GAcircles Noise_circles m4 m7 m6 m5 m4 ndep(m4)= 51 GAcircles=0.414 / gain=8.457 mpedance = Z0 * ( j0.636) m6 ndep(m6)= 46 GAcircles=0.308 / gain=8.297 mpedance = Z0 * ( j0.639) m7 ndep(m7)= 16 Noise_circles=0.413 / ns figure=1.463 mpedance = Z0 * ( j0.936) m5 ndep(m5)= 51 Noise_circles=0.347 / ns figure=1.303 mpedance = Z0 * ( j0.598) -1.2 cir_pts (0.000 to ) Figure 4 - Gamma Compromise Figure 4 is an example of how the compromise point is chosen. Γ ooo is the point where the lowest noise figure is (noted by marker m5) and Γ cccc is the compromise point (noted by marker m6). Marker m7 shows how much the noise would increase by choosing Γ cccc. While the input is matched to Γ cccc, the output is matched to Γ ooo. Γ ooo is dependent on Γ cccc in bilateral transistors. Γ ooo = S 22 + S 12S 21 Γ cccc 1 S 11 Γ cccc (2.15)

29 Mixer A microwave mixer is a three-port device with two input ports and one output port. The output signal consists of the difference between the frequencies of signals at two inputs. The two types of mixers are up-conversion mixer and down-conversion mixer. An up-conversion mixer mixes the local oscillator frequency and the intermediate frequency and produces the higher radio frequency. A down-conversion mixer mixes the radio frequency and the local oscillator frequency and produces the lower intermediate frequency. Illustrations of the types of mixers can be found in Pozar [9]. This project utilizes the down-conversion mixer where the signals at the input ports are the local oscillator signal and the signal from the receiver antenna. v LL (t) = ccc2πf LL t (2.16) v RR (t) = ccc2πf RR t (2.17) v II (t) = Kv RR (t)v LL (t) = K 2 [ccc2π(f RR f LL )t + ccc2π(f RR + f LL (t)] (2.18) Equations 2.16 through equations 2.18 describe the waveforms at the terminals of the mixer. Although mixers should behave the same, there are many ways to design a mixer. Various designs are a single-ended FET, 90 balanced, 180 balanced, double balanced, and image reject. Pozar [9] showed the differences in characteristics of different types of mixers. The design chosen for this project is the 90 balanced mixer because the simplicity of its design outweighs its average performance. The 90 balanced mixer consists of a 90 coupler, which is the same design as section 2.2. The difference is that two input ports are used, and the output ports are combined after passing through a couple of diodes. Mixer design is presented in section 3.5.

30 18 From section 2.2, the voltage at port two is half of the voltage at port one with a delay of 90. The voltage at port three is half of the voltage at port one with a delay of 180. Since the input into port four is the local oscillator voltage, the voltage is transferred to port three at 90 and to port two at 180. In equation form, those voltages are v 1 (t) = 1 2 [V RR cos(ω RR t 90 ) + V LL cos(ω LL t 180 )] (2.19) v 1 (t) = 1 2 (V RRsssω RR t V LL cccω LL t) v 2 (t) = 1 2 [V RR cos(ω RR t 180 ) + V LL cos(ω LL t 90 )] (2.20) v 2 (t) = 1 2 ( V RR cos ω RR t + V LL sssω LL t) The current through the diodes is i 1 (t) = Kv 1 2 (2.21) i 2 (t) = Kv 2 2 (2.22) K in the above equations is a constant and the current out of port three is negative because of the orientation of the diode. The resulting current is i II (t) = KV RR V LL sssω II t (2.23) The relevant parameter is the frequency (ω II ).

31 Low Pass Filter A microwave low pass filter is a low pass filter that could be constructed using lumped elements or transmission lines. Its purpose is to filter out high frequency signals and pass lower frequency signals; it works in conjunction with the microwave mixer. It filters everything but the intermediate frequency. Designing a low pass filter starts with choosing a type of filter. Two types considered for this project are Butterworth and Chebyshev. The tradeoff between a Butterworth filter and a Chebyshev filter is that the Butterworth has a flat pass band with smaller difference between the pass band attenuation and the stop band attenuation, and the Chebyshev filter has ripples in the pass band and has a steeper roll off. The insertion-loss method design starts with selecting the order of the filter from the required attenuation in the stop-band. Then the filter coefficients are selected from the tables [9]. The coefficients are normalized lumped element component values, normalized to cut off frequency of one. These values are then scaled to the desired frequency. A final step in high frequency circuits is converting the lumped components into transmission lines, if necessary. After the background necessary to create the components, chapter 3 provides computer simulations on how each of these components operates. The computer simulations contain schematics and simulation results using Agilent s Advanced Design System and Ansys High Frequency Structure Simulator.

32 20 Chapter 3 ADS AND HFSS SIMULATIONS In this chapter, circuit design and simulations are presented for the Antenna, Oscillator, Amplifiers, Power Divider, Mixer, and Low Pass Filter. 3.1 Antenna A printed dipole is designed using HFSS. The substrate is a Rogers Duroid 4003C high frequency laminate. The substrate properties entered into HFSS are shown in Table 1. Property Height value 32 mmmm Relative Dielectric Constant (ε r ) 3.55 Table 1 Substrate Properties for Antenna Fabrication Material properties that are not considered are the loss tangent, thickness of metal and dielectric roughness. These might affect the differences between the simulated result and fabricated result. The same printed dipole antenna is used for both the transmitter and receiver antenna.

33 21 Figure 5 - Printed Dipole Model The printed dipole antenna is shown in Figure 5. The wave enters the dipole from the wave-port connected to the signal path that is parallel to the Y-axis, and then splits the dipole on the X-axis, which radiates radially on the Y-Z plane. The dipole is designed with the length of λ 2 = c f εr 2 = c 2f ε r. Then the length of the dipole is tuned in HFSS in order to have minimal reflections at 10 GHz. Figure 6-3D Radiation Pattern of Antenna

34 22 The 3D radiation pattern shows the "donut" shape that is expected from a dipole antenna. The shape is not uniform radially on the Y-Z plane because of the difference between the electric field traveling in the air and inside of the substrate. Figure 7 Return Loss of Antenna The reflection coefficient plot shows the frequency of operation for the antenna. At 10 GHz, the refection coefficient is at negative 11.8 db. Between 9.5 GHz and 10.5 GHz, the reflection coefficient is also below negative 10 db. Figure 8 VSWR of Antenna

35 23 Another way of looking at the performance of the antenna is by analyzing the VSWR plot. The VSWR at 10 GHz is 1.7. Since the simulated value is close to the ideal value of 1, this shows that the designed antenna works well. The HFSS antenna parameters are shown in Figure 9. The input power into the port is 1W. Figure 9 - HFSS Antenna Parameters

36 24 Item Quantity Rogers Duroid 4003C Substrate 1 Pasternack SMA Jack (up to 18 GHz) 2 Table 2 Antenna Bill of Materials 3.2 Oscillator The oscillator is designed using ADS. Unlike designing the antenna in section 3.1, more parameters are considered for the substrate as shown in Table 3. Property Height value 32 mmmm Relative Dielectric Constant (ε r ) 3.55 Loss Tangent (tan δ) Copper thickness Copper conductivity Surface roughness 35 μμ S m 4 μμ Table 3 Substrate Properties for Oscillator Fabrication The simulation setup is shown in Figure 10. To obtain the bias points, the collectoremitter voltage is swept from 3 V to 5 V and the base current is swept from 50 μμ to 75 μμ, as shown in Figure 11. The sweep shows the values where the transistor operates as on or off.

37 25 Figure 10 Schematic for Oscillator Bias Sweep After obtaining the transistor s performance in forward active mode, the collector emitter voltage is chosen to be 3 V. The plots in Figure 11 show that the bias points should be V CC = 3 V V BB = 0.84 V i C = 20 mm m2 VBE= plot_vs(i_probe1.i, VBE)=0.019 VC= m m I_Probe1.i I_Probe1.i VBE VC Figure 11 - Oscillator Bias Simulation Results

38 26 The collector-emitter resistor and the emitter-ground resistor values of 120 Ω and 50 Ω allow for the desired bias values. Figure 12 - Oscillator Bias Network with Simulation Results After biasing the circuit, the value for the inductor connected to the base of the transistor is swept from 1 nh to 10 nh. The sweep shows where the transistor is most unstable; it shows that the lower the inductance value is, the more unstable it is. The value of 1 nh is chosen for the simulation. Figure 13 Schematic for Oscillator Feedback Inductor Sweep

39 27 Figure 14 Stability Factor Mu as a Function of Base Inductor for Circuit in Figure 13 After the inductor is chosen, the load is swept to find the most unstable point, as shown in Figure 15 and Figure 16. Figure 15 Schematic for Oscillator Instability Sweep

40 28 Figure 16 Smith Chart to Determine the Load and Terminal Impedances The Smith chart in Figure 16 show two Smith charts; the main Smith chart represents Gamma-In, and the Smith chart drawn on top Gamma-In is Gamma-T. These reflection coefficients show what the input and output should be matched to. From the results shown in Figure 16, the load and terminal impedances that gave the transistor the most unstable configuration are j and 50 j The load impedance is the impedance of the circuit attached to the emitter and the terminal impedance is the impedance of the circuit attached to the collector, just before the output port. The terminal impedance is only matched to the imaginary value because the real value, 50 Ω, represents a device connected to the output.

41 29 Figure 17 Schematic for Oscillation Test Using Ideal Equations There are two ADS simulation devices in Figure 17 that check for oscillation. Those devices are OscPort and OscTest. OscPort simulates a time domain of the oscillation, and OscTest simulates a frequency domain of the oscillation. After simulating with optimal impedance represented by a Z1P_Eqn block in ADS, the transistor oscillated at about 10 GHz. The period of oscillation is at picoseconds and picoseconds, which represents the frequency at about 9.7 GHz as shown in Figure 18.

42 30 Figure 18 Simulation Results for Oscillation Test Using Ideal Equations Once it is determined that the presented load impedance allows oscillation, the lumped elements are replaced with ideal transmission lines. Using the transmission lines minimizes the number of lumped components and it minimizes the total discontinuities during fabrication. Figure 19 Schematic for Oscillation Test from Using Stubs

43 31 After the transmission line is added, the circuit is re-simulated to verify that it still oscillates. The shape of the oscillation from the transmission line circuit follows a sine wave shape better than the circuit with the ideal load blocks, which may be because the transmission line s impedance is equal to the load impedance only at the one frequency. Figure 20 - Oscillation Test Results from Using Stubs Incremental steps are taken to make sure that oscillation still occurs after a small change. The oscillation is checked after converting transmission line from lumped elements. Then the oscillation is checked after converting from series transmission line, which cannot be constructed on a microstrip board, to parallel transmission lines.

44 32 Figure 21 - Recalculations of Microstrip Components Simulation Results Microstrip lines are inserted into the circuit and new load and terminal impedances are calculated since the microstrip lines shifts some of the parameters. The new impedances to match to are shown in Figure 21. The new load and impedances are then converted into parallel microstrip lines and are inserted into the circuit, as shown in Figure 22, and the final simulation results is shown in Figure 23.

45 Figure 22 Schematic for Oscillator with Microstrip Lines 33

46 34 Figure 23 Oscillator Simulation Results Item Quantity Rogers Duroid 4003C Substrate 1 Pasternack SMA Jack (up to 18 GHz) 1 20 Ω Resistor 1 50 Ω Resistor Ω Resistor 1 47 nn Inductor 2 1 μμ Capacitor 2 Table 4 Oscillator Bill of Materials

47 Amplifier The amplifier design and simulation is presented in this section. The substrate used here is a Rogers Duroid The properties are shown in Table 5. property Height value 31 mmmm Relative Dielectric Constant (ε r ) 2.2 Loss Tangent (tan δ) Copper thickness Copper conductivity Surface roughness 35 μμ S m 4 μμ Table 5 Substrate Properties for Amplifier Fabrication The noticeable difference in the properties is the loss tangent and the relative dielectric constant. These values are lower; therefore, the material impedes a signal less than the Rogers Duroid 4003C Low Noise Amplifier (LNA) The optimization feature in ADS determines the bias circuit for the LNA. The base and collector resistors are swept until the collector-emitter voltage is 1.8 V and the collector current is 15 mm. Then the values of the resistors are substituted with resistor values found in the lab. After substituting with the lab values, the bias points remain near the same.

48 36 V_DC SRC1 Vdc=3 V R R3 R=44.2 Ohm R R1 R=12.1 kohm DC_Feed DC_Feed1 vc I_Probe I_Probe1 DC_Feed DC_Feed2 Term Term1 Num=1 Z=50 Ohm DC_Block DC_Block1 BFP840ESD X1 _M=1 DC_Block DC_Block2 Term Term2 Num=2 Z=50 Ohm Figure 24 - LNA Bias Circuit Having only the transistor biased, the transistor gain output looks very desirable. The gain at 10 GHz is about 12 db, but that gain value cannot be achieved since the circuit is not unconditionally stable, as shown in Figure 26, where the Mu factors are less than one at most frequencies.

49 db(s(2,2)) db(s(2,1)) db(s(1,2)) db(s(1,1)) freq, GHz Figure 25 - Amplifier S-Parameters before Matching Circuit MuPrime1 Mu freq, GHz Figure 26 - Stability Plot before Adding the Stability Circuit

50 38 After creating the bias circuit, the amplifier has to be stabilized. The stability circuit consists of a branch to ground immediately following the collector and a parallel branch. The branch to ground provides stability at low frequencies where the parallel branch provides stability at high frequencies. By adding the stability circuits, the maximum achievable gain at 10 GHz reduces from 12 db to 7.5 db. Another stage that slightly reduces the gain is the noise compensation circuit. The 100 Ω resistor from collector to ground stabilizes the circuit at lower frequencies, and the 48.7 Ω resistor in parallel with the 22 nn inductor stabilizes the circuit at higher frequencies. V_DC SRC1 Vdc=3 V R R3 R=44.2 Ohm R R1 R=12.1 kohm DC_Feed DC_Feed1 vc I_Probe I_Probe1 DC_Feed DC_Feed2 R R4 R=48.7 Ohm DC_Block Term DC_Block1 Term1 Num=1 Z=50 Ohm BFP840ESD X1 _M=1 DC_Block DC_Block3 L L1 L=22 nh R= R R5 R=100 Ohm DC_Block DC_Block2 Term Term2 Num=2 Z=50 Ohm Figure 27 - LNA Stability Circuit

51 m1 freq= 10.00GHz m1 db(s(2,1))=7.599 db(s(2,2)) db(s(2,1)) db(s(1,2)) db(s(1,1)) freq, GHz Figure 28 - LNA S-Parameters after Stability Circuit MuPrime1 Mu freq, GHz Figure 29 - LNA Stability

52 Noise_circles GAcircles m3 indep(m3)= 34 Noise_circles=0.684 / ns figure=2.057 impedance = Z0 * ( j0.910) m freq GHz GHz GHz Zout j j j cir_pts (0.000 to ) Figure 30 - Max Gain Point and Lowest Noise Point 10 8 nf(2) 6 4 m4 m4 freq= 10.00GHz nf(2)= freq, GHz Figure 31 Transistor Noise before Matching Circuits Once the circuit is stable, noise circles and gain circles are plotted on the Smith chart, as described in section 2.5. The gamma compromise point is shown in Figure 30. The input

53 41 impedance is defined by gamma compromise, and the output impedance is calculated by equation The simulated s-parameters are S 11 = S 12 = S 21 = S 22 = The value of the input impedance obtained from Figure 30 is j The value of output circuit is calculated to be j Figure 32 shows the matched circuit. Figure 33 and Figure 34 show that the noise is reduced from dd to dd and the gain is reduced from dd to dd. V_DC SRC1 Vdc=3 V R R3 R=44.2 Ohm R R1 R=12.1 kohm DC_Feed DC_Feed1 vc I_Probe I_Probe1 DC_Feed DC_Feed2 R R4 R=48.7 Ohm Term Term1 Num=1 Z=50 Ohm Ref TLIN TLOC TL1 DC_Block TL2 Z=50.0 Ohm DC_Block1 Z=50.0 Ohm E= E= F=10 GHz F=10 GHz BFP840ESD X1 _M=1 DC_Block DC_Block3 L L1 L=22 nh R= R R5 R=100 Ohm DC_Block DC_Block2 TLIN TL3 Z=50.0 Ohm E= F=10 GHz Ref TLOC TL4 Z=50.0 Ohm E= F=10 GHz Term Term2 Num=2 Z=50 Ohm Figure 32 - Matching Circuits

54 42 50 nf(2) m4 freq= 10.00GHz nf(2)= m freq, GHz Figure 33 - Noise Factor Reduction after Matching Circuits m5 m5 freq= 10.00GHz db(s(2,1))=6.908 db(s(2,2)) db(s(2,1)) db(s(1,2)) db(s(1,1)) freq, GHz Figure 34 - Final Gain of LNA

55 43 Item Quantity Rogers Duroid 5880 Substrate 1 Infineon BFP 840 transistor 1 Pasternack SMA Jack (up to 18 GHz) Ω Resistor Ω Resistor Ω Resistor kω Resistor 1 22 nn Inductor pp Capacitor 3 Table 6 LNA Bill of Materials Maximum Gain Amplifier The two main design features for a maximum gain amplifier are stability for all frequencies and terminal matching circuits. Ensuring that the amplifier is stable for all frequencies removes any ambiguity that the transistor may oscillate at any frequency as described in Chapter 2.4.

56 44 Figure 35 Schematic for Maximum Gain Amplifier The full circuit for the maximum gain amplifier is shown in Figure 35. The bias circuit is determined through an optimization process in ADS with a desired collector-emitter voltage at 2 V and the collector current at 20 mm. The stability circuit follows the collector circuit with a branch to ground and parallel branches. The branch to ground allows for stability at lower frequencies and the parallel branch stabilizes higher frequencies. At the ends of each side there is

57 45 an input matching circuit and an output matching circuit. These circuits are also determined by optimization inside ADS. The single stub matching circuits is inserted into the transistor circuit and is optimized until the gain at 10 GGG is at its maximum while keeping the circuit stable. Figure 36 Maximum Gain Amplifier S-Parameters after Being Matched The input and output stability is shown in Figure 37. At all frequencies, the factor is above one; therefore, it is unconditionally stable. The circuit is more stable before the matching circuits, and it became borderline stable after adding the matching circuit. These are shown at frequencies between 5 and 8 GHz where the stability factor is closer to one.

58 46 Figure 37 - Max Gain Amplifier Stability Plot Item Quantity Rogers Duroid 5880 Substrate 1 Infineon BFP 840 transistor 1 Pasternack SMA Jack (up to 18 GHz) Ω Resistor 1 32 Ω Resistor Ω Resistor Ω Resistor kω Resistor 1 47 nn Inductor 2 33 nn Inductor pp Capacitor 3 Table 7 Maximum Gain Amplifier Bill of Materials

59 Power Divider The design of an ideal power divider is shown in Figure 38. The input port is port 1. The output ports are ports 2 and 3. The isolation port is the port terminated with a 50 Ω resistor. S_Param SP1 Start=1 GHz Stop=18 GHz Step=0.1 GHz S-PARAMETERS Term Term1 TLIN Num=1 TL1 Z=50 Ohm Z=50.0/sqrt(2) Ohm E=90 F=10 GHz TLIN TL2 Z=50.0 Ohm E=90 F=10 GHz R R1 R=50 Ohm TLIN TL4 Z=50.0/sqrt(2) Ohm E=90 F=10 GHz TLIN TL3 Z=50.0 Ohm E=90 F=10 GHz Term Term3 Num=3 Z=50 Ohm Term Term2 Num=2 Z=50 Ohm Figure 38 Schematic for Ideal Power Divider The results of the simulation in Figure 39 show that the power at ports two and three are the same at negative 3 dd at 10 GGG. The circuit is a matched circuit because the return loss, S 11, is negative 300 db. This value is very low because all components used in the simulation are ideal transmission lines.

60 48 0 m1-10 db(s(3,1)) db(s(2,1)) db(s(1,1)) m1 freq= 10.00GHz db(s(1,1))= db(s(2,1))= db(s(3,1))= freq, GHz Figure 39 - Ideal Power Divider Simulation Results The Power Divider circuit has a minor deviation from the original circuit. The deviation is at terminal two. The output port cannot be on the same side of the PCB due to the SMA Jack being too large and the 90 length being not long enough to compensate for the large jack. Terminal two has to be outputted on the top side of the PCB. This can be seen in Figure 64.

61 49 Figure 40 - Power Divider Microstrip Model Figure 41 Power Divider Simulation Results

62 50 Originally, the simulation is operating at 8 GHz. The original circuit is using 90 lengths along with 35 Ω and 50 Ω widths. These parameters have to be tuned until the circuit operates at 10 GHz. This is done using the optimizer in ADS. Item Quantity Rogers Duroid 5880 Substrate 1 Pasternack SMA Jack (up to 18 GHz) 3 50 Ω Resistor 1 Table 8 Power Divider Bill of Materials 3.5 Mixer The ideal 90 balanced mixer is shown in Figure 42. SRC1 and SRC2 are input sources; they represent the signal from the local oscillator and the signal from the receiver antenna. When the input signals are at different frequencies f1 and f2, the signal at the output is at the difference frequency, f d = f 1 f 2. When the inputs are at the same frequency, only the local oscillator frequency shows at the output of the mixer. Figure 43 shows the simulation for when the inputs are at different frequencies. The circuit is simulated with a frequency difference of 100 MHz to show the Doppler Effect.

63 51 Figure 42 Schematic for an Ideal Mixer Figure 43 - Mixer Output from Different Input Frequencies Then the Mixer is converted to microstrip lines. The difference between the microstrip circuit and the ideal circuit is the attenuation in the signals. There is attenuation in both the local oscillator signal and the signal from the receiver in the microstrip circuit.

64 52 Figure 44 Schematic for Mixer Figure 45 Simulation Results for Mixer Circuit Item Quantity Rogers Duroid 5880 Substrate 1 PIN Diode 2 Pasternack SMA Jack (up to 18 GHz) 3 Table 9 Mixer Bill of Materials

65 Low Pass Filter The design for this filter is completed using the Filter Design tool in ADS. The low pass filter specification is a maximally flat filter with a cut off frequency of 2 khz. Figure 46 - ADS Filter Design Guide

66 54 Figure 47 Schematic for Lumped Elements Filter. Figure 48 - Low Pass Filter Simulation Results The simulation results match the expected results from the filter design guide; the negative 3 db is about 2 khz, and the negative 20 db frequency is about 5 khz. These frequencies are chosen to keep a maximum of three components.

67 55 Chapter 4 CIRCUIT FABRICATION AND MEASUREMENTS All of the PCBs are milled using a T-TECH QC5000 PCB mill [17]. When using the PCB mill, the substrate has to be held still in order to get the best cut. There are pins protruding from the waste board through the substrate on the center top and center bottom ends. These pins roughly secure the substrate, but since the holes on the substrate are slightly larger than the pins, it allows the substrate to shift up to five mils during milling. When the end mill etches the board, it is plunged down by an air compressor and is stopped by a plastic foot. The plastic foot grips the substrate tightly, which shifts the board if it is not secured properly. Taping the substrate down with masking tape at its edges helps keep the board from shifting. The substrates are sometimes warped in various areas and they need to be physically pressed down by hand while the QC5000 mills the substrate. In addition, the end mill s height has to be adjusted by using the dials on the QC5000 throughout the milling duration because the height of the copper is sometimes uneven throughout the substrate. The speed of the cutting bit has to be specific. Slow speeds could damage the routing bit, and high speeds do not cut the material well. For the mill that is set up in the microwave lab, a 20-mil end mill at RPMs makes the best cuts after trying with RPMs and RPMs. After the milling process, the components of the circuit are soldered onto the PCBs. The difficulty with soldering chip components, such as resistors and capacitors (most components in this project are 0805 size), is dealing with the heat. The components are small enough that heat quickly travels to the other end of the component, melting a different soldering point; it could also damage the component. To contain the heat at a specific area, a large metal block is placed

68 56 under the circuit board while soldering. The large metal block acts like a heat sink. This helps when soldering chip components. The fabricated circuits in this project are antennas, oscillator, high gain amplifier, power divider, and mixer. All of the components, except the mixer, are tested after fabrication. The equipments used for testing the fabricated circuits are an HP8720C Network Analyzer, an HP 8350B Sweep Oscillator, an HP 8592L Spectrum Analyzer, and a Power Designs TP340 Power Supply. The HP8720C is a two port Network Analyzer that operates between the frequencies of 50 MMM and 20 GGG. The HP 8350B is an oscillator that operates between the frequencies of 10 MMM and 20 GGG. Lastly, the 8720C is a Spectrum Analyzer that operates between the frequencies of 9 kkk and 22 GGG. 4.1 Antenna The properties of the PCB are described in section 3.1 Antenna. The layout for the antenna is shown in Figure 49. In order to connect the ground path, two small tabs to the left and right of the trace are added to attach the solder. Once the soldering is done, a razor blade is used to remove excess trace. Figure 49 - Layout of Signal and Ground Layers for Antenna

69 57 Figure 50 Antenna Signal Path Figure 51 Antenna Ground Path Two antennas are fabricated, but the above figures only show one antenna. The second antenna is very similar to the first antenna and is fabricated using the same Gerber files; therefore, it is not displayed. NETWORK ANALYZER PORT 1 PORT 2 COAX DUT Figure 52 - Antenna Test Setup To test the antenna, a network analyzer, and a coax cable is used. S-Parameters for a oneport circuit are tested for frequencies from 50 MMM to 20 GGG.

70 58 Figure 53 Antenna Test Results on Network Analyzer Parameter Simulated Result Actual Result Percent Difference Return Loss, S 11 at 10 GGG 12 dd 7 dd 42 % Table 10 - Comparison of Simulated and Actual Results for Antenna The results from the Network Analyzer show that the reflection at 10 GHz is negative 7 db. The lowest value of the output is at 11.2 GHz. The actual results are better at some frequencies and worse at some frequencies, as shown in the simulation in Figure 7. The suspected reason that the test results are different from the simulated results is because the input port is not modeled properly in the simulation. The ground path of the antenna has extra tabs where the ground of the SMA jack is soldered. The conductor that extended beyond the length of the SMA jack is cut off, which is not part of the simulation. In a future implementation, the SMA jack will be part of the HFSS model.

71 Oscillator The properties of the PCB are described in section 3.2. The layout for the oscillator is shown in Figure 54. The connection for the SMA jack is fed in from the ground layer of the PCB then soldered onto the output port. Figure 54 - Layout of the Oscillator

72 60 Figure 55 - Fabricated Oscillator POWER SUPPLY DUT COAX SPECTRUM ANALYZER Figure 56 - Oscillator Test Setup with Spectrum Analyzer To test the oscillator, a spectrum analyzer, and a coax cable is used. A bias-tee is used at the output of the DUT and acts as an extra capacitor in case the DC Block capacitor on the circuit fails.

73 61 Figure 57 - Oscillator Test Results on Spectrum Analyzer Parameter Simulated Result Actual Result Percent Difference Frequency of Oscillation 9.7 GGG GGG 3.8 % Table 11 - Comparison of Simulated and Actual Results for Oscillator The results from the Spectrum Analyzer show that the oscillation is GGG with a power of negative ddd. The simulated oscillation is 9.7 GGG; therefore, the difference is 3.8 %. The obvious reason for the difference is due to the terminal transmission line. The width is originally four mils, but has to be increased to 15 mils for fabrication. There is also a microstrip tee on the load side, which is not accounted for in the simulation.

74 Amplifier The high gain amplifier is fabricated on a Duroid 5880 substrate. To make sure there is enough ground for the circuit, large ground pads are connected to each emitter. The ground pads contain multiple connections to the ground layer using a copper wire High Gain Amplifier The properties of the PCB are described in section The layout for the amplifier is shown in Figure 58. SMA Jacks are soldered to edge of the board for input and the output. Figure 58 - High Gain Amplifier Layout

75 63 Figure 59 - Max Gain Amplifier Fabricated Circuit POWER SUPPLY FUNCTION GENERATOR COAX DUT COAX SPECTRUM ANALYZER Figure 60 - Amplifier Test Setup with Spectrum Analyzer To test the amplifier, a spectrum analyzer, and a coax cable is used at the output. A function generator and a coax cable is used at the input. Each port of the DUT, the input and the output, had a bias-tee connected and acts as extra capacitors in case the DC Block capacitors on the circuit fail.

76 64 Figure 61 - Max Gain Amplifier at 5 GHz on Spectrum Analyzer Frequency (GHz) Simulated Gain (db) Actual Gain (db) Percent Difference NNNN N/A NNNN N/A % % % NNNN N/A % % NNNN N/A %

77 % % NNNN N/A NNNN N/A Table 12 - Comparison of Simulated and Actual Results for Max Gain Amplifier The circuit is tested using the HP8350B oscillator to power the input and the Spectrum Analyzer to display the output. Although the amplifier does not work quite as expected at the intended frequency, it amplifies signals at other frequencies. The best gain is 8 db at 3 GHz. Since the performance of the amplifier is not what is expected, there are a few possible reasons for the cause. The main reason is improper modeling of transistor ground connection, which may have caused instability at another frequency, but the oscillation amplitudes are not high enough to be registered by the Spectrum Analyzer. The other reasons are improper modeling of the RF Choke inductors. The RF Chokes should have been modeled with interconnects between them and the microstrip tees instead of modeling the connection straight on to the tees. Lastly, the components may have been placed too close to each other and they introduced parasitic capacitance. In a future implementation, more distance will be maintained between the components by using longer interconnects, and to properly model the transistor s ground connection.

78 Power Divider The properties of the PCB are described in section 3.4. The layout for the power divider is shown in Figure 62. SMA Jacks are soldered to the edges of the board. To secure the ground for the 50 Ω terminated port, a strip of copper is soldered from the grounded end of the resistor to the ground layer. The strip is also soldered to the ground of the SMA jack connected to port 1. Figure 62 - Power Divider Layout

79 67 A 50 Ω terminal has to be fabricated in order to test the power divider on a two-port Network Analyzer. This is done by cutting the signal path from an SMA jack and soldering a 50 Ω resistor from the signal path to the ground. During the tests, this terminal emulates a device connected to it and absorbs half of the power. Figure Ohm Terminal Figure 64 - Fabricated Power Divider

80 68 NETWORK ANALYZER PORT 1 PORT 2 NETWORK ANALYZER PORT 1 PORT 2 50 Ohm Terminal 1 2 DUT DUT 3 50 Ohm Terminal Port 3, Forward Transmission Test Setup Port 2, Forward Transmission Test Setup Figure 65 - Power Divider Test Setups with Network Analyzer To test the power divider, a network analyzer, a 50 Ω terminal, and a coax cable is used. S-Parameters for a two-port circuit are tested for frequencies from 50 MMM to 20 GGG. First, port 2 is terminated with the 50 Ω terminal, and port 3 is tested. Then port 3 is terminated with the 50 Ω terminal, and port 2 is tested.

81 69 Figure 66 - Port 3 Test Connection Figure 67 - Port 2 Test Connection Figure 68 Forward Transmission at Port 3, S31 Figure 69 Forward Transmission at Port 2, S21 Figure 70 Return Loss at Port 1, S11

82 70 Parameter Simulated Result Actual Result Percent Difference Forward Transmission at Port 2, S dd dd 25 % Forward Transmission at Port 3, S dd dd 16 % Return Loss, S dd dd 95 % Table 13 - Comparison of Simulated and Actual Results for Power Divider Figure 66 and Figure 67 show the test setup on the Network Analyzer. The isolated port is terminated with a 50 Ω resistor and the open port is terminated with a 50 Ω connector. Figure 68 and Figure 69 show that the outputs from the two ports are very similar to each other and are close to the simulated circuit. The output at port 3 shows negative 4 db and the output at port 2 is negative 3.7 db. Figure 70 shows that the circuit is matched because the reflection is negative 14.6 db. It is an acceptable number although the percent difference of the actual result from the simulated result is very high. The cause may have been from the isolated port not being grounded properly. In a future implementation, the resistor at the isolated port will have shorter connection to ground. 4.5 Mixer The properties of the PCB are described in section 3.5. The layout for the mixer is shown in Figure 71. SMA Jacks are soldered to the edges of the board.

83 71 Figure 71 Layout of the Mixer Figure 72 - Fabricated Mixer The mixer is fabricated, but it is not tested. The difficulty in the fabrication is connecting the SMA jacks. The mount on the jacks is large and it barely touches the circuit. This can cause unintended reflections. The diodes used are PIN diodes that are able to operate at high frequencies. The mixer is not tested because the low pass filter is not fabricated. The mixer and the low pass filter are needed to feed in signals of two frequencies and output the intermediate frequency. Measurements for this component will be in a future work.