Pulse-Width Modulated CMOS Power Amplifiers

Transcription

1 ED R E S U ATU C FO E FE SU S I CREATAS Pulse-Width Modulated CMOS Power Amplifiers Jeffrey S. Walling and David J. Allstot M odern wireless communications systems are now being almost fully integrated into radio frequency (RF) systems-on-chip (SOC). The power amplifier (PA) is currently the gating element to the realization of a full complimentary metal-oxide-semiconductor (CMOS) RF-SOC solution due to its relatively poor performance when compared to counterparts designed in III-V compound semiconductor technologies. CMOS suffers in comparison for two main reasons: 1) Scaling of Jeffrey S. Walling (noyade@u.washington.edu) and David J. Allstot (allstot@ee.washington.edu) are with the Department of Electrical Engineering, University of Washington. Digital Object Identifier 1.119/MMM Date of publication: 14 January /11/$ IEEE February 211

2 the minimum feature size, which serves to make the devices faster, has the undesired effect of lowering the voltage stress tolerance of the devices. Lowering of the supply voltage forces the PA to operate with higher current, using a passive matching network to transform the impedance of the antenna (e.g., 5 V) to a much lower value. This results in lower efficiency because the loss in this network is proportional to the impedance transformation ratio. 2) Passive components, especially inductive elements on CMOS substrates, incur significantly more loss than those on III-V substrates because the CMOS substrate has higher conductivity. As a consequence, there is more loss with CMOS substrates due to electromagneticcoupling-induced lossy eddy currents. The loss in peak efficiency is exacerbated by modern wireless communication standards that utilize nonconstant envelope modulation (e.g., orthogonal frequency division multiple-access, quadrature amplitude modulation, etc.). Due to the demand for higher data rates, these nonconstant envelope modulation methods have been adopted more widely because they allow for a reduction in the symbol rate of the signal. This reduces the bandwidth occupied by the signals by allowing more than 1 bit of information to be transmitted per symbol at the expense of encoding information in the amplitude domain. For PAs, this is troublesome because the amplifier is designed to achieve peak efficiency only when it is saturated; nonconstant envelope modulation forces the average power transmitted to be reduced from the peak or saturated output power of the PA, resulting in lower average efficiency. A plot of the efficiency characteristic of a linear PA operating in a Class-B mode accompanied by the envelope probability density function (pdf) of an IEEE 82.11a [1] symbol is shown in Figure 1. It should be noted that, although the Class-B PA is not by nature a linear PA, the operation of the PA does use the transistor as a linear transconductor. The Class-B PA achieves a peak efficiency of 78.5% for the peak output voltage, but, in amplifying an IEEE 82.11a signal, it would rarely operate near this peak. In fact, the average operating point is approximately 22% of the peak voltage, resulting in a significant reduction in efficiency. CMOS PAs as are unlikely to be realized for applications that demand several watts of output power, but they offer an attractive solution for mobile devices, providing that they can outperform their III-V counterparts in terms of cost, scale of integration, and average efficiency. Most of the effort in scaling CMOS technology over the last three decades has been aimed at improving the performance of CMOS devices as switches, thus, it stands to reason that amplifiers that take advantage of improved switching performance can offer improvements over a linear counterpart. However, switching amplifiers cannot linearly Modern wireless communications systems are now being almost fully integrated into RF systems-on-chip. η (%) Env. p.d.f. Class B η Normalized Envelope (V) amplify signals that have variable input amplitudes (e.g., nonconstant envelope modulation). Many methods for linearization of saturated amplifiers (e.g., switching amplifiers) have been proposed, such as outphasing (e.g., Chireix and linear amplification with nonlinear components) [2][4], supply modulation (e.g., envelope tracking and envelope elimination and restoration and polar transmitters) [5][8], and pulse-width modulation (PWM) [9][12]. The former methods rely on either large passive combinatorial networks (outphasing), or complicated analog baseband circuitry (supply modulation) in order to achieve good linearity, while the latter (PWM) can be achieved without extra passives or analog circuitry. This makes the PWM technique attractive for integration as it can more favorably take advantage of technology scaling. For these reasons, this article focuses on implementing PWM PAs in CMOS. Amplifier Topology Selection There are three commonly used switching PA topologies, Class-D, -E and -F, as shown in Figure 2. They all work by switching energy into a resonant tank at a fixed frequency and operate efficiently by avoiding overlap of the voltage and current waveforms in the switching transistor, though the means by which they achieve these behaviors are quite different. The Class-D amplifier has been used extensively for the PWM applications, but it does have several drawbacks compared to the others. Most notably, it has a large parasitic drain capacitance due to the large power transistors (M P and M N ) that must be charged and discharged every cycle, resulting in a large dynamic power dissipation that increases linearly with Probability (%) Figure 1. Class-B drain-efficiency characteristic and IEEE 82.11a envelope probability density function. February

3 Over any modulation envelope, the Class-E PA has higher efficiency than its Class-B counterpart. frequency. This capacitance can be tuned using an inductor at the expense of narrowing the frequency response of the amplifier and increasing its die area (cost). Additionally, significant care must be taken to avoid the large crowbar current that can flow from the power supply to ground if M P and M N are closed simultaneously [9]. Although the Class-F amplifier does not suffer from these drawbacks, it does require either a transmissionline element or a lumped-element equivalent to achieve proper operation, which results in large die area (cost). Additionally, the goal of the transmission line is to create large impedances at odd harmonic frequencies in order to square the drain voltage. Due to the large parasitic drain capacitance, it is difficult to achieve a large impedance at high frequencies without requiring some additional tuning, again at the expense of the overall frequency response [13]. The Class-E amplifier actually takes advantage of the large parasitic drain capacitance that is used to delay the rise of the drain voltage until after the drain current has returned to zero [14]. In a typical design, the transistor provides part of the necessary capacitance with additional capacitance added, using a lumped component. The Class-E PA does suffer from potential voltage breakdown issues, although there are many solutions to mitigate these problems [15], [1]. Pulse-Width Modulated Class-E PA The output power of a Class-E PA is insensitive to variations of amplitude at the input of the PA; thus, another means must be used to linearly amplify a signal with varying envelope modulation. Conceptually, the Class- E PA works by storing energy in an inductor [L d, Figure 2(c)] when the switch is closed and then releasing that In M P M N energy into a passive resonant network L d, L m, C d, C m [Figure 2(c)] when the switch is opened. Thus, if the duration of the switch closure is reduced or increased, the amount of energy stored per cycle is reduced or increased proportionally. A change in duty cycle therefore corresponds to a change in output power. The variation in input power1p i 2, output power 1P o 2, and drain efficiency 1h2 of a Class-E PA with respect to duty cycle are determined from [16]. P i 5 V DD 2, (1) R DC P o 5 V2 DDg 2 R 2R DC, (2) h 5 g2 R, (3) 2R DC g 5 2y sin f 1 sin y 2 2y cos f 1 cos y 1 2 cos f 1 sin y 22 sin1f2y2 sin y sin f sin 2y cos12f1c21y cos c, R DC 5 L d L d L m Out ω o Out L m Z o In In C d C m R opt L C Z opt (a) (b) (c) Figure 2. Switching PA topologies: (a) Class-D, (b) Class-F and (c) Class-E. (4) 1 2pB 12y2 1 2yg sin1f 2 y2 22g sin f sin y2, (5) y 5 1p 2 12 # d, (6) where V DD is the supply voltage, R is the optimum termination resistance chosen to achieve the desired output power, g is the dc-ac power transfer ratio, R DC is the equivalent dc-resistance of the switch, and d is the duty cycle. Optimum efficiency is achieved for B R, d 5.5, and c º, where f is calculated according to [16]. The power transfer characteristic of the Class-E PA with respect to duty cycle is shown in Figure 3(a), and its efficiency with respect to the normalized output voltage is plotted in Figure 3(b). For comparison, the efficiency characteristic of an ideal Class-B PA is also shown along with the envelope probability density function for the aforementioned IEEE 82.11a modulated signal. It is important to note that for all voltages, the pulsewidth modulated Class-E PA has higher efficiency, which means that over any modulation envelope, the Class-E PA has higher efficiency than its Out Class-B counterpart. C m Instantaneous Versus Average Efficiency Two efficiency metrics are important when dealing with PAs operating on non-ce modulated signals. Instantaneous 54 February 211

4 power-added efficiency (PAE) is the PAE occurring at one specific value of the envelope P o 1V2 PAE1V2 5 P DC 1V2 1 P i 1V2 5 P o 1V2 P in 1V2. (7) This metric is typically only important at the peak output voltage V DD. Because efficiency degrades significantly with a reduction in output voltage, it is important to design the amplifier to have a large peak instantaneous efficiency. A more important metric for nonconstant envelope modulated signals is the average efficiency, which relates to the total power consumed across the range of expected envelope voltages of the signal. To compute the average efficiency, the output power 3P o 1V24 and input power 3P in 1V24 are weighted by the envelope probability density function 3p1V24 of the modulated signal and integrated. The average efficiency is then the ratio of the average output power P o, avg to the average input power PAE avg 5 P o, avg P in, avg 5 e Vmax P V o 1V2 # p1v2dv min. (8) e Vmax P in 1V2 # p1v2dv V min For an IEEE 82.11a signal, the average efficiency for a pulse-width modulated Class-E PA is 15%, compared to 7.5% for a Class-B PA. Because the average efficiency provides an estimate of the energy consumed in real time by a mobile communication device during transmission, it is a more important metric than the instantaneous efficiency. In most mobile communication devices, the PA is the dominant consumer of energy from the battery. Because the pulse-width modulated PA uses only half the average energy of a linear PA, it enables an extension of the talk time and mobility of the device and reduces the energy required to charge the battery. Bandpass Pulse-Width and -Position Modulation In bandpass pulse-width and -position modulated systems, one symbol is transmitted during each cycle of the carrier frequency [11] s1t2 5 a1t2cos1vt 1 f1t22, (9) where s1t2 is the transmitted symbol, a1t2 and f1t2 are the envelope and phase components of the symbol, respectively, and v is the RF carrier frequency. A bandpass pulse-width and -position modulated symbol is created by mapping a1t2 to the width [duty cycle, d1t2] and f1t2 to the edge-time of the pulse [1]. One advantage of bandpass pulse-width and -position modulation is that the entire system up to the PA can be implemented using digital signal processing (DSP) It is desirable to use only the filtering provided by the output network of the PA in order to minimize the loss and maximize efficiency. Normalized P out (db) η (%) Input Duty Cycle (%) (a) Class E η Class B η Env. p.d.f Normalized Output Voltage (V) (b) techniques. This allows the design to exploit the scaling advantages CMOS offers, including a reduction in power. Methods to generate a bandpass pulse-width and -position modulated signal are examined in the following. Bandpass Delta-Sigma Modulation In a bandpass delta-sigma modulated system used for PWM (Figure 4), the baseband modulated signals are first up-converted in frequency and then mapped to a binary format via quantization in the delta-sigma modulator [9]. This technique is well known to create significant quantization noise that is shaped to be out-of-band. This noise is troublesome, as it occurs just before the PA, where it is amplified and broadcast, which creates the potential for problems with regulatory standards. It is desirable to use only the filtering provided by the output network of the PA in order to minimize the loss and maximize efficiency. The PA in [9] was able to meet the code division multiple access (CDMA) IS-95 [17] specifications for out-of-band noise, but it might have difficulty Probability (%) Figure 3. (a) Output power versus duty cycle. (b) Efficiency versus output power for Class-E and -B PAs. February

5 I(t ) Baseband Modulation Q(t ) satisfying wider bandwidth standards [e.g., wideband CDMA (WCDMA) [18], worldwide interoperability for microwave access (WiMAX) [19], etc.]. Comparator-Based Bandpass Pulse-Width and -Position Modulation In order to avoid the out-of-band noise problem associated with delta-sigma modulation, a comparator-based system can be used wherein the signal is not quantized so there is no associated quantization noise to be shaped out-of-band (Figure 5). Unfortunately, this system is subject to linearity problems for a couple of reasons. First, the signal is divided into a low-frequency amplitude modulated path, a1t2, and a high-frequency phase modulated path, f1t2, using a coordinate rotation digital computer (CORDIC) algorithm. This difference in frequency means that the paths experience different delays, and, if there is a mismatch at the comparator, the result will be loss of fidelity of the signal due to the a1t2 signal being combined with the wrong f 1t2 signal. The error in recombination can result in two problems: spectral regrowth and transmit bit errors. Spectral regrowth occurs because the mismatch causes the spectral components associated with the a1t2 and f 1t2 signals to spread. More seriously, the error in recombination means that the wrong data is transmitted and DSP DSP Digital Frequency Upconversion I(t ) a(t ) Baseband Modulation CORDIC Q(t ) φ(t ) DAC DAC BP-ΔΣ Modulator A Z 2 Z 2 Figure 4. Architecture of a bandpass delta-sigma (BP-DS) modulated transmitter [9]. VCO Comparator Figure 5. Comparator based bandpass pulse-width and -position modulation [11]. x2 + B results in high bit error rate and incorrect demodulation of the signal at the receiver. Second, the comparator is subject to drift due to voltage and temperature changes, Switching PA which can again affect the signal fidelity. In [11], the authors added a low-pass negative feedback loop at the output of the a1t2 digital-to-analog converter (DAC) to improve linearity and compensate for the aforementioned drawbacks; although this low-pass feedback does impact the bandwidth of the system, it is not as problematic as feeding back the bandpass signal due to better delay performance in the feedback path. However, the feedback system does add concerns regarding the stability. Finally, this solution loses the advantages of scaling with the addition of analog components that use a larger area and consume more power than a more digital implementation. Outphasing-Based Bandpass Pulse-Width Modulation The outphasing based bandpass PWM system (Figure 6) [1], [2] achieves a solution that is mostly digital, does not have significant out-of-band noise, and does not have issues associated with path delay mismatches due to the processing of signals at different frequencies. To generate a bandpass PWM modulated signal 1In2, the baseband signal is first transformed from a Cartesian 1I, Q2 to a polar representation 1A, f) using a CORDIC algorithm and then converted to two-phase modulated outphased signals 1S 1, S 2 2. The amplitude information is then stored in the difference in phase between the two signals and can thus be decoded to a binary pulse using a digital logic-based combiner such as the NAND/NOR shown in Figure 6. By operating in the digital domain, the signal is less subject to the process, voltage, and temperature variations of the comparator-based architecture, and thus there is no need for feedback. This makes the outphasing-based method inherently wider bandwidth than the prior architecture and again enables a solution that takes full advantage of CMOS technology scaling. A slight modification to the system Switching PA that uses a variable delay cell and a NOR gate to produce the variable pulse-width was 56 February 211

6 In I I, Q Map Q I A CORDIC Q φ cos 1 (A) + φ 1 s 1 PM φ 2 s 2 Limit and Retime Limit and Retime PWM Combiner PWM PWM Figure 6. Outphasing-based bandpass pulse-width modulation (PWM) generator and analog representations of the waveforms. proposed in [21]. Fundamentally this system operates similarly to the outphasing system described previously and is subject to similar limitations. Limitations of Pulse-Width Modulated Systems The main limitation of a CMOS pulse-width modulated system is the minimum width of a pulse that can be processed by digital logic without being swallowed. Pulse swallowing occurs because a finite amount of time is necessary to change the voltage on the gate of the PA output stage. A pulse is swallowed when the driving circuits are not able to change this voltage fast enough to turn on the transistor for the duration of the pulse. This effect is exacerbated in high-power PA applications because the gate width of the output transistor is necessarily very large in order to handle the high current levels that flow through it. This wide gate width results in a large capacitance, and thus a large RC time constant associated with changing the voltage level at the input to the PA. The amount of dynamic range available for a given pulse width is shown in Figure 7. Note that the x-axis is limited to 1 ps to more clearly illustrate the dynamic range of the higher frequency signals. The normalized output power versus pulse width is plotted for three frequencies, 1, 2.5, and 5 GHz, along with a bold line at 4 ps, which represents the minimum pulse width Normalized Output Power (db) GHz Pulse Width (ps) 2.5 GHz 1 GHz that could be processed by a PA designed to output 1 W in 65-nm CMOS. It is clear that the dynamic range is affected significantly by the frequency of operation, e.g., a pulse-width modulated PA operating at 5 GHz has ~13 db less dynamic range than one operating at 1 GHz. This limitation dramatically affects the modulation that can be processed by the PA. For example, a signal with orthogonal frequency division multiple-access modulation (e.g., IEEE 82.11a) could be processed by a PWM PA at 1 GHz but not at 5 GHz. A comparison of the basic architectures is presented in Table 1. For more details, see [22][27]. 8 1 Figure 7. Normalized output power versus pulse width. TABLE 1. Pulse-width modulation architecture comparison. Bandpass Delta Sigma Pulse-Width and -Position Modulation Comparator Bandpass Pulse-Width and -Position Modulation Outphasing Bandpass Pulse-Width and -Position Modulation Digital/Analog Components Before PA All digital before PA/no analog components necessary High speed comparator, low-pass filter and op-amp in feedback loop All digital before PA/no analog components necessary Miscellaneous DS modulator shapes noise out-of-band, requires additional filtering Oversample ratio limits peak signal bandwidth Analog components use bias current, Reduce efficiency Mismatches in a(t), f(t) can result in errors Mismatches in a(t), f(t) result in reduced fidelity References/Additional Reading [8] [1], [11], [16], [21] [9], [17], [22] February

7 Slab Inductors b 3 L 1N C1N b b 1 b 2 C 2N + Out + S 1 Clock RX and Retime b Inverter Drivers v b L1P L 2P C 2P C 1P + S 2 Clock RX and Retime b Figure 8. Topology of an outphasing pulse-width modulated PA. 1.6 mm 29 Clock RX, Retiming and PA Drivers Output Stage Slab Inductor Output Matching Network 1.3 mm Ootput Power (dbm) Slab Inductor Figure 9. Class-E outphased pulse-width modulated PA microphotograph in 65-nm CMOS. 65-nm Implementation of Outphasing Bandpass Pulse-Width Modulation To highlight an example of a pulse-width modulated PA system, the implementation of the outphasing-based bandpass pulse-width modulated PA discussed previously is now considered. A top-level schematic of an outphasing pulse-width modulated PA is shown in Figure 8. It receives two outphased signals, S 1 and S 2, and, after retiming, the signals are combined and buffered to drive the input of the PA. Note that all circuitry up to the output of the inverter drivers (Figure 8) is designed using standard cell-based static CMOS digital logic, resulting in significant area and power savings compared to an analog solution. The inverter drivers are designed Efficiency (%) Duty Cycle (%) (a) Class E η 15 1 Class E PAE Class B η Output Power (dbm) (b) Figure 1. (a) Measured output power versus input duty cycle and (b) PAE and drain efficiency (h) versus input duty cycle. with a scaling factor of 2 and sized appropriately to switch the large gate capacitance of the PA output stage. The PA is split into four parallel paths that can be independently enabled/disabled via control 58 February 211

8 bits, b 2b 3, to further enhance the dynamic range of the PA. Additionally, slab inductors are used at the output rather than traditional spiral inductors. This is an improvement because the slab inductors incur less loss than a spiral inductor, and they can handle larger currents because they do not use a crossover layer on a lower, usually thinner, metal layer. A microphotograph of an outphased pulse-width modulated PA is shown in Figure 9. Fabricated in a 65-nm low-leakage CMOS process with eight layers of metallization, it occupies 1.6 mm mm. The The purpose of the pulse-width modulated PA is to amplify nonconstant envelope modulated signals using a switching PA. output stage operates from V DD V, while the digital circuitry operates from V DD,Logic V to deliver 28.6 dbm into a 5-V load. The PA operates Ch1 pi/4 Meas Time 1.5 Range: mv Pulse Not Found Ch1 Spectrum dbm Range: 1 dbm Pulse Not Found 1. logmag 3 m/div 1 db/div dbm Center: 2 MHz (a) RBW: khz Ch1 pi/4 Err Vect Time Range: mv 2% Pulse Not Found (b) Span: 625 khz TimeLen: μsec LinMag 2% /div Ch1 pi/4 Syms/Errs EVM = Mag Err = Phase Err = Freq Err = IQ Offset = Quad Offset = % Start: sym %rms %rms deg Hz db mdeg EVM = 4.6% rms P out = dbm PAE = 21% (c) %pk at sym %pk at sym %pk at sym Amp Droop = 16.5 udb/sym Gain Imb =.67 db (d) Stop: 11 sym Range: mv Pulse Not Found Figure 11. Vector signal measurement of the outphasing PWM PA with a p/4-dqpsk (nonconstant envelope) modulated input signal. Quadrants (a) signal constellation, (b) power spectral density, (c) instantaneous error vector magnitude, and (d) received data. February

9 over a bandwidth of GHz with peak efficiency and output power at 2.2 GHz. The output power, PAE, and h are shown in Figure 1. As desired, the output power varies versus the duty cycle, achieving a peak output power of 28.6 dbm for a 5% duty cycle and 22 dbm for an 18% duty cycle. The corresponding PAE values are 28.5% and 11%, respectively. The effects of pulse swallowing are seen for duty cycles less than 18% as the output power rolls off dramatically (and unpredictably) below this value. Also note the similar peak drain efficiencies between the Class-E and -B PAs, as predicted in Figure 3(b). Finally, the purpose of the pulse-width modulated PA is to amplify nonconstant envelope modulated signals using a switching PA. A vector signal measurement of a p/4-dqpsk modulated signal with a symbol rate of 192 khz and peak-to-average power ratio of ~4 db is shown in Figure 11. As noted, the PA achieves an average output power of 26.7 dbm at an average PAE of 21% with an error vector magnitude of 4.6 % rms. Conclusions The relentless scaling of CMOS circuits has led to the possibility of completely integrated RF-SOCs, including the PA. A CMOS PA likely will not achieve the same peak output power and efficiency as its counterpart in a III-V technology. It is conceivable, however, that by taking advantage of the strengths of CMOS switching devices, future CMOS PAs can win in terms of average efficiency and, perhaps more importantly, cost. PWM techniques offer one such potential solution, owing to the level of digital integration possible. Because of this, PWM PAs are expected to scale well, and the dynamic range possible with such amplifiers should increase as well because the faster devices will be able to process signals with smaller pulse widths. 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