XRT86L38EVAL EVALUATION SYSTEM USER MANUAL

Transcription

1 XRT8L8EVAL EVALUATION SYSTEM USER MANUAL Page of

2 EVALUATION KIT PART LIST This kit contains the following: XRT8L8EVAL Application Board XRT8L8 GUI Evaluation Software XRT8L8 0-ball TBGA XRT8L8EVAL User Manual XRT8L8 Datasheet FEATURES FPGA Design Which Controls the Framer/LIU and Supports Communication Between the PCI Bridge and the XRT8L8 PCI Bridge Connector for Easy Connection Through a Standard PC CD ROM Containing the GUI Software (Executable File) Line Interface Modules Coupled to the Receiver Inputs and Transmitter Outputs Power Supply Design Which uses the Supply Voltage From the PCI Bridge Accessible I/O Interface for Common Laboratory Equipment SYSTEM CONFIGURATION-LAB SETUP The XRT8L8EVAL application board is setup as a common test circuit. Figure shows a simplified block diagram of the default test configuration. PCI Bridge XRT8L8EVAL Board Graphical User Interface RJ ADDR[:0] DATA[7:0] JTAG XCS00E Spartan IIE (80 I/Os) XCF0S PROM Clock Reference ADDR[:0] DATA[7:0] OVERVOLTAGE PROTECTION XRT8L8 T/E Framer/LIU Combo Physical Interface Figure Simplified Block Diagram of the XRT8L8EVAL Application Board Page of

3 APPLICATION CIRCUITRY FPGA The XRT8L8EVAL uses an FPGA designed to control the Framer/LIU and support communication between the PCI bridge and the XRT8L8. The FPGA chosen contains enough I/O pins to support all eight channels with one configuration. By default, the FPGA is configured into an FPGA loopback mode, whereby the output pins from the Framer block are internally looped back to the input pins. This allows standard network equipment connected to the physical interface to monitor data integrity through a complete communication path. PCI Bridge XCS00E Spartan IIE (80 I/Os) XRT8L8 T/E Framer/LIU Combo Figure Simplified Block Diagram of the FPGA Interface Line Interface Module Internal Impedance The XRT8L8 has the termination impedance inside the LIU. No termination resistors are necessary for the transmit outputs or the receive inputs. This allows the user to have one bill of materials for all three line impedances. Figure is a simplified block diagram of the interface connection. OVERVOLTAGE PROTECTION XRT8L8 T/E Framer/LIU Combo Physical Interface Figure Simplified Block Diagram of the Interface Connection Page of

4 GRAPHICAL USER INTERFACE (GUI) INSTALLATION PROCEDURE The CD ROM contains the necessary files in order to fully evaluate the XRT8L8 evaluation board. By clicking on the xrt8lx evaluation vxxx.exe file, the GUI will automatically install all components. If properly installed,the GUI can be launched from C:\Program Files\Exar\XRT8LX Evaluation Software. Once the GUI is launched, the user is given a choice to launch the GUI in either T or E mode. Selecting will load the T FPGA or the E FPGA, respectively. The user is then presented with this menu. Page of

5 T TEST MENU The Test menu contains the necessary GUI for testing Bit-Oriented Signaling, Message-Oriented Signaling, Robbed Bit Signaling and Alarm & PMON Monitoring. In order to test these features, it is necessary to place the device in a Framer Local Loopback or an External Loopback by shorting Ttip/Tring to Rtip/Rring through the RJ connectors. Also, one should deselect the FPGA loopback in General Configuration from the Configuration menu. Page of

6 T BIT ORIENTED SIGNALING In order to Test BOS, select the desired channel, select a framing format that supports BOS such as ESF and ensure Controller and Data Link Bits are used. Then click Send. Page of

7 T MESSAGE ORIENTED SIGNALING In order to Test MOS, select a framing format that supports MOS, select a Fill Pattern, select a TSLOT conditioning (note that D/E Timeslot can be used with practically al framing formats) and select a HDLC Controller (Controller must be used when using Data Link Bits). Then click Start which begins the process of checking for received messages. Click Test to send the message. Page 7 of 7

8 T SLC9 Test In Order SLC9, ensure the framing format is SLC9, modify the SLC9 message to your liking. Other settings can be left at default. Then click Send. Click Check to check for received messages. Page 8 of 8

9 T ROBBED BIT SIGNALING MENU In order to Test RBS, select the desired channel, and then Subchannel (Time Slot) to be configured. Once the desired time slot is selected, the transmit signaling bits can be programmed. This menu is used in conjunction with the T Specific page from the General Configuration Menu. Page 9 of 9

10 ALARM & PMON MONITORING Page 0 of 0

11 E TEST MENU The Test menu contains the necessary GUI for testing Message-Oriented Signaling, CAS Signaling and Alarm & PMON Monitoring. In order to test these features, it is necessary to place the device in a Framer Local Loopback or an External Loopback by shorting Ttip/Tring to Rtip/Rring through the RJ connectors. Also, one should deselect the FPGA loopback in General Configuration from the Configuration menu. Page of

12 E MESSAGE ORIENTED SIGNALING In order to Test MOS, select a framing format that supports MOS, select a Fill Pattern, select a TSLOT conditioning (note that D/E Timeslot can be used with practically al framing formats) and select a HDLC Controller (Controller must be used when using Data Link Bits). Then click Start which begins the process of checking for received messages. Click Test to send the message. Page of

13 E SIGNALING TEST In order to Test Signaling, select the desired channel, and then Subchannel (Time Slot) to be configured. Once the desired time slot is selected, the transmit signaling bits can be programmed. This menu is used in conjunction with the E Specific page from the General Configuration Menu. Page of

14 ALARM & PMON MONITORING CONFIGURATION MENU The Configuration menu allows the user to provision the device into common modes for the Framer and LIU sections of the combo chip. Page of

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20 Page 0 of 0 AD LA C7 C -SERR AD[:0] CLK LA AD8 AD -DEVSEL AD7 R9.7k AD7 LA7 J7A PCI BRIDGE B B B B B B B7 B8 B9 B0 B B B B B7 B8 B9 B0 B B B B B B B7 B8 B9 B0 B B B B B B B7 B8 B9 B0 B B B B B B B7 B8 B9 B B B B B B7 B8 B9 B0 B B A A A A A A A7 A8 A9 A0 A A A A A7 A8 A9 A0 A A A A A A A7 A8 A9 A0 A A A A A A A7 A8 A9 A0 A A A A A A A7 A8 A9 A A A A A A7 A8 A9 A0 A A -DEVSEL AD C AD RD- CSn_88 AD R.7K -INTA AD D LED-0 -IRDY -TRDY LA AD9 -TRDY AD8 AD -STOP R8.7k INIT* -LOCK -SERR LD C LD C 0uF AD9 LD WR- AD9 ADS C LA8 DONE PME- AD0 LA9 IDSEL -RST AD -PERR AD CSn_FPGA AD AD0 AD AD8 AD IDSEL DIN LW_R AD AD LINT AD7 LD PROGRAM* AD AD AD7 R 7k DOUT AD -IRDY LD[7:0] R 70 -LOCK AD AD C0 LA0 AD AD AD9 CLK LA -CBE -CBE VIO LA0 AD8 VIO -CBE LD AD8 AD C8 AD AD9 AD0 LRST- AD9 C LA AD AD R 0 C AD0 AD -RST LA C9 LA LRDYn PAR AD8 PME- AD AD0 AD Q FDNN -INTA AD7 -CBE R.7k AD AD -CBE0 LD7 U PCI LA LA LAD LA LAD7 LA LAD8 LA LAD9 LA7 LAD0 LA8 LAD LA9 LAD LA0 LAD LA LAD LA LAD LA LAD7 LA LAD8 LA LAD9 LA LAD0 LA7 LAD LA8 LAD LA9 LAD LA0 LAD LA LAD LA LAD LA LAD7 LAD8 LAD9 AD AD0 AD9 AD8 AD7 AD AD AD AD CLK INTA# RST# FRAME# TRDY# IRDY# STOP# IDSEL DEVSEL# PERR# SERR# C/BE# C/BE# C/BE# C/BE0# PAR AD8 AD7 AD AD AD AD AD AD AD0 AD9 AD8 AD7 AD AD AD AD AD AD AD0 LW/R# LBE0# LBE# LBE# LBE# ADS# BLAST# EECS EESK EEDI EEDO LAD0 LAD LAD LAD LAD LAD LAD LAD0 LAD AD AD AD0 AD9 BTERM# CS# GP0 LOCK# LINTI MODE LCLK LREQ LRDYI# LGNT TEST LINTI ALE RD# WR# LRST# CS0# GP CS# CS# BCLKO TRST# TCK TMS TDO TDI GP7 GP GP GP GP8 PME# LPMInt# ENUM# VIO LEDon# LPMESet CPCISW C 0.0uF C AD R 7k AD7 C LA AD -CBE0 ALE PAR R7.7k C LA AD LA AD LD0 -FRAME C LA[:0] -STOP -CBE AD AD0 AD AD0 AD U 9CS 8 7 CS SK DI DO VCC PRE PE LA LD CCLK LCLK -FRAME -CBE LA0 AD -PERR AD0 Figure XRT8L8EVAL PCI Bridge (Schematic Page )

21 Page of LA[:0] TESTMODE TP T PACK0 DOUT pdben U.MHz 8 OE OUT PCLK LA MCLKIN PACK0 TP8 LD TSCLK LA LD[7:0] TDI TP TP T ALE LA8 LA LA U.MHz 8 OE OUT LA GPIO_0 DIN LA C8 0.UF ptype TOSCCLK LA0 LA LRST- LA9 GPIO_ LD7 GPIO_ PREQ DONE TXON 8KEXTOSC tale GPIO_ GPIO_ SPARTAN IIE RDtRD R 0 CCLK GPIO_ GPIO_ H JTAG trd R.7K TP T LD atestmode TSCLK GPIO_ 8KEXTOSC.MHz R OPEN GPIO_0 TP T ADS LA ptype0 LD TP9 LA0 EOSCCLK LINT LA[:0] tale MCLKIN INIT* TP LD LA7 ptype0 R9.7K PREQ atestmode EOSCCLK LD0 R0 0 CSn_88 LA0 R8.7K tcs R 00 GPIO_ R 0 TP T R OPEN MCLKOUTnT LD PROGRAM* BLASTn TP T LA GPIO_0 C7 0.UF LA LA TMS LA8 TESTMODE LA7 LA TP7 T LA.MHz XCS00E INTERFACE CSn_FPGA GPIO_ PREQ0 R7 OPEN MCLKOUTnE ESCLK PACK LA TP0 LA twr LA0 XRT8L8 LD JTAG_RING TOSCCLK LA TP T ptype ptype PCLK twr TP T LD TCK TP T LA UF Y7 AA7 Y W V AA M8 M M0 N7 N8 N0 Y9 AA9 AB9 W8 P8 M9 AB8 Y V9 P Y8 P AA W7 T T0 T8 T9 R R R8 R9 V0 V U U0 U8 U9 N9 P7 P9 N L L0 L8 AA AB D C B A E A C9 E E AB0 AA0 AA U AB W0 Y W C C B V7 AB7 L7 K K D C B A C G G G G G H TXON LOP 8KEXTOSC TOSCCLK EOSCCLK 8KHZSY GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ PREQ PREQ0 PACK PACK0 CSn_8L8 BLASTn ptype0 DATA0 DATA CS RD WR ptype ptype ADDR0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR7 DATA DATA DATA DATA DATA DATA7 GPIO_ GPIO_ TESTMODE atestmode MCLKIN MCLKOUTnE MCLKOUTnT TSCLK ESCLK SCK SCS SDI SRST SDO TDO TDI TCK TMS ADS LW_R M0 M M DONE PROGRAM INIT DIN DOUT CCLK pdben ADDR8 ADDR9 ADDR0 ADDR ADDR ADDR ADDR.MHz LCLK ALE tale twr trd PCLK tcs LD WR- ANALOG GPIO_ U7F F D G N P U W W W V V Y AB Y AA AC Y AB AF AA AA AA AD AD AB8 AD0 AE AE AA AB Y Y AA W W Y Y W L R W M R W V V V V U U U U U T T T P N N M T R R P P N N R P G B E D B E9 B8 E B A7 B7 A D7 B E7 A B D E C D C B E JTAG_TIP JTAG_RING TXON LOP RESET 8KEXTOSC TOSCCLK EOSCCLK 8KHZSY GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ PREQ PREQ0 PACK PACK0 fulladdr indirectaddr ptype0 PCLK pdata0 pdata pcs pas prd pwr ptype ptype pdben pdack paddr0 paddr paddr paddr paddr paddr paddr paddr7 pdata pdata pdata pdata pdata pdata7 paddr8 paddr9 paddr0 paddr paddr paddr paddr pint pblast GPIO_ GPIO_ TESTMODE TCK TRST TMS TDI TDO atestmode MCLKIN MCLKOUTnE MCLKOUTnT ANALOG LW_R LCLK 8KHZSY pdben tcs LA JTAG_TIP C9 0.UF LD0 BLASTn LD7 TP7 T LA LRST- GPIO_ GPIO_0 LD U 9.08MHz 8 OE OUT LD[7:0] ESCLK MCLKOUTnT LA CSn_88 LOP ptype PREQ0 8KHZSY LA9 LD TXON PACK TP T MCLKOUTnE LOP TDO LD LRDYn LD GPIO_ Figure XRT8L8EVAL FPGA Control (Schematic Page )

22 Page of RXSER RXSERCLK0 RXCHCLK7 TXSERCLK RXOH J RJ TXSY RXSY RXSER TTIP7 RXCHN7_ TTIP RXSY RXOH7 C RXOHCLK TXSERCLK TXSER RXSERCLK RXCHN7_0 RXCRCSY7 RXCRCSY RXSY7 RXSY RXSY XCS00E NETWORK DATA[7:] RXSERCLK RXSER TXCHN7_ C 0.8uF TXSY TXCHN7_ TXSERCLK RXSERCLK RXSER0 RXLOS RXSER7 RXSERCLK7 RXSERCLK TXOHCLK7 UB V W Y AA V U W W AB AA AB U V W AA AB U V Y AB Y W V U0 V0 Y0 W0 AA0 U9 V9 Y9 W9 AB0 AA9 AB9 W8 V8 AA8 AB8 W7 V7 AA AA7 AB7 W V AA AB AB AB TXOH7 TXOHCLK7 TXCHCLK7 TXSERCLK7 TXSER7 TXCHN7_ TXCHN7_ TXCHN7_ TXCHN7_ TXCHN7_0 TXSY7 TXMSY7 RXOH7 RXOHCLK7 RXCHCLK7 RXSERCLK7 RXSER7 RXCHN7_ RXCHN7_ RXCHN7_ RXCHN7_ RXCHN7_0 RXSY7 RXCRCSY7 RXCASY7 TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY RXSY J RJ TRING7 TXSER RXSER RXSER RTIP TXCHN_ RXOHCLK7 TXSER TXSER TXSER0 RXCASY7 RXCHN_0 RXSY TTIP RXSERCLK0 TXSY RXCHN_ TXSY RTIP RXSY7 TXSY TXSERCLK0 TXSERCLK0 TXCHCLK7 RXSERCLK QUAD TRANSFORMER FOR CHANNELS [7:] TXSERCLK7 RXSY0 TXCHN_ TXOHCLK TXSY XRT8L8 TXSERCLK TXSY TXSER TXCHN7_ TXSY TXSERCLK J RJ RRING TXSERCLK TXSERCLK RXSY C0 0.8uF RXCHN_ RXSY0 RXSER TXSER0 RXCHN7_ RXSERCLK TXSER C H TXSER TXSER TRING RXCASY TXSY TXCHN7_0 RXSERCLK RXSERCLK RXCHN_ RXSERCLK RXSER TXSY7 RXSER RXCHN7_ RXSY RXSER0 TXSERCLK TXSY RXSER TXMSY7 TXSER RXCHN_ C RTIP7 RXSER7 TXMSY TXSERCLK RRING7 RRING TXCHN_0 TXCHN_ TXSERCLK7 RXSY TXCHCLK RXSERCLK7 TXSER7 C TXSERCLK RXSY TXSY J RJ RXCHN7_ RXLOS7 TXSY7 U7B U U V W AC AE AB AB AE AB AC AD AD AC AE AF AF7 AE7 AF AB AB7 AF AE AF AC7 AB8 AC AD AF AD AF0 AC0 AD0 AE AB9 AE8 AF8 AE9 AF9 AB0 AD8 AC8 AE AE AE AB AE AF AD AF AB AC AB AE0 AC9 T R T U AC TTIP7 TRING7 RTIP7 RRING7 TXOH7 TXOHCLK7 TXCHCLK7 TXSERCLK7 TXSER7 TXCHN7_ TXCHN7_ TXCHN7_ TXCHN7_ TXCHN7_0 TXSY7 TXMSY7 RXOH7 RXOHCLK7 RXCHCLK7 RXSERCLK7 RXSER7 RXCHN7_ RXCHN7_ RXCHN7_ RXCHN7_ RXCHN7_0 RXSY7 RXCRCSY7 RXCASY7 RXLOS7 TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TTIP TRING RTIP RRING RXLOS TTIP TXSER RXSERCLK TXSER TXOH7 TRING RXSY TXSY0 SPARTAN IIE RXSER TXOH RRING TXSERCLK RXCHCLK RXSERCLK TXSY TXSER T SMD TTP RXCT TRP RTP RRP TTP RXCT TRP RTP RRP TTP RXCT TRP RTP RRP TTP RXCT TRP RTP RRP RRS RTS TRS TTS RRS RTS TRS TTS RRS RTS TRS TTS RRS RTS TRS TTS TXSER7 TXSY0 TRING S HEADER x TXCHN7_ RXSERCLK TXSERCLK RXSER RXSER RTIP RXSY TXCHN_ Figure XRT8L8EVAL FPGA Channel Control (Schematic Page )

23 Page of RXCHN_ RXOH RXSER RRING C7 0.8uF RXOHCLK SPARTAN IIE RXSY C 0.8uF RXSY RXCHCLK RXCASY TXCHN_ TXSERCLK RXOH RXCHN_0 RXCHN_ RRING TXCHN_ RXCRCSY RXSERCLK TXSERCLK TRING TTIP RXSER TXSERCLK TXOHCLK RXSY RXCHN_ RXSY RXSY RXSY RXCHN_ TXCHN_ H TXCHN_ TRING TXSY RXCHCLK TXMSY RXSERCLK XCS00E FRAMER BLOCK[:] RXOHCLK TXSY U7C P P P R M M M N AF0 AC AD AB AE AF AB AC AB AE AD AC AF AD AE7 AF7 AE AC9 AC8 AD7 AC7 AB7 AF8 AD8 AF9 AF AE9 AF AF AD AE AB AD9 AE0 AC0 AF AD AF AC AA Y AB AD AC AB AC AF AE AD AE AB AD TTIP TRING RTIP RRING TTIP TRING RTIP RRING RXLOS RXLOS TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXSERCLK RXSER RXCASY TXCHN_ RTIP RXSER TXSER TXSY RXSER RXSER RXCHN_0 TXSY UC W V W U U U U T T T T T R R R P P P P R P P N N N N N M M M M M L L L L L K K K K K J J J J J J H H TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXSER TXCHN_ RXSERCLK TXCHN_ RXSERCLK RXSERCLK TXSY RXCHN_ TXCHN_0 TXMSY RXCRCSY XRT8L8 TXSER TXCHCLK TXSY TXSERCLK RXCHN_ TXSER TXSER TXCHN_ RXCHN_ RTIP TTIP RXCHN_ RXLOS RXLOS TXSERCLK TXCHCLK TXCHN_0 TXSER RXSERCLK TXOH TXOH TXOHCLK Figure 7 XRT8L8EVAL FPGA Channel Control (Schematic Page )

24 Page of TTIP RRING RRING RXSERCLK RXCHN_ RXSY RXOH TXSERCLK RTIP TXSY TXOH RXOHCLK TXSY RXSER RXCHN_0 C SPARTAN IIE RXCHN_ T SMD TTP RXCT TRP RTP RRP TTP RXCT TRP RTP RRP TTP RXCT TRP RTP RRP TTP RXCT TRP RTP RRP RRS RTS TRS TTS RRS RTS TRS TTS RRS RTS TRS TTS RRS RTS TRS TTS TRING0 TXCHN_ TXSER RXCHN_ TXSERCLK RXCHN_ RXSER TXSY TXCHN_ UD F F F F E E D D C D D B A A C B B A C B A E7 E8 D7 C7 B7 D8 C8 B8 A8 E9 F9 D9 C9 E0 B9 A9 F0 D0 C0 B0 A0 F B A E D B C A TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXCHN_ RXCHN_0 C0 TTIP C8 0.8uF RXLOS RXSY RXSERCLK RTIP TXMSY XCS00E FRAMER BLOCK[:] TXOHCLK TXCHN_ RTIP0 RTIP TTIP RXCRCSY TXSY RXSER H TXOHCLK TRING RXCHN_ RXCHCLK RXCHN_ C TRING J7 RJ RXCASY TXSER RXOH TXCHN_ TXSERCLK TXCHN_ TXSY RXCHCLK RXSER TXCHN_ C TXSER TXSERCLK TRING RRING0 TXOH TXSER TXCHN_0 RXCHN_ U7D J K J K K M M M L L K L F G F H D K J J H G G G H E E B D E E F C D F B C D E A C0 C A C C B A D9 E0 A K L K L J K H J H B0 TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TTIP TRING RTIP RRING TTIP TRING RTIP RRING RXLOS RXLOS J RJ TXSY RRING RXLOS TXSERCLK RXCASY RXCRCSY QUAD TRANSFORMER FOR CHANNELS [:0] RXSY RXSER TXCHCLK RXSER TXCHN_ RXSY TTIP0 TXCHN_0 XRT8L8 RXSY J RJ TXSER TXMSY TXCHCLK J8 RJ RXSERCLK RXSERCLK TXSERCLK RXCHN_ TXSER C9 0.8uF RXSERCLK RXSY RXSERCLK RXOHCLK Figure 8 XRT8L8EVAL FPGA Channel Control (Schematic Page )

25 Page of TXCHN_ RXSER RXSER RXLOS0 RXCHCLK TXSER TXSER0 TXSY TXSERCLK RXSY TXSER0 RXOHCLK0 RXCHN_ TXMSY RXCHN_ RXCASY TRING RXOH0 TXCHN0_0 TXCHN0_ RXCHN0_0 TXOH TXSY0 RXSERCLK TXOH0 TXMSY0 SPARTAN IIE TXCHCLK C 0.8uF TXOHCLK TXSERCLK TXSY RXSER0 TXSERCLK RXCHN_0 H TXCHN0_ RXSY0 C 0.8uF TXCHN_0 RXSERCLK0 RXSER TTIP0 RXSER0 RXSERCLK0 RXSY0 TXSERCLK0 RXCHN0_ TXCHN0_ RTIP0 RXSY TXSY RXCHN0_ RXOH RXCHCLK0 RXSERCLK0 TXCHN0_ TXSY0 TXSER RXCHN_ TXSER0 RXCRCSY XCS00E FRAMER BLOCK[:0] TTIP UE E A B C D A B C D E E7 E A7 B7 C7 A8 B8 A9 B9 C8 A0 B0 E9 E0 D D F9 F0 E F E G8 G9 G0 G F H8 H9 H0 H J7 J8 H J9 J0 J J K7 K8 K9 TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXOH0 TXOHCLK0 TXCHCLK0 TXSERCLK0 TXSER0 TXCHN0_ TXCHN0_ TXCHN0_ TXCHN0_ TXCHN0_0 TXSY0 TXMSY0 RXOH0 RXOHCLK0 RXCHCLK0 RXSERCLK0 RXSER0 RXCHN0_ RXCHN0_ RXCHN0_ RXCHN0_ RXCHN0_0 RXSY0 RXCRCSY0 RXCASY0 RRING RXCHN0_ RXCRCSY0 RXCASY0 RXCHN_ TXSERCLK0 RXCHN0_ TXSER TXSERCLK0 TXCHCLK0 TRING0 RRING0 TXCHN_ RXSERCLK TXSY0 RTIP RXLOS TXCHN_ RXSY0 TXOHCLK0 U7E A8 A9 E7 C9 D7 A A0 B9 D8 C8 C A7 B D A B B C7 B A E D D D E C E A A D C E A B D A9 B0 C B9 A8 A C7 A0 C0 C9 E9 D8 D9 B8 E0 G H F G F G D E A E8 TXOH TXOHCLK TXCHCLK TXSERCLK TXSER TXCHN_ TXCHN_ TXCHN_ TXCHN_ TXCHN_0 TXSY TXMSY RXOH RXOHCLK RXCHCLK RXSERCLK RXSER RXCHN_ RXCHN_ RXCHN_ RXCHN_ RXCHN_0 RXSY RXCRCSY RXCASY TXOH0 TXOHCLK0 TXCHCLK0 TXSERCLK0 TXSER0 TXCHN0_ TXCHN0_ TXCHN0_ TXCHN0_ TXCHN0_0 TXSY0 TXMSY0 RXOH0 RXOHCLK0 RXCHCLK0 RXSERCLK0 RXSER0 RXCHN0_ RXCHN0_ RXCHN0_ RXCHN0_ RXCHN0_0 RXSY0 RXCRCSY0 RXCASY0 TTIP TRING RTIP RRING TTIP0 TRING0 RTIP0 RRING0 RXLOS RXLOS0 RXSER0 RXSERCLK XRT8L8 RXOHCLK TXCHN_ RXSY Figure 9 XRT8L8EVAL FPGA Channel Control (Schematic Page )

26 Page of L C0 VCCV8 R0 0 UA XCS00E POWER E E8 F F7 G7 G8 G G H7 H R7 R T7 T8 T T U U7 V V8 F7 F8 G9 G0 F F G G G7 H7 J K N P R7 T7 T T U U T9 T0 U7 U8 N7 P7 R T G H J7 K7 A A B B C C0 G G J9 J0 J J J J K9 K0 K K K K L7 L9 L0 L L L L L M7 M9 M0 M M M M M N9 N0 N N N N P9 P0 P P P P T T Y Y0 AA AA AB AB C8 C 0uF FPGA BYPASS CAPACITORS A C C9 VCCV8 C8 C C C8 C0 C L V8 C8 C C C89 V8 C C7 R C TP T C9 C C97 J9 JUMPER R C8 00uF C 0uF C9 C9 C C C90 FPGA BYPASS CAPACITORS C7 C9 C7 0uF D.V C8 C8 C9 C88 0uF TP9 T C9 VCCV8 L C T C9 TP T U7A XRT8L8 Y AA AE AD AD9 AF AC AB9 AC AB AA V P L H C B D0 B7 C D0 C Y AD AC AD7 AC AF AE8 AB0 AD AC AA T N J F A E8 C E C8 A B A A F H J L N R T V D F H K M P T V D C B C E E B C H J K L M N R T E G J L N R U W D D A D A T T T T T T T T R R R R R R R R PLL PLL PLL PLL PLL PLL PLL PLL T T T T T T T T R R R R R R R R 8 VCCV8 C7 0uF C80 FRAMER BYPASS CAPACITORS C98 C8 C79 C9 C TP T C9 C C7 C87 0uF TP8 T L U8 REG0A VIN VOUT ADJ ENABLE C C7 T TP0 T C8 C8 0uF C7 C7 C7 C78 C0 L C 0uF C7 C A R 0 C77 C70 SPARTAN IIE Figure 0 XRT8L8EVAL Power Supply Design (Schematic Page 7)

27 Layout Recommendations RTIP/RRING Traces (Long Haul Applications) The most critical traces are those routed for the receiver inputs in Long Haul applications, where the input may be attenuated up to db of cable loss. The differential pair of each channel should be isolated from other signals on the PCB to prevent unwanted crosstalk or interference. TTIP and TRING transmit an output at full power (0 db) and should be routed with at least 0 mil spacing away from the receive signals. Center Tap Capacitor on the Transformer For best performance, it is recommended that the center tap of the receive transformer be bypassed to ground with a capacitor if a center tap is available. The capacitor will help filter out noise that otherwise could be AC coupled from the line interface through the transformer. T Transmit Analog Power Supply (.V ±%) T can be shared with D. However, it is recommended that T be isolated from the analog power supply R. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.µF capacitor. R Receive Analog Power Supply (.V ±%) For long haul applications, R should not be shared with other power supplies. It is recommended that R be isolated from the digital power supply D and the analog power supply T. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.µF capacitor. Note: In long haul applications where the receive inputs can be severely attenuated, it is critical to have a clean power supply design and clean PCB layout with respect to R. It is highly recommended that R be isolated from D and T. D Digital Power Supply (.V ±%) D should be isolated from the analog power supplies. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Every two D power supply pins should be bypassed to ground through at least one 0.µF capacitor. A Analog Power Supply (.V ±%) A should be isolated from the digital power supplies. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through at least one 0.µF capacitor. It s recommended that all ground pins of this device be tied together at one common ground point. Page 7 of 7