ZICM35xSPx Hardware Design Guidelines

Transcription

1 Application Note ZICM35xSPx Hardware Design Guidelines Document No: (Issue C) INTRODUCTION This Application Note provides module placement, schematic design examples and layout guidelines for the MeshConnect EM35x Mini Modules from California Eastern Laboratories (CEL). Two example designs are presented along with simple block diagrams and schematics demonstrating the ZICM35xSPx Module communicating via a Universal UART or SPI bus. Layout guidelines are also presented along with design guidelines checklists to aid developers wanting to quickly integrate the ZICM35xSPx family into their product designs. Date Published: March 17, 014 Page 1

2 TABLE OF CONTENTS Introduction... 1 Module Ground Planes and Keepouts... 3 Module Placement... 4 Antenna Checklist... 4 ZICM35xSPx Circuit Examples... 4 ZICM35xSPx UART Example... 5 ZICM35xSPx SPI Example... 6 Bill Of Material For UART and SPI Schematic Examples... 7 Layout Design Guidelines... 7 VCC and Trace Antenna... 8 Power Supply... 8 VCC Check List... 8 Grounding Pins And Planes... 9 Grounding Check List... 9 References Revision History Page

3 MODULE GROUND PLANES AND KEEPOUTS There are two recommended module placement options: 1. ZICM35xSPx antenna overhanging PCB (this option is preferred). ZICM35xSPx antenna with copper keepout along PCB edge The module placement options are shown in Figures 1 and. Refer to the MeshConnect EM35x Mini Modules Datasheet for keepout dimensions. Figure 1. Example ZICM35xSPx layout with antenna overhanging PCB Figure. Example ZICM35xSPx layout with copper keepout along PCB board edge Page 3

4 MODULE PLACEMENT Figure 3. Example ZICM35xSPx Module placements Figure 3 shows various allowed module placement options. In options 1, and 3, the antenna is overhanging the module and in options 4, 5 and 6, there is a copper keepout along the PCB edge under the antenna. Options 1-3 are preferred. If the product requirements do not allow for the module to overhang the PCB, options 4-6 can be used, with option 4 preferred. Note: The RF performance will be impacted slightly due to the presence of PCB material underneath the antenna. ANTENNA CHECKLIST If a system housing is required, an enclosure suitable for.4ghz RF should be used. Plastic is recommended with no metallic coatings. As with all RF circuitry, mounting the module in and around metals will have significant effect on the radiation pattern of the antenna and needs to be tested on a case-by-case basis. If a metal housing is required, using the integrated trace antenna is not recommended. Instead, use an external antenna. See CEL s Application Note "Mini Module Castellation Pin Layout Guidelines" for layout recommendations when using an external antenna. Ferrous materials should be placed as far from the antenna as possible. Any objects other than air near the antenna will have an impact on it. While it may seem obvious that the antenna will be affected by any metal objects near the antenna, it is also true that any objects which do not have the dielectric constant of air, such as a plastic case or a human hand, will also detune the antenna. A separation of 0.075" (1.905mm) or greater is recommended between the antenna and the housing in all directions. ZICM35xSPx CIRCUIT EXAMPLES The EM35x contains two Serial Controller (SC) interfaces: 1. SC1 (EM35x GPIOs PB1, PB, PB3 and PB4) can be used as a UART, SPI or TWI bus.. SC (EM35x GPIOs PA1, PA, PA3 and PA4) can be used as a SPI or TWI bus. Two circuit examples are shown below. The first shows SC1 as a UART with no connection on SC. The second shows SPI connections on SC1 and SC. Page 4

5 1 3 4 ZICM35xSPx Hardware Design Guidelines ZICM35xSPx UART Example Figure 4. ZICM35xSPx configured with UART block diagram Figure 4 shows an example block diagram with the ZICM35xSPx configured for UART communication. RTS/CTS hardware flow control uses two signals (nrts and ncts) in addition to received and transmitted data (RX and TX). Flow control is used by a data receiver to prevent buffer overflow by signaling an external device when it is and is not allowed to transmit. Hardware flow control is available in NCP mode only (see Silicon Labs EM35x documentation for more detail). ZICM35xSPx 33 GND 1 GND U1 GND 3 RF_OUT 31 GND NC 3 PC5 30 PB5 NRESET 4 NRESET 9 PB6 SW0 5 PC6 8 PB7 BUZZER 6 PC7 7 External RS-3 tranciever or UART NCTS 7 PA7 8 PB3 6 PC1 5 PB0 NRTS 9 PB4 4 NCP MODE WITH FLOW CONTROL 10 PA PA1 C1 10uF C 10pF PA4 PA5 LED0 1 GND 13 VCC 14 PA 15 PA3 16 PA4 17 PA5 18 PA6 19 PB1 0 PB 1 JTCK ISA3 CONNECTOR RECOMMENDED FOR SOFTWARE DEVELOPEMENT J JTCK 9 10 NRESET PA4 PA5 External RS-3 tranciever or UART TXD RXD SAMTEC_FTSH F-DV-K JTCK EXAMPLE SWITCH EXAMPLE LED 1K R5 R7 LED101 1 LED RED R LED0 SW0 33 SWITCH1 EXAMPLE BUZZER 5 BUZZER 1 BUZZER1 OPTIONAL EXAMPLE EXTERNAL CIRCUITS Figure 5. ZICM35xSPx configured with UART schematic example The schematic in Figure 5 shows the ZICM35xSPx configured as a UART without external flash memory. Page 5

6 1 3 4 ZICM35xSPx Hardware Design Guidelines ZICM35xSPx SPI Example ZICM35xSPx configured with SPI block diagram Figure 6. ZICM35xSPx configured with SPI block diagram Figure 6 shows an example block diagram with the ZICM35xSPx configured for SPI communications. External flash memory is connected to SC. ZICM35xSPx 33 GND 1 GND U GND 3 RF_OUT 31 GND NRESET NC 3 PC5 4 NRESET 5 PC6 6 PC7 7 PA7 8 PB3 9 PB4 10 PA0 30 PB5 9 PB6 8 PB7 7 6 PC1 5 PB0 4 3 SW0 BUZZER R9 10K 1 PA3 PA1 SERIAL FLASH 1 R11 10K U3 1 /CS VCC 8 DO /HOLD 7 3 /WP CLK 6 4 GND DI 5 W5Q80BVSNIG C4 10nF PA PA0 11 PA1 OPTIONAL SPI PB3 PB4 PB1 PB SERIAL FLASH PA0 PA1 PA PA3 C6 10uF 1 GND 13 VCC C7 10pF 14 PA 15 PA3 16 PA4 17 PA5 18 PA6 19 PB1 0 PB 1 JTCK ISA3 CONNECTOR RECOMMENDED FOR SOFTWARE DEVELOPEMENT J JTCK 9 10 NRESET PA4 PA5 SAMTEC_FTSH F-DV-K PA4 PA5 LED0 JTCK EXAMPLE SWITCH EXAMPLE LED 1K R5 R7 LED101 1 LED RED R LED0 SW0 33 SWITCH1 EXAMPLE BUZZER 5 BUZZER 1 BUZZER1 OPTIONAL EXAMPLE EXTERNAL CIRCUITS Figure 7. ZICM35xSPx configured with SPI schematic example Figure 7 shows an example of the ZICM357xSPx configured to communicate with SPI flash and an optional SPI port. Page 6

7 BILL OF MATERIAL FOR UART AND SPI SCHEMATIC EXAMPLES Quantity Reference Value Part Number Manufacturer Description Tolerance 1 C4 10nF GRM155R71E103KA01D MURATA CAP CER 10000PF 5V 10% X7R 040 ±10% R9 R11 10K RC040JR-0710KL YAGEO RES 10K OHM 1/16W 5% 040 SMD ±5% C1 C6 10uF GRM1BR61C106KE15L MURATA CAP CER 10UF 16V X5R 0805 ±10% C C7 10pF GRM1555C1H100JZ01D MURATA CAP CER 10PF 50V 5% C0G 040 ±5% 1 J CONN 10p FTSH F-DV-K SAMTEC HEADER CONNECTOR,PCB MNT,RECEPT,10 CONTACTS, PIN, PITCH U1 U MODULE ZICM35xSPx CEL ZICM357SPx-1 MODULE 1 U3 Flash Mem W5Q80BVSNIG Optional External Circuits Winbond Electronics IC SPI FLASH 8MBIT 8SOIC 1 BUZZER1 76dB CEP-1160 CUI BUZZER PIEZO 4KHZ 14MM EXT DRIVE 1 LED1 LED RED LNJ14R8RA PANASONIC LED RED USS TYPE R4 510 RC040JR-07510RL YAGEO RES 510 OHM 1/16W 5% 040 SMD 5% 1 R5 1K RC040FR-071KL YAGEO RES 1.00K OHM 1/16W 1% 040 SMD 1% 1 R7 33 RC040JR-0733RL YAGEO RES 33 OHM 1/16 W 5% 040 SMD 5% 1 SWITCH1 TACTILE SWITCH B3S-1100P OMRON MOMENTARY LIGHT TOUCH SMT SWITCH W/ ESD GND Table 1 shows an example Bill of Material required for the UART and SPI circuit examples along with their optional external circuits. LAYOUT DESIGN GUIDELINES Table 1. Bill of Material for UART and SPI Schematic Example Figure 8. Example top layer layout using the ZICM35xSPx Module Page 7

8 VCC AND TRACE ANTENNA Figure 9. Layout highlighting VCC trace thickness POWER SUPPLY CEL recommends a power supply design of 3.3V with a ripple of no more than +/- 0.3Vpp. Supply range is.1v to 3.6V. The supply for the ZICM35xSP0-1 Module should be capable of sourcing at least 50mA. The supply for the ZICM35xSP-1 Module should be capable of sourcing at least 00 ma. VCC CHECK LIST VCC trace should be thick, at least 0 mils to 40 mils. VCC bypass capacitor (typically 10uF CERAMIC 16V X5R 0805). Bypass capacitors are present within the ZICM35xSPx Module as well. We recommend a 10 pf RF bypass capacitor close to VCC. Page 8

9 GROUNDING PINS AND PLANES Figure 10. Layout highlighting ground pins GROUNDING CHECK LIST All ground pins should be connected to the ground plane. If thermals are used, we recommend combining webs no smaller than 0 mils. Thermal relief should be kept to a minimum on the RF pin and surrounding ground pins (pin 31, 3 and 33). The module relies on the ground plane of its host printed circuit board for proper performance. A flooded ground plane at least 1.5 X 1.5 is recommended for the top and bottom layers of the PCB. The 1.5 includes the flooded ground plane under the module and the surrounding ground plane (the total ground plane is larger than the module). This means a ground flood of 1.5 X 1.5 is recommended on layer 1 and 4 of a four layer board. We also recommend ground vias from top to bottom layers in a grid spaced every 00 mil or less. Page 9

10 REFERENCES Reference Documents Download California Eastern Laboratories EM357 Mini Module Datasheet Link Mini Module Castellation Pin Layout Guidelines For External Antenna Link Using an External Flash Memory with ZICM357SPx Mini Module Link Silicon Labs PCB Design with an Ember EM35x AN698 Link EM351/EM357 - High-Performance, Integrated ZigBee/ System-on-Chip Link REVISION HISTORY Previous Versions Changes to Current Version Page(s) (Issue A) July 15, (Issue B) August 15, (Issue C) March 17, 014 Initial Release Updated figures 5 and 7 for better viewing / printing 5, 6 Re-labeled LED circuits in figures 5 and 7 5, 6 N/A Page 10

11 Disclaimer The information in this document is current as of the published date. The information is subject to change without notice. For actual design-in, refer to the latest publications of CEL Data Sheets or Data Books, etc., for the most up-to-date specifications of CEL products. Not all products and/or types are available in every country. Please check with an CEL sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of CEL. CEL assumes no responsibility for any errors that may appear in this document. CEL does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of CEL products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of CEL or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer s equipment shall be done under the full responsibility of the customer. CEL assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While CEL endeavors to enhance the quality, reliability and safety of CEL products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in CEL products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. For More Information For more information about CEL MeshConnect products and solutions, visit our website at: Technical Assistance For Technical Assistance, visit Page 11