DS3/E3/STS-1 to Fiber Optic Reference Design using 78P2241B APPLICATION NOTE. Altera PLD. 75 Ohm Cable LOS RCLK RPOS LCV FIBER OUT FIDATA RX1

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1 DS/E/STS- to Fiber Optic Reference Design using PB APPLICATION NOTE SEPTEMBER 00 INTRODUCTION In typical DS/E/STS applications, signals are normally transported over ohm coax cable. The distance from the transmitter to the receiver is limited to about 000 feet to ensure interoperability between equipment. In applications where a longer reach is desired (for example inter-city where distances can run in the hundreds of miles), a Fiber Optics link can be designed. This application note explains a suggested design of a Fiber Optic extender that was tested in TDK laboratories using the PB, although the design could be applied to other TDK Px series LIUs as well. Contact your local TDK Semiconductor representative ( to obtain more detailed information on the design. SIGNALS DESCRIPTION The DS/E/STS- signal over coax cable is Alternative Mark Inversion (AMI). Use of zero limiting codes, such as Binary three Zero Substitution (BZS) for DS and STS- or High Density Binary three (HDB) for E, insure a minimum number of transitions in the data stream to keep the clock recovery phase locked loop in lock. BLOCK DIAGRAM DESCRIPTION Figure Shows a block diagram of the tested implementation. The Altera PLD contains the necessary circuit to adapt COAX signals to Fiber Optics signals. OTHER APPLICABLE DEVICES P P P Ohm Cable RX Altera PLD BITS SCSRAMBLER FIBER OUT Ohm Cable PB TRANSCEIVER TX TPOS TCLK BITS DESCSRAMBLER NRZ Data XVCO CLOCK RECOVERY HFBR-0x FIBER MODULE FIBER IN Figure. DS/E/STS- to fiber block diagram. - -

2 DS/E/STS- to Fiber Optic reference Design using PB COAX TO FIBER PATH:. DS/E/STS Signal is received by PB Transceiver. Clock is recovered () and NRZ signals and RNEG correspond to the received AMI signal from the coax.. The Altera PLD includes a bits scrambler that limits the number of zeros to 0.. The Altera PLD includes a seven bit counter to record errors.. Off the shelf Fiber Optics Module drives the Fiber Optics cable. FIBER TO COAX PATH:. Fiber module recovers and converts fiber optic signals to NRZ data.. Crystal VCO (XVCO) recovers clock and data from NRZ data. The Altera PLD includes a bit Descrambler.. The PB generates the appropriate DS/E/STS signals on the coax, which are compliant to the applicable standard. The PB implementation is the same as our regular coax demo board (see demo board manual for PB -pin TQFP) POWER SUPPLY CONNECTION The demo board is constructed as a four-layer PC board. The outer two planes carry the signals. The internal two layers are the ground and power supply planes. The power supply pins are connected directly to the supply planes (see Layout Files Figures: to ). BOARD LAYOUT CONSIDERATIONS When designing a system board for high-speed applications, there are several important factors to consider. This document contains a few recommendations that can help alleviate noise due to sub-optimal board layout around the LIU. A possible layout approach is to use a different ground at the BNC connectors for noise immunity. The BNC connectors should be connected to frame ground. The component ground should be a plane that connects directly to the negative supply pin. This ground plane will carry all the return currents of the LIU logic. The frame ground at the BNC connectors should be isolated from the other grounds if possible. The grounds should be isolated from each other by placing a strip of area, which is void of copper in the ground plane underneath the primary of the transformers. See Figure. FRAME GROUND TX- COAX RX-COAX COPPER VOID COMPONENT GROUND LIU Figure. Two different ground areas Some systems require a connection from the connector to the frame ground. In these cases, such as the coaxial cable being run near high disturbance sources and the far end being connected to a separate system with a separate ground reference, DC current and EMI generated AC currents may flow through the shield of the cable. The layout should provide placement for components that connect the cable shield to the frame ground. These components can be completely removed for full isolation or include either capacitors or zero ohm resistors for direct connection to frame ground. The designer can experiment to establish which option will satisfy his requirements best. A possible problem with using zero Ohm resistors is the DC path between the far end and the near end, which may connect the two building grounds together. The advantage of having the capacitors is to cut the DC path. On the other hand, we have introduced AC impedance between the two grounds, this means that the capacitor value will have to be chosen depending on the predominant interference frequency. When the cable shield is connected to the frame ground, the frame will need to be connected to an external ground source, such as a system chassis ground or earth ground, to dissipate the noise. For the positive supply we recommend a plane that connects all the supply pins of the LIU. This supply plane should be connected with the lowest possible impedance to the major supply. It is advisable to void the positive supply under the coaxial connectors and the primary side of the transformers to avoid noise being coupled in the supply. - -

3 DS/E/STS- to Fiber Optic reference design using PB The differential termination resistors for the line-side input and output signals should be placed as close as possible to the chip. Also, the traces for each of the line-side differential pairs should be run as parallel, straight, and as close as possible to avoid any reflection caused by a variance in trace lengths between a differential pair. The traces should be kept on the top layer of the board, and the width of the traces should be adjusted to meet the characteristic impedance of the line. The preferred differential termination scheme is shown in Figure. The value of each resistor should equal one half of the total termination used for the pair, so that each half of the signal is seeing the correct termination value. The capacitor value should be 0.uF. + of Diff Pair R=R=/ RLine - of Diff Pair R R Figure. Recommended termination of a differential pair Care should be taken when placing the RFO resistor. The RFO should be placed as close as possible to the chip and the trace to the resistor should remain on the top layer. Also, the LF capacitor should be placed close to the chip. To eliminate overshoot on the digital signals coming from the framer to the LIU, series resistors of 0 ohms should be added to the TCLK, TPOS and TNEG signals. Placing a ground trace on each side of TCLK and will also help to reduce noise on the board. For the LIU, decoupling capacitors should be implemented to help reduce noise. These are located directly underneath the LIU on the bottom side of the board. The and connections from the LIU should be made through via s, which are connected to the and of the decoupling capacitors. DESIGN DESCRIPTION, SIGNAL FLOW AMI Receiver The AMI coded data is received and decoded in the transceiver PB. Since the ENDEC function is enabled, the outputs of the transceiver are and. The receiver will also output two control signals and. (see Figure ) The N will indicate a loss of signal on the coaxial cable. (Line Code Violation) will indicate that an AMI code violation has occurred. Receive Signal Test points: SIGNAL N Gate Array Coax to Fiber. The gate array will scramble the data before sending it to the Fiber module. This is done to ensure there are enough transitions in the NRZ data so that the XVCO can retrieve the clock information out of the data stream. (see Figure ) The signal increments a seven bit counter, the contents of the counter are displayed on the seven red LED s. On power up all red LED s are turned off, if an error occurs, the red LED s display it, and the green LED turns off. The green led will go on during power on sequence or by pushing the RST button. The green LED will be turned off and all red LED s will turn on if the N signal is activated. (see Figure ) There are four LED s to indicate the status of operation. These LEDs are: OK, _COAX, _FIBER and _LOCK. OK will be turned on by activity on the signal. _COAX will turn on if the coax cable is removed. _FIBER will turn on if the fiber cable is removed. _LOCK will turn on if the XVCO loses lock. A jumper is provided to activate the internal loopback of the gate array. If pin and are connected then the signals and are connected to TPOS and TCLK respectively. Also the fiber receive signal is connected to the fiber transmit signal. Fiber Module The required bandwidth for the fiber module is low since the maximum frequency transferred is the STS- data rate which is. MHz. The demo board is equipped either with a OCP_ module or a HFBR 0 both will work over long distances of fiber cable (see Figure ). The interface for the transmit data is done via a single ended resistorbiased PECL translator. - -

4 DS/E/STS- to Fiber Optic reference design using PB From the fiber to the gate array the interface is PECL to TTL. The conversion is done by an off the shelf translator. In this case, the LT. XVCO The role of the XVCO is to extract the clock information from the data stream and reduce the jitter accumulated (see Figure ) Gate Array Fiber to Coax The gate array will descramble the data received from the Fiber module and convert it to NRZ data (TPOS). The gate Array is equipped with the Bit Blaster such that the customer can load his customized program. (see Figure ) Transmit Signals Test points: Rate settings. E the XVCO needs to be. MHz, the MODE jumper needs to be in E and R=.K. DS the XVCO needs to be. MHz, the MODE jumper needs to be in DS and R=.K. STS- the XVCO needs to be. MHz, the MODE jumper needs to be in STS- and R=.K. Latency DS is about 0ns from the coax connector to the fiber and vise versa. E is about ns from the coax connector to the fiber and vise versa. SIGNAL TCLK TPOS Coax_Int Control Fiber N TPOS N TPOS N TPOS RCCLK RCCLK RCCLK TCLK TCLK TCLK Fiber Coax_Int Control Reset Reset Figure Block Diagram. - -

5 DS/E/STS- to Fiber Optic reference design using PB - - PWR N TCLK LPBK E E-.k LBO R C 0.uF N OPTIONAL C 0.uF Tb TG-00N 0 C 0.uF C 0.uF C 0.uF C 0.0uF C 0.uF TPOS C 0.0uF TX C 0.0uF C0 0.uF NO.uF C TPOS DLB RX C 0.uF R 0 C 0.uF R DS-.K C0 0.uF C 0.uF U PB-IGT LIN+ LIN- RFO LOUT+ LOUT- ENDEC E TPOS/TNRZ TNEG TCLK TXEN LF RNEG /RNZR MON ICKP LBO LPBK OPTIONAL C 0.uF C 0.0uF R 0 C 0.uF D PWR C 0.uF FRAME_ ANA STS-.k C 0.uF C 0.uF STS R Ta TG-00N TCLK DS C 0.uF MODE R 0 Figure Coaxial Interface.

6 DS/E/STS- to Fiber Optic reference design using PB C0 C C C C C 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF R K R K R 0K R K C 0.UF C0 C C C C C.uF 0.uF 0.uF 0.0uF 0.0uF 0.uF OK _COAX _FIBER N TPOS JP TCLK R D R 0 R 0 D D 0 N TPOS TCLK OK OKL C CN F FN L LN U EPM0AE PDN CLRN EN TDI CLK LPBK LPBK TMS TDO TCK D D D D0 D D D D R0 0 RCCLK LPBK HBB MSB D R D R D R D0 R D R0 D R R D R LSB R K R K R K R K HEADER0 BLASTER 0 R K _LOCK R 0 D D Figure Control Circuitry. - -

7 DS/E/STS- to Fiber Optic reference design using PB - - C 0.uF C0 0.uF R 0K R 0 R 0 R 0 R R 0 U LT Vcc IN+ IN- D+ Vcc RCCLK C 0.uF RF 0K U DTR- RD+ RD- _Rx _Tx TD+ TD- _Tx _Rx C.uF R R C.uF C.uF R 0K RB E=0k/DS=k/STS=.k C 0.0uF R0. C.uF U TRU00 0 VC OPN OPOUT PHO DATAIN OUT CLKIN IN OP+ OE OUT R 0 C 0.uF C 0.uF L.uH R0 0 C 0.uF CF 00PF L.uH C 0.uF R R 0 C 0.0uF R R 0 U LT Vcc IN+ IN- D+ Vcc Figure Fiber Interface. R 0k R 0k UA AC00-0 RST R 0k C 0uF UD AC00-0 C uf UB AC00-0 UC AC Figure Led s reset circuitry.

8 DS/E/STS- to Fiber Optic reference design using PB Figure Layer Bottom Traces. Figure 0 Layer Top Traces. - -

9 DS/E/STS- to Fiber Optic reference design using PB Figure Layer Ground Planes. Figure Layer Positive Supply Plane. - -

10 DS/E/STS- to Fiber Optic reference design using PB Figure Top Silk Screen. Figure Bottom Silk Screen - 0 -

11 DS/E/STS- to Fiber Optic reference design using PB FTA-TOP Revision: Revised://00 Item QTY Reference Value Vendor Partnum PCB_Footprint PRECISION CF 00pF PANASONIC ECU-VHKBM 0 0% C,C,C,C,C,.uF PANASONIC ECS-TECR 0% C,C,C,C,C0,C,C, 0.uF TDK CXRE0M 0 0% C,C,C,C,C,C, C0,C,C,C,C0,C, C,C,C,C,C0,C, C,C,C,C,C,C,C0 C,C HIGH VOLTAGE C PANASONIC ECJ-VBH0K 0 0% C,C,C,C,C,C,C 0.0uF PANASONIC ECJ-VBH0K 0 0% C.0uF PANASONIC ECJ-VFHZ 0 % C 0uF TDK CBA0 0 0% C uf TDK C0XRIA0K 0 0% D PWR,D MSB,D LED GREEN Lumex Opto SSL-LXAGD-V Led smd 0 0 D LSB,D,D,D,D0,D,D LED RED Lumex Opto SSL-LXAID-V Led smd D,D,D L,L.uH PANASONIC ELJ-FDRKF 0 0% RB E=0k PANASONIC ERJ-ENF00V 0 % DS=K PANASONIC ERJ-ENF0V 0 % STS=.K PANASONIC ERJ-ENFV 0 % RF 0K PANASONIC ERJ-ENF0V 0 % RST PB C & K KTPCM MOM RX,TX BNC_RT OHM AMP/TYCO - BNC_RT R,R,R,R,R0,R, PANASONIC ERJ-ENF0V 0 % R,R,R R,R,R PANASONIC ERJ-ENFR0V 0 % R STS=.K PANASONIC ERJ-ENFV 0 % DS=.K PANASONIC ERJ-ENFV 0 % E=.K PANASONIC ERJ-ENFV 0 % R 0 PANASONIC ERJ-ENF00V 0 % 0 R,R,R0 0 PANASONIC ERJ-ENF00V 0 % R,R,R,R,R,R 0K PANASONIC ERJ-ENF00V 0 % R,R,R,R,R,R,R,R K PANASONIC ERJ-GEYJ0V 0 % R,R,R 0 PANASONIC ERJ-GEYJV 0 % R PANASONIC ERJ-GEYJ0V 0 % R,R,R PANASONIC ERJ-GEYJ0V 0 % R0,R 0 PANASONIC ERJ-GEYJ0V 0 % R,R,R,R 0 PANASONIC ERJ-ENF00V 0 % R0. PANASONIC ERJ-ENFRV 0 % R 0 PANASONIC ERJ-GEYJV 0 % 0 R 0 PANASONIC ERJ-GEYJV 0 % T :/:ct HALO TG-00N smt % U PTQFP TDK P-IGT TQFP U EPM0 ARROW EPM0AETC- TQFP U TRU00 VECTRON TRU0GKCGA DIP U HFBR 0 AGILENT HFBR 0 FIBER U,U LT Linear Tech LTCS SOIC U AC00-0 Fairchild AC00SC SOIC Table Bill Of Material No responsibility is assumed by TDK SEMICONDUCTOR CORPORATION for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, visit our web site or contact your local TDK Semiconductor representative. TDK Semiconductor Corp., Michelle Dr., Tustin, CA 0, TEL () 0-00, FAX () 0-, TDK Semiconductor Corporation 0/0/00 rev. - -