PCB REV DATE DATE SCH REV 01 JAN JAN 05 wsk START

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1 1 SCH REV PCB REV DATE BY DESCRIPTION PCB REV DATE BY JAN 0 START JAN 0 PCB Rev 1 done JAN 0 PCB Rev 1 done APR 0 01 FEB FEB 0 Sheet : Changed CPLD from XCXL to XC2XL; Sheet 8: Corrected data in/out connections between U & U2; Changed U from DIP to SOIC, type A to type B; Sheet : Changed U, U21, & U22 to 4LVX24 TSSOP; Sheet : Added R12 0k resistor across the crystal to assist oscillator startup; Voided ground and power planes under ethernet termination networks; Changed U to SOIC package; Added pin locator silk-screen ticks to fine-pitch devices; Changed U, U21, & U22 to 4LVX24 TSSOP; FEB Sheet : Changed R12 to 1M; Changed C80 to 4pF; FEB 20 Sheet : Added WAIT(L); Sheet : Added WAIT(L), SBX_RD(L) & SBX_WR(L); Sheet : Disconnected SBX_RD(L) and SBX_WR(L) from U; APR 02 Sheet 4: Changed C4 package size, changed C81, C82 value and package size; Sheet : Changed C1, C1, C1 value and package size; Sheet : Changed C18 value and package size; Sheet : Changed C8 package size; 01 APR 0 Sheet : Deleted P; Added C1, JP8, R1, U24 & U2; Removed & connection to Sheet ; Sheet : Deleted GND, TCK, TDI, TDO, TMS, TP, TP10, TP11, VCC; Sheet : Removed & ; Change U, U21, & U22 to 4LVC424A; Sheet : Renamed P2 & P to J & J; Renamed P to JP10; Sheet 10: Renamed P8 to J2; Sheet 11: Renamed S1 to SW2; Deleted C, JP, MCU_GND, MCU_TCK, MCU_TDI, MCU_TDO, MCU_TMS, MCU_TRST, RP, U; Added C2, R1, R18; APR 0 PCB Rev 2 done JUL 20 Sheet 2: Added notes and jumper descriptions; REVISIONS NOTES MCU: EXTERNAL BUS INTERFACE MCU: POWER MEMORY: SRAM MEMORY: FLASH CPLD GLUE LOGIC ETHERNET INTERFACE SBX INTERFACE 1-WIRE INTERFACE DIGITAL I/O & JTAG SERIAL I/O POWER, CLOCK, & RESET Systronix Inc Proprietary Information. This document contains financial, business, scientific, technical, economic or engineering information subject to USC , Protection of Trade Secrets. Disclosure to others, use, or copying, without the express written authorization of Systronix Inc is strictly prohibited. Violation may result in criminal prosecution under 18 USC or 18 USC 10. Copyright 1, Systronix Inc. Unpublished Work. All rights reserved. REVISIONS 1

2 2 JP1 JP2 JP JP4 JP JP JP8 JP! JP NO USER OPTION. SELECTS POWER SUPPLY FOR U2 & U UART 1 TxD TO RS-22 TRANSCEIVER U2 UART 1 TxD TO DALLAS 1-WIRE TRANSCEIVER U14 NO USER OPTION. ISOLATES THE REGULATOR UART 1 RxD FROM RS-22 TRANSCEIVER U2 UART 1 RxD FROM DALLAS 1-WIRE TRANSCEIVER U14 NO USER OPTION. ISOLATES THE REGULATOR JTAG PORT COMMUNICATES WITH CPLD U4 JTAG PORT COMMUNICATES WITH aj-100 CS0(L) CS1(L) INSTALLED SRAM_CE(L) FLASH_CE(L) NOT INSTALLED FLASH_CE(L) SRAM_CE(L) TO THE DS2480 VPP PIN; SEE NOTE 1 VPP (+12) FOR 1-WIRE EPROM PROGRAMING RETURN (GND) FOR EXTERNAL VPP SUPPLY SW2 TO IOA SW2 TO IOA4 SW2 TO IOA SW2 TO IOA 1 SHEET 12 SHEET 12 SHEET SHEET 12 SHEET SHEET 11 SHEET SHEET 10 SHEET 11! 1 JP PROVIDES AN ACCESS POINT FOR AN EXTERNAL PROGRAMMING VOLTAGE SUPPLY. IF EPROM PROGRAMMING IS NOT REQUIRED, A JUMPER MUST BE INSTALLED TO CONNECT TO THE DS2480 VPP PIN. VPP MUST BE APPLIED BEFORE. 2 MCS0(L) address range 0x0140_ x0140_FFFF MCS1(L) address range 0x0141_ x0141_FFFF NOTES 2

3 RP1 U1:A EBI (CTRL) WAIT(L) U24 FLASH_CE(L) D[1..0] U1:B EBI (ADDR) CS0(L) CS1(L) A2 A A4 A A A A8 A A10 A11 A12 A A14 A1 A1 A1 A18 A1 A20 A21 SWAP MEM R1 NCSB1PX C1 U2 NCSB1PX SRAM_CE(L) A[21..2] D[1..0] U1:C EBI (DATA) U1:E D0 D1 D2 D D4 D D D D8 D D10 D11 D12 D D14 D1 D1 D1 D18 D1 D20 D21 D22 D2 D24 D2 D2 D2 D28 D2 D0 D1 GPIO B R/W CS4(L) CS(L) MCU: EXTERNAL BUS INTERFACE

4 4 U1:K POWER C81 10uF.V C82 10uF.V C8 C4 10uF.V C C40 C41 C42 C C C4 C C R U8 MIC24-2.BM C4 C 100pF C 100pF C8 100pF MCU POWER 4

5 U1 U1 A2 A A4 BA2 BA BA4 A1 A14 A BA1 BA14 BA A BA A12 BA12 A A BA BA A1 A1 BA1 BA1 8 A8 A BA8 BA A18 A1 BA18 BA1 A10 A11 BA10 BA11 A20 A21 BA20 BA21 A[21..2] D[1..0] SRAM_CE(L) C4 4ALVCH124_TSS A2 A A4 A A A A8 A A10 A11 A12 A A14 A1 A1 A1 A18 A1 U C4 C28 D0 D1 D2 D D4 D D D D8 D D10 D11 D12 D D14 D1 C44 C1 10uF.V C1 10uF.V C48 A2 A A4 A A A A8 A A10 A11 A12 A A14 A1 A1 A1 A18 A1 4ALVCH124_TSS U12 C2 C4 C4 D1 D1 D18 D1 D20 D21 D22 D2 D24 D2 D2 D2 D28 D2 D0 D1 C1 10uF.V MEMORY: SRAM ASC408-10TC ASC408-10TC

6 U1 U18 BA2 BA BA4 BA BA BA BA8 BA BA10 BA11 BA12 BA BA14 BA1 BA1 BA1 BA18 BA1 BA20 BA21 BD0 BD1 BD2 BD BD4 BD BD BD BD8 BD BD10 BD11 BD12 BD BD14 BD1 BA2 BA BA4 BA BA BA BA8 BA BA10 BA11 BA12 BA BA14 BA1 BA1 BA1 BA18 BA1 BA20 BA21 BD1 BD1 BD18 BD1 BD20 BD21 BD22 BD2 BD24 BD2 BD2 BD2 BD28 BD2 BD0 BD1 AM2LV10D-0EC C2 C18 10uF.V AM2LV10D-0EC C2 FLASH_CE(L) D[1..0] U1 U20 BD[1..0] 8 BD_BUS_RD(H) BD_BUS_EN(L) D8 D D10 D11 D12 D D14 D1 BD8 BD BD10 BD11 BD12 BD BD14 BD1 D24 D2 D2 D2 D28 D2 D0 D1 BD24 BD2 BD2 BD2 BD28 BD2 BD0 BD1 BD[1..0] D0 D1 D2 D D4 D D D BD0 BD1 BD2 BD BD4 BD BD BD D1 D1 D18 D1 D20 D21 D22 D2 BD1 BD1 BD18 BD1 BD20 BD21 BD22 BD2 C0 4ALVCH124_TSS C1 C2 4ALVCH124_TSS C MEMORY: FLASH

7 R/W FLASH_CE(L) CS4(L) CS(L) WAIT(L) ETH_MEMR(L) ETH_MEMW(L) ETH_IOR(L) ETH_IOW(L) NOT NORMALLY STUFFED R/W CLKO FLASH_CE(L) CS4(L) CS(L) A1 A1 A18 A1 A20 A21 ETH_MEMR(L) ETH_MEMW(L) ETH_IOR(L) ETH_IOW(L) ETH_A0 MCS0(L) MCS1(L) SBX_BUS_EN(L) SBX_BUS_RD(H) BRK(L) BD_BUS_RD(H) BD_BUS_EN(L) ETH_A0 SBX_RD(L) SBX_WR(L) MCS0(L) MCS1(L) SBX_BUS_EN(L) SBX_BUS_RD(H) TDI CPLD_TMS(H) TCK 11 C8 10uF.V C84 C8 BRK(L) TDO 11 BD_BUS_RD(H) BD_BUS_EN(L) CLKO CPLD GLUE LOGIC

8 8 U2 J1 X1 20MHz R ETH_MEMR(L) ETH_MEMW(L) ETH_IOR(L) ETH_IOW(L) ETH_A0 8R 1% R 100 1% R8 8R 1% C 0pF RJ-1 RJ-2 RJ- RJ- BA2 BA BA4 BA BA BA BA8 BA BA10 BA11 BA12 BA C C8 RJ24 ETH_IRQ(H) U R10 11 BD0 BD1 BD2 BD BD4 BD BD BD BD8 BD BD10 BD11 BD12 BD BD14 BD1 C2 LC4B SOIC C C4 C8 C BD[1..0] R11 4.k 1% C C0 C1 CS800A-CQ ETHERNET 8

9 U21 DIG. I/O & JTAG SBX_INT0(H) SBX_INT1(H) SBX_IRQ0(H) SBX_IRQ1(H) 11 GLUE NOT NORMALLY STUFFED TP2 TP1 SBX_-12 SBX_+12 J SBX_WR(L) SBX_RD(L) U C C 4LVC424A C1 4.uF SBX_A2 MCS1(L) MCS0(L) SBX_BUS_EN(L) SBX_BUS_RD(H) MEMORY: SRAM BA4 BA BA2 4LVC424A C8 SBX_ SBX_A2 SBX_A1 SBX_A0 SBX_MCS1(L) SBX_MCS0(L) C SBX_INT1(H) SBX_INT0(H) SBX_ SBX_WR(L) SBX_RD(L) MCS1(L) IS NOT USED BY MOST SBX CARDS SO IT CAN BE A USER DECODE SBX_WR(L) SBX_RD(L) SBX_MCS1(L) SBX_MCS0(L) SBX_A1 SBX_A0 SBX_D SBX_D SBX_D SBX_D4 SBX_D SBX_D2 1-WIRE SBX_D1 SBX_D0 10 OWIO MEMORY: FLASH U22 BD[1..0] BD0 BD1 BD2 BD BD4 BD BD BD SBX_D0 SBX_D1 SBX_D2 SBX_D SBX_D4 SBX_D SBX_D SBX_D 4LVC424A C0 C1 SBX INTERFACE bab/

10 10 SERIAL I/O SERIAL I/O 12 1-WIRE_TXD 1-WIRE_RXD 12 C! SEE NOTE 1 U14 JP SBX 10 OWIO DS2480 DS2480B D D CMPSH- CMPSH- J2 RJ11-/ DOW NET CONNECTOR VRAW 1-WIRE INTERFACE 10

11 11 U1:F ETHERNET R14 U1:D GPIO C P GPIO A ETH_IRQ(H) 8 SBX SW2 JP10 U1:H GPIO E HEADER8X1 P SBX_IRQ0(H) SBX_IRQ1(H) LED1 RED BR1111C R 0 U1:I JTAG IF HEADER8X1 P1 MCU_TMS(H) TCK TMS TDI JP R1 1k C2 IDC10M TDO GLUE TCK CPLD_TMS(H) GLUE TDI TDO BRK(L) BRK(L) R18 1k DIGITAL I/O & JTAG 11

12 12 1-WIRE 1-WIRE_TXD 10 1-WIRE 1-WIRE_RXD RTSB TXDB RXDB CTSB U2 C P RTS> TxD> DTR> <DCD <DSR <RxD <CTS <RI GND HDR 2X 2MM SHR DTEDCE CTS> RxD> DSR> DCD> <DTR <TxD <RTS GND 10 U1:G _OR_ C C C _OR_ GPIO D C8 SOUT SIN CTSB RTSB TXDA RXDA CTSA RTSA RTSA TXDA RXDA CTSA SP211CA U C P4 RTS> TxD> DTR> <DCD <DSR <RxD <CTS <RI GND HDR 2X 2MM SHR DTEDCE CTS> RxD> DSR> DCD> <DTR <TxD <RTS GND _OR_ C14 C10 C11 _OR_ C12 SP211CA _OR_ SERIAL I/O 12

13 RP2 GLUE U R U1:J CLK & RESET CLKO PB KT11 SW1 DS184A ETHERNET C2 LED2 RED BR1111C R1 0 18pF C80 4pF R12 1M X2 10MHz SBX 8 U11 D8! P2 MOLEX 2 TO 24 V INPUT LTCS8 U10 C1.nF R 4.k 1% R1 1.82k 1% D C2 CMSH2-40 CMPSH- L2 2.uH 1A D2 C0.V 1A MAX JP 100uF V C PASTE P1 OTHER SHEETS OTHER SHEETS P DJ-00-B VRAW C20 80uF C2 D SMBJ24M 00W LTCS8 C2.nF R4 4.k 1% R2.k 1% D4 C21 CMSH2-40 CMPSH- L1 2.uH 1A C22 V 1A MAX JP 100uF V C24 PASTE P1 P1 P POWER, CLOCK, & RESET

A50/A51/A60. June 2008 (4th Edition) All Rights Reserved

A50/A51/A60. June 2008 (4th Edition) All Rights Reserved A50/A51/A60 June 2008 (4th Edition) All Rights Reserved Part I - A50/A51 RS-232 to RS-422/RS-485 Converter A50/A51 RS-232 to RS-422/RS-485 Bidirectional Converter Part II - A60 RS-232 Surge Protection