QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339 LOW NOISE, 500KSPS, 12-BIT ADC

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1 LTC0 DESCRIPTION Demonstration circuit features the LTC0 low noise, 00ksps, -Bit, ADC. The LTC0 has an SPI compatible serial interface that can be used to select channel polarity and unipolar or bipolar settings. DCA demonstrates the DC and AC performance of the LTC0 in conjunction with the DC0B QuikEval and DC0B Fast DAACS data collection boards. Use DC0B to demonstrate DC performance such as peak-to-peak noise and DC linearity. Use DC0B if precise sampling rates are required or to demonstrate AC performance such as SNR, THD, SINAD and SFDR. Alternatively, by connecting the DCA into a customer application, the performance of the LTC0 can be evaluated directly in that circuit. Design files for this circuit board are available. Call the LTC factory. LTC is a trademark of Linear Technology Corporation Figure. DCA Connection Diagram

2 DC0B QUICK START PROCEDURE Connect DCA to a DC0B USB High Speed Data Collection Board using connector J. Connect DC0B to a host PC with a standard USB A/B cable. Apply V-V DC to the V-V and terminals. Apply a low jitter signal source to IN+ on connector J. Apply a low jitter clock with a maximum frequency of 0MHz to connector J. The clock can be a sine wave or square wave with maximum amplitude of dbm. Note that J PSCOPE SOFTWARE CONFIGURATION The Pscope software will recognize DCA and configure itself automatically. The default configuration is for IN+ with respect to IN- in unipolar mode. Make sure that the jumpers are set as shown in Figure. If bipolar mode is desired, it will be necessary to change the Pscope ADC configuration setting as well as jumpers JP and JP. From the front page of the software select ADC Configuration from the Configure menu. Select -Bits, Alignment, FPGA Ld Serial 0 Class, - Channel. Do not check Positive Edge Clk. has a 0Ω termination resistor to ground, which will prevent most logic from driving this pin directly. Run the Fast DAACS software (Pscope.exe version K or later) supplied with DC0B or download it from Complete software documentation is available from the Help menu. Updates can be downloaded from the Tools menu. Check for updates periodically as new features may be added. Check Bipolar if the JP UNI jumper is set to. An example of the ADC configuration menu is shown in Figure. JP should be changed from to VREF/ in bipolar mode, so that the minus input is biased halfway between ground and Vref. Click the Collect button (See Figure ) to begin acquiring data. Depending on which board was previously used by Pscope it may be necessary to press Collect a second time. The Collect button then changes to Pause, which can be used to pause data acquisition. Figure. Jumper Settings Figure. User Configure Menu

3 DC0B QUICK START PROCEDURE Connect DCA to a DC0 USB serial controller using the supplied -conductor ribbon cable. Connect DC0 to a host PC with a standard USB A/B cable. Run the evaluation software supplied with DC0 or download it from The correct control panel will be loaded automatically. HARDWARE SET UP Version K of QuikEval or higher should be used for this board. Click the COLLECT button to begin reading the ADC. Change the range (unipolar or bipolar) by right clicking over the range indicator in the display. See Figure. SIGNAL CONNECTIONS J SMA connector for IN+. Limit input swings to 0V-.0V. For optimum performance, the input should be band limited to the frequencies of interest. See schematic for details. J FastDAACS interface to DC0B. Do not use J at the same time. J Conversion Clock Input. This input has a 0Ω termination resistor, and is intended to be driven by a dbm sine or square wave. To achieve full AC performance of this part, the clock jitter should be kept under 0ps. This input is capacitively coupled to a clock buffer so that level shifting is not required. To run at maximum conversion rate, apply a 0MHz signal to this connector. J is used only for DC0B. DC0B generates its own clock signal. J Quick Eval interface to DC0B. Do not use J at the same time. This connector can also be used to drive the ADC directly. See schematic for details. JUMPERS JP (OVDD) connects the OVDD pin of the ADC to V or to an external voltage. The SDO pin swings from ground to OVDD. JP contains CONV, SDI, SCK and a buffered SDO signal. This connector is intended to monitor these signals. For for those who want to drive the ADC directly use J. JP (IN-) selects whether the IN- pin of the ADC is to be cleanly grounded near the ADC or connected to VREF/. JP (VREF) selects onboard or external reference for the ADC JP (DIN Word) selects the channel configuration and unipolar/bipolar settings of the ADC. (JP is used by the DC0B only. It is ignored by the DC0B.) GROUNDING AND POWER CONNECTION Connect a V to V power supply to the - VDC and posts when using DC0B. If the DC0B is used it will provide power to the DC.

4 Figure. DCA Pscope Screenshot

5 Figure. DCA QuikEval Screen Shot

6 C uf C 0.uF R.0K % V E0 R. % (Opt) V E V U LT0ACS-.0 VOUT VIN DNC DNC C 0.uF U SNAHCTG0DCKT C 0.uF CONV_AT_ADC E.V C uf J IN+ 0V -.0V C uf V E VREF R 0 C 0uF.V MUX EXPOSED CONVST SDO SCK SDI VREF OVDD VDD PAD IN+ IN- LTC0CDD U 0 U LTES-. IN ADJ OUT.V V JP EXT OVDD V E IN+ V JP EXT REF VREF.0V R 00 C uf 0V E VREF/ R.K % C uf V E EXT REF U NCSVU0PX SDO_AT_0 JP DO CLK CNV DI E OVDD E V - V E IN- R 00 C 0.0uF SCK_AT_ADC C 0uF C 0uF.V V U LTES- IN ADJ OUT SDI_AT_ADC C pf SDO_AT_BUF C 0.uF JP IN- VREF/ C 0.0uF C0 0.uF C pf.v C 0.uF R 0 % C 0uF.V R.K %

7 V C 0.uF # R. % + - U LTCS + - U LTCS R0.K % V R.K % + - U LTCS R K R.K % V R J EDGE-CON E SCK C 0.uF U NCSVU0PX OE A B U NCSZPX CONV_AT_ADC C 0.uF C 0.uF R.K % SDI_AT_ADC.V C 0.uF R E CNVCLK R.K %.V E MISO R0 MISO E CNVST CONV_AT_ADC C 0.uF UNI V E LATCH V C 0.uF E CONV VCC_IN R K C0 0.uF C 0.uF # E MOSI CLK_IN OS R.K.V SDO_AT_0 Array EEPROM U LC0-I /ST SDA VCC A0 A A VSS WP SCL V C 0.uF J -0 Molex 0 MOSI/SDA EESDA VUNREG V CS SCK/SCL EEVCC MISO EESCL EE NC SDI_AT_ADC R C 0.uF.V C 0.uF U NCSZ0PX_NL C0 0.uF.V V SDO_AT_0 JP 0 0 V SCK_AT_ADC SCK_AT_ADC.V LATCH U NCSZ0PX_NL R.K % R.00K % V J CONV R U0 NLSZUSG D CP Q Q VCC PR CLR V V MOSI U NCSZ0PX_NL C.uF V.V CNVST C 0.uF SDO_AT_BUF.V