PARAMETER CONDITION VALUE Depending on Sampling Rate and the A/D Converter Provided, this Supply Must Provide Up to 500mA.

Transcription

1 DESCRIPTION LTC0, LTC06, LTC0, LTC0, LTC0, LTC0, LTC0 6-Bit/-Bit 0Msps to 0Msps ADCs Demonstration circuit 99A supports members of a family of 6-bit/-bit 0Msps to 0Msps ADCs. Each assembly features one of the following devices: LTC 0, LTC06, LTC0, LTC0, LTC0, LTC0, or LTC0 high speed, high dynamic range ADCs. Other members of this family include the LTC08/ LTC08-6-bit/-bit 0Msps ADC with LVDS outputs. These 9mm 9mm QFN devices are supported by Demonstration circuit 8 (CMOS outputs) or by Demonstration circuit 996 (LVDS outputs). Several versions of the 99A demo board supporting a single-ended clock input, specifically targeted for use with the Msps LTC0, 0Msps LTC0 and 0Msps LTC0 A/D converters, are listed in Table. LTC0, LTC0, LTC06 and LTC0 have differential clock inputs but use a single-ended clock input for evaluation with the DC input on the DC99A board. Depending on the required sample rate and input frequency, the DC99A is supplied with the appropriate ADC and with an optimized input circuit. The circuitry on the analog inputs is optimized for analog input frequencies from DC to 0MHz or from MHz to 0MHz if using the transformer coupled input. For higher input frequencies, contact the factory for support. Design files for this circuit board are available at L, LT, LTC, LTM, μmodule, Linear Technology and the Linear logo are registered trademarks and QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Table. DC99A Variants DC99 VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY 99A-A LTC0 6-Bit 0Msps DC - 0MHz 99A-B LTC06 6-Bit 80Msps DC - 0MHz 99A-C LTC0 6-Bit 6Msps DC - 0MHz 99A-D LTC0 6-Bit 0Msps DC -0MHz 99A-E LTC0 6-Bit Msps DC - 0MHz 99A-F LTC0 6-Bit 0Msps DC - 0MHz 99A-G LTC0- -Bit 0Msps DC -0MHz 99A-H LTC06- -Bit 80Msps DC - 0MHz 99A-I LTC0- -Bit 6Msps DC - 0MHz 99A-J LTC0 6-Bit 0Msps DC - 0MHz PERFORMANCE SUMMARY (T A = C) PARAMETER CONDITION VALUE Supply Voltage Depending on Sampling Rate and the A/D Converter Provided, this Supply Must Provide Up to 00mA. Optimized for.v [.V.V Min/Max] Analog Input Range Depending on PGA Pin Voltage.V P-P to.v P-P Logic Input Voltages Minimum Logic High.V Maximum Logic Low 0.8V Logic Output Voltage Minimum Logic High at.6ma (VCX Output Buffer, V CC =.V) Maximum Logic Low at.6ma Sampling Frequency (Convert Clock Frequency) See Table.V (Ω Series Terminations) 0.V (Ω Series Terminations)

2 PERFORMANCE SUMMARY (T A = C) Convert Clock Level 0Ω Source Impedance, AC-Coupled or Ground Referenced (Convert Clock Input Is Capacitor Coupled on Board and Terminated with 0Ω.) Resolution See Table Input Frequency Range See Table SFDR See Applicable Data Sheet SNR See Applicable Data Sheet V P-P.V P-P Sine Wave or Square Wave QUICK START PROCEDURE Demonstration circuit 99A is easy to set up to evaluate the performance of the LTC0, LTC06, LTC0, LTC0, LTC0, or LTC0 A/D converters. Refer to Figure for proper measurement equipment setup and follow this procedure: Setup If a DC8 QuikEval II Data Analysis and Collection System was supplied with the DC99A demonstration circuit, follow the DC8 Quick Start Guide to install the required software and for connecting the DC8 to the DC99A to a PC. DC99A Demonstration Circuit Board Jumpers The DC99A demonstration circuit board should have the following jumper settings as default: (as per Figure ) JP: Output clock polarity: JP: SENSE:, (Internal reference) JP: PGA:.V range JP: RAND: Not randomized JP: SHDN: Not shutdown JP6: DITH: No internal dithering Applying Power and Signals to the DC99A Demonstration Circuit If a DC8 is used to acquire data from the DC99A, the DC8 must FIRST be connected to a powered USB port or provided an external 6V to 9V BEFORE applying.v across the pins marked +.V and PWR on the DC99A. The DC99A demonstration circuit requires up to 00mA depending on the sampling rate and the A/D converter supplied. The DC8 data collection board is powered by the USB cable and does not require an external power supply unless it must be connected to the PC through an unpowered hub in which case it must be supplied an external 6V to 9V on turrets G(+) and G( ) or the adjacent.mm power jack. Encode Clock NOTE: This is a logic compatible input, contrary to the majority of Linear Technology ADC demo boards. It is not terminated with 0Ω. Apply an encode clock to the SMA connector on the DC99A demonstration circuit board marked J ENCODE INPUT. For the best noise performance, the ENCODE INPUT must be driven with a very low jitter source. A low jitter.v oscillator with direct connection through a barrel is recommended. If using a sinusoidal generator, the amplitude should be as large as possible, up to V P-P or dbm, filtered and terminated with a 0Ω thru-terminator. If a generator with 0Ω output impedance is connected via a cable, it is recommended that a thru-terminator be used. However, below MHz, it is recommended that a square wave drive be used. If a sinusoidal ground referenced signal, or an AC-coupled signal is used,.v to.v DC bias must be introduced via a bias tee. DC99A has provision for a popular surface mount oscillator form and some population options to select this as the clock source. (Please see schematic.) If only sinusoidal or clipped sinusoid signal sources are available as the clock source for scenarios involving sampling rates less than Msps to 0Msps, it is recommended

3 QUICK START PROCEDURE Figure. DC99A Setup that a divide by or divide by 8 be used. If the converter is to be used at very low sampling rates approaching the minimum, a higher divide ratio may be required. This is especially important if undersampling. If you want to use these converters at less than the minimum sampling rate, it is recommended that you run the ADC above the minimum rate, and decimate. If oversampling low frequencies, the use of a sinusoid is potentially acceptable, but it must be very clean or the low dv/dt will result in a great sensitivity to wideband noise in the clock driver. The use of a divider may require a bandpass filter prior to the divider in order to achieve best SNR as the divider can exaggerate phase noise if it is sensitive to GHz frequencies. Contact Linear Technology for recommendations or in some cases, available clock sources or dividers. Most generators require filtering or they will compromise both the SNR and the SFDR of the ADCs. Generally data sheet FFT plots are taken with 0 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non-harmonically related spurs and broad band noise. Low phase noise Agilent 86B generators are used with TTE band pass filters for both the Clock input and the Analog input. In the case of the LTC0/LTC0/LTC0 we use a divide by. This demo board is, populated by default for the DC input path. There is a transformer mounted at T, but C, C6, R9 and R are not populated. If a single-ended AC input is required, the DC input paths must be disconnected by removing R6,, and, and the above components installed.

4 QUICK START PROCEDURE If the transformer input is required, C and C6 should be 0.μF XR 00, R9 and R should be 0Ω 00 resistors. Note that this transformer (ETC-T) is poor below MHz. Reduced amplitude signals can be applied to 00kHz. Applications below 00kHz must be driven directly via DC inputs. As there are a significant number of these boards that are customized, please confirm the population of your board. The schematic below shows the default population, the photograph shows the population of a transformer coupled version. This board may also be populated with LTC0-0 for DC drive applications, in which case, R is a 0.μF capacitor. Apply the analog input signal of interest to the SMA connector on the DC99A demonstration circuit board marked J ANALOG INPUT. These inputs are capacitive coupled to a Flux coupled transformers ETC-T. In some cases, where these devices are to be used in undersampling scenarios, this transformer should be replaced with an ETC-- Balun. The DC99A can be modified for direct DC drive from a suitable differential signal source. This may be done by yourself or at special request when you order the demo board. If the DC input paths are populated with low value (.Ω) resistors at both ends of these transmission lines, you must provide a reasonably well balanced differential drive with.v common mode. The spacing of these SMA connectors (0.8") allows them to be mated directly with demo boards for devices such as the LT99, LT99, LT and others. It is not recommended to drive this ADC in a single-ended fashion into a single DC input. An internally generated conversion clock output is available on pin of J and the data samples are available on Pins to of J which can be collected via a logic analyzer, cabled to a development system through a SHORT to inch long 0-pin ribbon cable or collected by the DC8 QuikEval II Data Acquisition Board using the PScope System Software provided or down loaded from the Linear Technology website at If a DC8 was provided, follow the DC8 Quick Start Guide and the instructions below. If data is to be collected by a logic analyzer, pin 0 must be strapped to O or.v. (Please see schematic.) To start the data collection software if PScope.exe is installed (by default) in \Program Files\LTC\PScope\, double click the PScope Icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. If the DC99A demonstration circuit is properly connected to the DC8, PScope should automatically detect the DC99A, and configure itself accordingly. If necessary, the procedure below explains how to manually configure PScope. Under the configure menu, go to ADC Configuration. Check the Config Manually box and use the following configuration options: User configure 6-Bit (or -Bit if using - versions) Alignment: Left-6 Bipolar ( s complement) Positive clock edge Type: CMOS If everything is hooked up properly, powered and a suitable convert clock is present, clicking the Collect button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC8 Quick Start Guide and in the online help available within the PScope program itself. Analog Input Network For optimal distortion and noise performance the RC network on the analog inputs should be optimized for different analog input frequencies. At this point in time, the circuit in Figure for input frequencies below 0MHz. For input frequencies from 0MHz to 0MHz, the circuit in Figure is used. These two input networks cover a

5 QUICK START PROCEDURE broad bandwidth and are not optimized for operation at a specific input frequency. In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. Narrow band high-q filters may produce poor SNR results with Dither enabled. 0% bandpass would be preferred over % bandpass on the analog input. The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 0Ω outside the passband. In cases with long transmission lines, db to 0dB pads may be required to obtain low distortion. If your generator cannot deliver full-scale signals without distortion, you may benefit from a medium power amplifier based on a Gallium Arsenide Gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be unable to deliver the combination of low noise figure and High IP point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit. For advice on drive circuits or for input frequencies greater than 0MHz contact the factory for support. For input frequencies less than MHz, or greater than 0MHz, other input networks may be more appropriate. Please consult the factory for suggestions on drivers and networks if your signal sources extend outside these ranges, or if you experience difficulties driving these suggested networks. 0Ω V CM.μF ANALOG INPUT 0.μF 0.μF T : Ω Ω 0Ω 0.μF 0Ω Ω + A IN.pF Ω A IN LTC0/ LTC0 T = MA/COM ETC--. RESISTORS, CAPACITORS ARE 00 PACKAGE SIZE, EXCEPT.μF dc99a F0 Figure. Analog Front End Circuit For 0MHz+ 0Ω V CM ANALOG INPUT 0.μF T : Ω 0Ω 0.μF.μF Ω + A IN 8.pF LTC0/ LTC0 Ω 0Ω Ω A IN T = COILCRAFT WBCI-IT OR MA/COM ETC-T RESISTORS, CAPACITORS ARE 00 PACKAGE SIZE EXCEPT.μF dc99a F0 Figure. Analog Front End Circuit for MHz < A IN < 0MHz

6 PARTS LIST ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER Required Circuit Components C, C, C, C, C6 CAP., XR, 0.μF, V, 0% 060 TDK, C608XRE0K 0 C, C6 (OPEN) CAP., 060 C8, C CAP., XR,.μF, 6.V, 0% 060 TDK, C608XR0JK C, C, C CAP., C0G, 8.pF, 0V, % 00 AVX, 00A8RJAT C9, C-C9, C8 CAP., XR, 0.μF, 0V, 0% 00 TDK, C00XRA0K 6 C0 CAP., XR, 0μF, 6.V, 0% 080 TDK, C0XR0J06K C CAP., XR, 0.0μF, 0V, 0% 060 TDK, C608XRH0K 8 C CAP., XR,.0μF, 6V, 0% 060 TDK, C608XRC0K 9 C CAP., XR,.μF, 0V, 0% 080 TDK, C0XRAK 0 0 C (OPT) CAP., 00μF, 6.V 60 E, E, E TESTPOINT, TURRET, 0.06" MILL-MAX, JP-JP SINGLE ROW HEADER, -PIN SAMTEC, TMM0-0-L-S 6 JP-JP6 SHUNT SAMTEC, SN-BK-G J CON, HDR, CNTRS, 0-PIN SAMTEC, TSW-0-0-L-D J, J, J CON., SMA 0Ω EDGE-LANCH CONNEX, 6 0 OSC (OPT) RN, RN, RN, RN RES ARRAY, Ω, %, 00 VISHAY, CRA0S0800JRT 8 R, R, R0, R RES., CHIP, 0k, /6W, % 00 AAC, CR0-0JM 9 R, R RES., CHIP, k, /6W, % 060 AAC, CR6-0JM 0 0 R, R6, R9, R-R, R, R0 (OPEN) RES., CHIP, 060 R6, R RES., CHIP, 0Ω, /6W, % 060 AAC, CR6-00JM R, R8 RES., CHIP, Ω, /6W, % 00 VISHAY, CRCW000JRT6 R8 RES., CHIP, Ω, /6W, % 00 AAC, CR0-0JM R9 RES., CHIP, k, /6W, % 00 AAC, CR0-0JM R0, R RES., CHIP,.Ω, /6W, % 00 AAC, CR0-RJM 6 R, R RES., CHIP, 0Ω, /6W, 00 AAC, CJ0-000M 8 R, R RES., CHIP,.9Ω, /6W, % 060 VISHAY, CRCW060R9FRT6 9 R, R8, R9 RES., CHIP, 0k, /6W, % 060 AAC, CR6-0JM 0 R RES., CHIP, 0k, /6W, % 060 AAC, CR6-0FM R RES., CHIP, 00k, /6W, % 060 AAC, CR6-0JM R RES., CHIP, Ω, /8W, % 080 AAC, CR0-R0JM T TRANSFORMER, :, ETC-T M/A-COM, ETC-T U, U I.C., VCXBQX, DQFN0 FAIRCHILD, VCXBQX U, U I.C., NCSV86 SC0- FAIRCHILD, NCSV86PX 6 U6 I.C., LC0, TSSOP-8 MICROCHIP, LC0 I /ST U I.C., LT6, SO8 LINEAR TECH., LT6CS8 8 (STAND-OFF) STAND-OFF, NYLON 0." tall KEYSTONE, 88(SNAP ON) 6

7 SCHEMATIC DIAGRAM O ANALOG INPUT DCIN+ VERSION TABLE Assembly Type DC99A-A SHDN DITH INPUT FREQUENCY DC < Ain < 0MHz +.V * U LTC0CUK DC99A-B LTC06CUK DC99A-C LTC0CUK DC99A-D LTC0CUK DC99A-E LTC0CUK DC99A-F LTC0CUK DC99A-G LTC0CUK- DC99A-H LTC06CUK- DC99A-I LTC0CUK- DC99A-J LTC0CUK U NCSV86PX JP R SENSE R R OPEN 0K 0K C 0.uF JP JP PGA RAND U 0 VCC R6 R A B B6 A6 8 R8 B A B A 6 B A R9 R0 6 B A B A. 8 R C B0 A0 8.pF 9 T/R C OE 8.pF 0 R Sense O 6 C VCXBQX R R Vcm D 8.pF C8 D0..uF U D9 0 U * D8 VCC ENCODE Ain+ O INPUT B A 9 Ain- CLKOUT+ 0 J 9 B6 A6 8 R8 CLKOUT- R B A /ENC+ D 8 0 B A * 6 /ENC- EXPOSED PAD D6 B A D 6 6 R0 B A O B A R9 OSC 8 B0 A0 K Fo 9 T/R EN OE 0 opt. R 0.0uF Bits 6 Msps 0 0.0uF DC < Ain < 0MHz uF DC < Ain < 0MHz uF DC < Ain < 0MHz OHM DC < Ain < 0MHz 6 0 OHM DC < Ain < 0MHz uF DC < Ain < 0MHz 0 0.0uF DC < Ain < 0MHz uF DC < Ain < 0MHz 6 0 OHM DC < Ain < 0MHz 6 0 CONTRACT NO. APPROVALS DATE DRAWN June Wu //0 TITLE CHECKED APPROVED ENGINEER D. Redmayne //0 DESIGNER SIZE Tuesday, April, 0 SCALE: RNA RNB RNC RND RNA RNB RNC RND RNA RNB RNC RND RNA RNB RNC RND 60 McCarthy Blvd. Milpitas, CA 90 Phone: (08)-900 Fax: (08)-00 TECHNOLOGY LTC0 FAMILY 6 BIT HIGH SPEED ADC CAGE CODE DWG NO REV DC99A A FILENAME: SHEET OF 0 R6 C0 0uF 6.V C6 0.uF J U6 LC0 A0 A VCC 8 A A SDA SCL WP 6 + C 00uF 6.V opt. E C 0.0uF U LT6 OUT ADJ BYP IN 8 6 SHDN R8 0K C 0.uF R R JP R 0K C9 0.uF C.uF R 0K R J R S-0G R K C9 0.uF E E R 00K R9 0K T ETC-T SHDN DITH D0 D D D D O O 8 PGA RAND 6 MODE OE OF D D D 0 D 9 O 8 O C.0uF C 0.uF R K VCXBQX C8 C C6 C 0.uF 0.uF 0.uF 0.uF C 0.uF U NCSV86PX JP J R0 0K C8 0.uF JP6 R 0K C.uF R C C6 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

8 DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 0 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the construction of the product, it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 60 McCarthy Blvd. Milpitas, CA 90 Copyright 00, Linear Technology Corporation 8 LT 0 PRINTED IN USA Linear Technology Corporation 60 McCarthy Blvd., Milpitas, CA 90- (08) -900 FAX: (08) LINEAR TECHNOLOGY CORPORATION 0