LTC Bit, 20Msps Low Noise ADC FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION

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1 6-Bit, 2Msps Low Noise ADC FEATURES n 84.dB SNR (46μV RMS Input Referred Noise) n 99dB SFDR n ±2.3LSB INL(Maximum) n Low Power: 88mW n Single.8V Supply n CMOS, DDR CMOS, or DDR LVDS Outputs n Selectable Input Ranges: V P-P to 2.V P-P n 2MHz Full Power Bandwidth S/H n Shutdown and Nap Modes n Serial SPI Port for Configuration n Pin Compatible with LTC26:6-Bit, 25Msps, 45mW n 48-Lead (7mm 7mm) QFN Package APPLICATIONS n Low Power Instrumentation n Software Defined Radios n Portable Medical Imaging n Multichannel Data Acquisition DESCRIPTION The LTC 2269 is a sampling 6-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 84.dB SNR and 99dB spurious free dynamic range (SFDR). DC specs include ±LSB INL (typ), ±.2LSB DNL (typ) and no missing codes over temperature. The transition noise is.44lsb RMS. The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from.2v to.8v. The ENC + and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION.8V.8V V DD OV DD 2..5 Integral Non-Linearity (INL) ANALOG INPUT 2MHz CLOCK S/H 6-BIT ADC CORE CLOCK CONTROL OUTPUT DRIVERS D5 D CMOS DDR CMOS OR DDR LVDS OUTPUTS INL ERROR (LSB) TA GND OGND OUTPUT CODE 2269 TA2

2 ABSOLUTE MAXIMUM RATINGS Supply Voltages (V DD, O VDD )....3V to 2V Analog Input Voltage (A IN +, A IN, PAR/SER, SENSE) (Note 3)....3V to (V DD +.2V) Digital Input Voltage (ENC +, ENC, CS, SDI, SCK) (Note 4)....3V to 3.9V SDO (Note 4)....3V to 3.9V (Notes, 2) Digital Output Voltage....3V to (OV DD +.3V) Operating Temperature Range C... C to 7 C I... 4 C to 85 C Storage Temperature Range C to 5 C PIN CONFIGURATION FULL RATE CMOS OUTPUT MODE DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW TOP VIEW 48 V DD 47 V DD 46 SENSE 45 VREF 44 SDO 43 GND 42 OF 4 DNC 4 D5 39 D4 38 D3 37 D2 V CM A IN + 2 A IN 3 GND 4 REFH 5 REFL 6 REFH 7 REFL 8 PAR/SER 9 GND GND V DD 2 49 GND 36 D 35 D 34 D9 33 D8 32 OV DD 3 OGND 3 CLKOUT + 29 CLKOUT 28 D7 27 D6 26 D5 25 D4 V CM A IN + 2 A IN 3 GND 4 REFH 5 REFL 6 REFH 7 REFL 8 PAR/SER 9 GND GND V DD 2 49 GND 36 D_ 35 DNC 34 D8_9 33 DNC 32 OV DD 3 OGND 3 CLKOUT + 29 CLKOUT 28 D6_7 27 DNC 26 D4_5 25 DNC VDD 3 GND 4 ENC + 5 ENC 6 CS 7 SCK 8 SDI 9 GND 2 D 2 D 22 D2 23 D3 24 VDD 3 GND 4 ENC + 5 ENC 6 CS 7 SCK 8 SDI 9 GND 2 DNC 2 D_ 22 DNC 23 D2_ V DD 47 V DD 46 SENSE 45 VREF 44 SDO 43 GND 42 OF 4 DNC 4 D4_5 39 DNC 38 D2_3 37 DNC UK PACKAGE 48-LEAD (7mm 7mm) PLASTIC QFN T JMAX = 5 C, θ JA = 29 C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB UK PACKAGE 48-LEAD (7mm 7mm) PLASTIC QFN T JMAX = 5 C, θ JA = 29 C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB 2

3 PIN CONFIGURATION DOUBLE DATA RATE LVDS OUTPUT MODE TOP VIEW V CM A IN + 2 A IN 3 GND 4 REFH 5 REFL 6 REFH 7 REFL 8 PAR/SER 9 GND GND V DD 2 49 GND 36 D_ + 35 D_ 34 D8_ D8_9 32 OV DD 3 OGND 3 CLKOUT + 29 CLKOUT 28 D6_ D6_7 26 D4_ D4_5 V DD 3 GND 4 ENC + 5 ENC 6 CS 7 SCK 8 SDI 9 GND 2 D_ 2 D_ + 22 D2_3 23 D2_ V DD 47 V DD 46 SENSE 45 VREF 44 SDO 43 GND 42 OF + 4 OF 4 D4_ D4_5 38 D2_ D2_3 UK PACKAGE 48-LEAD (7mm 7mm) PLASTIC QFN T JMAX = 5 C, θ JA = 29 C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE CUK#PBF CUK#TRPBF UK 48-Lead (7mm 7mm) Plastic QFN C to 7 C IUK#PBF IUK#TRPBF UK 48-Lead (7mm 7mm) Plastic QFN 4 C to 85 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: 3

4 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 6 Bits Integral Linearity Error Differential Analog Input (Note 6) l 2.3 ± 2.3 LSB Differential Linearity Error Differential Analog Input l.8 ±.2.8 LSB Offset Error (Note 7) l 7 ±.3 7 mv Gain Error Internal Reference External Reference l.5 ±.2.2. Offset Drift ± μv/ C Full-Scale Drift Internal Reference External Reference ±3 ± ppm/ C ppm/ C Transition Noise External Reference.44 LSB RMS %FS %FS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (A IN + A IN ).7V < V DD <.9V l to 2. V P-P V IN(CM) Analog Input Common Mode (A IN + + A IN )/2 Differential Analog Input (Note 8) l.65 V CM V CM + 2mV V V SENSE External Voltage Reference Applied to SENSE External Reference Mode l V I INCM Analog Input Common Mode Current Per Pin, 2Msps 32 μa I IN Analog Input Leakage Current (No Encode) < A IN +, A IN < V DD l μa I IN2 PAR/SER Input Leakage Current < PAR/SER < V DD l μa I IN3 SENSE Input Leakage Current.625 < SENSE <.3V l 2 2 μa t AP Sample-and-Hold Acquisition Delay Time ns t JITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode Differential Encode CMRR Analog Input Common Mode Rejection Ratio 8 db BW-3B Full Power Bandwidth Figure 5 Test Circuit 2 MHz 85 fs RMS fs RMS DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. A IN =. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio.4MHz Input 5MHz Input 3MHz Input 7MHz Input SFDR Spurious Free Dynamic Range 2nd Harmonic.4MHz Input 5MHz Input 3MHz Input 7MHz Input l 82. l

5 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. A IN =. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SFDR SFDR Spurious Free Dynamic Range 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher.4MHz Input 5MHz Input 3MHz Input 7MHz Input.4MHz Input 5MHz Input 3MHz Input 7MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio.4MHz Input 5MHz Input 3MHz Input 7MHz Input l 92 l 95 l INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS V CM Output Voltage I OUT = l.5 V DD 25mV.5 V DD.5 V DD + 25mV V V CM Output Temperature Drift ±25 ppm/ C V CM Output Resistance 6μA < I OUT < ma 4 Ω V REF Output Voltage I OUT = l V V REF Output Temperature Drift ±25 ppm/ C V REF Output Resistance 4μA < I OUT < ma 7 Ω V REF Line Regulation.7V < V DD <.9V.6 mv/v DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC +, ENC ) DIFFERENTIAL ENCODE MODE (ENC NOT TIED TO GND) V ID Differential Input Voltage (Note 8) l.2 V V ICM Common Mode Input Voltage Internally Set.2 V Externally Set (Note 8) l..6 V V IN Input Voltage Range ENC +, ENC to GND l V R IN Input Resistance (See Figure ) kω C IN Input Capacitance (Note 8) 3.5 pf SINGLE-ENDED ENCODE MODE (ENC TIED TO GND) V IH High Level Input Voltage V DD =.8V l.2 V V IL Low Level Input Voltage V DD =.8V l.6 V V IN Input Voltage Range ENC + to GND l 3.6 V R IN Input Resistance (See Figure ) 3 kω C IN Input Capacitance (Note 8) 3.5 pf 5

6 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) V IH High Level Input Voltage V DD =.8V l.3 V V IL Low Level Input Voltage V DD =.8V l.6 V I IN Input Current V IN = V to 3.6V l μa C IN Input Capacitance (Note 8) 3 pf SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) R OL Logic Low Output Resistance to GND V DD =.8V, SDO = V 2 Ω I OH Logic High Output Leakage Current SDO = V to 3.6V l μa C OUT Output Capacitance (Note 8) 3 pf DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OV DD =.8V V OH High Level Output Voltage I O = 5μA l V V OL Low Level Output Voltage I O = 5μA l..5 V OV DD =.5V V OH High Level Output Voltage I O = 5μA.488 V V OL Low Level Output Voltage I O = 5μA. V OV DD =.2V V OH High Level Output Voltage I O = 5μA.85 V V OL Low Level Output Voltage I O = 5μA. V DIGITAL DATA OUTPUTS (LVDS MODE) V OD Differential Output Voltage Ω Differential Load, 3.5mA Mode Ω Differential Load,.75mA Mode V OS Common Mode Output Voltage Ω Differential Load, 3.5mA Mode Ω Differential Load,.75mA Mode l l mv mv.375 V V R TERM On-Chip Termination Resistance Termination Enabled, OV DD =.8V Ω POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate V DD Analog Supply Voltage (Note ) l V OV DD Output Supply Voltage (Note ) l..8.9 V I VDD Analog Supply Current DC Input Sine Wave Input l ma ma I OVDD Digital Supply Current Sine Wave Input, OV DD =.2V ma P DISS Power Dissipation DC Input Sine Wave Input, OV DD =.2V LVDS Output Mode l mw mw V DD Analog Supply Voltage (Note ) l V OV DD Output Supply Voltage (Note ) l V 6

7 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I VDD Analog Supply Current Sine Wave Input,.75mA Mode Sine Wave Input, 3.5mA Mode I OVDD Digital Supply Current (OV DD =.8V) Sine Wave Input,.75mA Mode Sine Wave Input, 3.5mA Mode P DISS Power Dissipation Sine Wave Input,.75mA Mode Sine Wave Input, 3.5mA Mode All Output Modes l l l P SLEEP Sleep Mode Power.5 mw P NAP Nap Mode Power mw P DIFFCLK Power Increase with Differential Encode Mode Enabled (No Increase for Nap or Sleep Modes) 2 mw ma ma ma ma mw mw TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f S Sampling Frequency (Note ) l 2 MHz t L ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On t H ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On t AP Sample-and-Hold Acquisition Delay Time l l l l ns ns ns ns ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) t D ENC to Data Delay C L = 5pF (Note 8) l ns t C ENC to CLKOUT Delay C L = 5pF (Note 8) l ns t SKEW DATA to CLKOUT Skew t D t C (Note 8) l.3.6 ns Pipeline Latency Full Data Rate Mode Double Data Rate Mode Cycles Cycles DIGITAL DATA OUTPUTS (LVDS MODE) t D ENC to Data Delay C L = 5pF (Note 8) l ns t C ENC to CLKOUT Delay C L = 5pF (Note 8) l ns t SKEW DATA to CLKOUT Skew t D t C (Note 8) l.3.6 ns Pipeline Latency Cycles SPI PORT TIMING (Note 8) t SCK SCK Period Write Mode Readback Mode, C SDO = 2pF, R PULLUP = 2k t S CS to SCK Setup Time l 5 ns t H SCK to CS Setup Time l 5 ns t DS SDI Setup Time l 5 ns t DH SDI Hold Time l 5 ns t DO SCK Falling to SDO Valid Readback Mode, C SDO = 2pF, R PULLUP = 2k l 25 ns l l 4 25 ns ns 7

8 ELECTRICAL CHARACTERISTICS Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than ma below GND or above V DD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than ma below GND without latchup. Note 5: V DD = OV DD =.8V, f SAMPLE = 2MHz LVDS outputs, differential ENC + /ENC = 2V P-P sine wave, input range = 2.V P-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from.5 LSB when the output code flickers between and in 2 s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: V DD =.8V, f SAMPLE = 2MHz CMOS outputs, ENC + = single-ended.8v square wave, ENC = V, input range = 2.V P-P with differential drive, 5pF load on each digital output unless otherwise noted. Note : Recommended operating conditions. TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels t AP ANALOG INPUT ENC N t H t L N + N + 2 N + 4 N + 3 ENC + t D D D5, OF N 6 N 5 N 4 N 3 N 2 CLKOUT + t C CLKOUT 2269 TD 8

9 TIMING DIAGRAMS Double Data Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels t AP ANALOG INPUT ENC N t H t L N + N + 2 N + 4 N + 3 ENC + t D t D D_ D4_5 D N-6 D N-6 D N-5 D N-5 D N-4 D N-4 D N-3 D N-3 D4 N-6 D5 N-6 D4 N-5 D5 N-5 D4 N-4 D5 N-4 D4 N-3 D5 N-3 OF OF N-6 OF N-5 OF N-4 OF N-3 CLKOUT + t C t C CLKOUT 2269 TD2 Double Data Rate LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels t AP ANALOG INPUT ENC N t H t L N + N + 2 N + 4 N + 3 ENC + D_ + D_ D4_5 + D4_5 OF + OF CLKOUT + t D t D D N-6 D N-6 D N-5 D N-5 D N-4 D N-4 D N-3 D N-3 D4 N-6 D5 N-6 D4 N-5 D5 N-5 D4 N-4 D5 N-4 D4 N-3 D5 N-3 OF N-6 OF N-5 OF N-4 OF N-3 t C t C CLKOUT 2269 TD3 9

10 TIMING DIAGRAMS SPI Port Timing (Readback Mode) t S t DS t DH t SCK t H CS SCK t DO SDI R/W A6 A5 A4 A3 A2 A A XX XX XX XX XX XX XX XX SDO HIGH IMPEDANCE D7 D6 D5 D4 D3 D2 D D CS SPI Port Timing (Write Mode) SCK SDI R/W A6 A5 A4 A3 A2 A A D7 D6 D5 D4 D3 D2 D D SDO HIGH IMPEDANCE 2269 TD4

11 TYPICAL PERFORMANCE CHARACTERISTICS INL ERROR (LSB) Integral Non-Linearity (INL) OUTPUT CODE 2269 G DNL ERROR (LSB) Differential Non-Linearity (DNL) OUTPUT CODE 2269 G2 AMPLITUDE () k Point FFT, f IN =.4MHz,, 2Msps FREQUENCY (MHz) 2269 G3 AMPLITUDE () k Point FFT, f IN = 5.MHz,, 2Msps FREQUENCY (MHz) 2269 G4 AMPLITUDE () k Point FFT, f IN = MHz,, 2Msps FREQUENCY (MHz) 2269 G5 AMPLITUDE () k Point FFT, f IN = 3.3MHz,, 2Msps FREQUENCY (MHz) 2269 G6 AMPLITUDE () k Point FFT, f IN = 7.3MHz,, 2Msps AMPLITUDE () k Point 2-Tone FFT, f IN = 4.8, 5.2MHz, 7, 2Msps COUNT Shorted Input Histogram FREQUENCY (MHz) 2269 G FREQUENCY (MHz) 2269 G8 N-6 N-5 N-4 N-3 N-2 N- N N+ N+2 N+3 N+4 N+5 N+6 OUTPUT CODE 2269 G9

12 TYPICAL PERFORMANCE CHARACTERISTICS 85 SNR vs Input Frequency,, 2Msps, 2.V Range 5 2nd, 3rd Harmonic vs Input Frequency,, 2Msps, 2.V Range 5 2nd, 3rd Harmonic vs Input Frequency,, 2Msps,.5V Range SNR () DIFFERENTIAL ENCODE SINGLE-ENDED ENCODE 2ND AND 3RD HARMONIC () ND 3RD 2ND AND 3RD HARMONIC () ND 3RD INPUT FREQUENCY (MHz) 2269 G INPUT FREQUENCY (MHz) 2269 G INPUT FREQUENCY (MHz) 2269 G2 3 2 SFDR vs Input Level, f IN = 5MHz, 2Msps 55 I VDD vs Sample Rate, 5MHz, Sine Wave Input 4 I OVDD vs Sample Rate, 5MHz, Sine Wave Input 3.5mA LVDS SFDR (dbc AND ) dbc I VDD (ma) mA LVDS OUTPUTS CMOS OUTPUTS IOVDD (ma) mA LVDS INPUT LEVEL () 2269 G SAMPLE RATE (Msps) 2269 G4.8V CMOS SAMPLE RATE (Msps) 2269 G SNR vs SENSE, f IN = 5MHz, SFDR vs Analog Input Common Mode, f IN = 9.7MHz, 2Msps, 2.V Range V DD.9V SNR, SFDR vs Sample Rate, f IN = 5MHz, SNR () SFDR () V DD.7V SNR, SFDR () 9 SFDR SNR SENSE PIN (V) 2269 G INPUT COMMON MODE (V) 2269 G SAMPLE RATE (Msps) 2269 G8 2

13 PIN FUNCTIONS (Pins that are the Same for All Digital Output Modes) V CM (Pin ): Common Mode Bias Output. Nominally equal to V DD /2. V CM should be used to bias the common mode of the analog inputs. Bypass to ground with a μf ceramic capacitor. A + IN (Pin 2): Positive Differential Analog Input. A IN (Pin 3): Negative Differential Analog Input. GND (Pins 4,,, 4, 2, 43, Exposed Pad Pin 49): ADC Power Ground. The exposed pad must be soldered to the PCB ground. REFH (Pins 5, 7): ADC High Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. REFL (Pins 6, 8): ADC Low Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. PAR/SER (Pin 9): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to V DD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or V DD and not be driven by a logic signal. V DD (Pins 2, 3, 47, 48): Analog Power Supply,.7V to.9v. Bypass to ground with.μf ceramic capacitors. Adjacent pins can share a bypass capacitor. ENC + (Pin 5): Encode Input. Conversion starts on the rising edge. ENC (Pin 6): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 7): Serial Interface Chip Select Input. In serial programming mode (PAR/SER = V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = V DD ), CS controls the clock duty cycle stabilizer (see Table 2). CS can be driven with.8v to 3.3V logic. SCK (Pin 8): Serial Interface Clock Input. In serial programming mode, (PAR/SER = V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = V DD ), SCK controls the digital output mode (see Table 2). SCK can be driven with.8v to 3.3V logic. SDI (Pin 9): Serial Interface Data Input. In serial programming mode, (PAR/SER = V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = V DD ), SDI can be used together with SDO to power down the part (Table 2). SDI can be driven with.8v to 3.3V logic. OGND (Pin 3): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OV DD (Pin 32): Output Driver Supply. Bypass to ground with a.μf ceramic capacitor. SDO (Pin 44): Serial Interface Data Output. In serial programming mode, (PAR/SER = V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to.8v 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = V DD ), SDO can be used together with SDI to power down the part (Table 2). When used as an input, SDO can be driven with.8v to 3.3V logic through a k series resistor. V REF (Pin 45): Reference Voltage Output. Bypass to ground with a 2.2μF ceramic capacitor. The output voltage is nominally.25v. SENSE (Pin 46): Reference Programming Pin. Connecting SENSE to V DD selects the internal reference and a ±.5V input range. Connecting SENSE to ground selects the internal reference and a ±.525V input range. An external reference between.625v and.3v applied to SENSE selects an input range of ±.84 V SENSE. 3

14 PIN FUNCTIONS FULL RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to O VDD ) D to D5 (Pins 2-28, 33-4): Digital Outputs. D5 is the MSB. CLKOUT (Pin 29): Inverted version of CLKOUT +. CLKOUT + (Pin 3): Data Output Clock. The digital outputs normally transition at the same time as the falling edge of CLKOUT +. The phase of CLKOUT + can also be delayed relative to the digital outputs by programming the mode control registers. DNC (Pin 4): Do not connect this pin. OF (Pin 42): Overflow/Underflow Digital Output. OF is high when an overflow or underflow has occurred. DOUBLE DATA RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to O VDD ) D_ to D4_5 (Pins 22, 24, 26, 28, 34, 36, 38, 4): Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D, D2, D4, D6, D8, D, D2, D4) appear when CLKOUT + is low. The odd data bits (D, D3, D5, D7, D9, D, D3, D5) appear when CLKOUT + is high. DNC (Pins 2, 23, 25, 27, 33, 35, 37, 39, 4): Do not connect these pins. CLKOUT (Pin 29): Inverted version of CLKOUT +. CLKOUT + (Pin 3): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT +. The phase of CLKOUT + can also be delayed relative to the digital outputs by programming the mode control registers. OF (Pin 42): Overflow/Underflow Digital Output. OF is high when an overflow or underflow has occurred. DOUBLE DATA RATE LVDS OUTPUT MODE All Pins Below Have LVDS Output Levels. The Output Current Level is Programmable. There is an Optional Internal Ω Termination Resistor Between the Pins of Each LVDS Output Pair. D_ /D_ + to D4_5 /D4_5 + (Pins 2/22, 23/24, 25/26, 27/28, 33/34, 35/36, 37/38, 39/4): Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D, D2, D4, D6, D8, D, D2, D4) appear when CLKOUT + is low. The odd data bits (D, D3, D5, D7, D9, D, D3, D5) appear when CLKOUT + is high. CLKOUT /CLKOUT + (Pins 39/4): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT +. The phase of CLKOUT + can also be delayed relative to the digital outputs by programming the mode control registers. OF /OF + (Pins 4/42): Overflow/Underflow Digital Output. OF + is high when an overflow or underflow has occurred. 4

15 FUNCTIONAL BLOCK DIAGRAM V DD OVDD ANALOG INPUT V REF 2.2μF S/H.25V REFERENCE 6-BIT ADC CORE CORRECTION LOGIC OUTPUT DRIVERS OF D5 D CLKOUT + CLKOUT RANGE SELECT SENSE REF BUF REFH REFL INTERNAL CLOCK SIGNALS OGND V CM μf V DD /2 DIFF REF AMP CLOCK/DUTY CYCLE CONTROL MODE CONTROL REGISTERS GND REFH 2.2μF REFL ENC + ENC PAR/SER CS SCK SDI SDO 2269 BD μf μf Figure. Functional Block Diagram 5

16 APPLICATIONS INFORMATION CONVERTER OPERATION The is a low power, 6-bit, 2Msps A/D converter that is powered by a single.8v supply. The analog inputs must be driven differentially. The encode input can be driven differentially or single-ended for lower power consumption. The digital outputs can be CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system). Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the V CM output pin, which is nominally V DD /2. For the 2.V input range, the inputs should swing from V CM 525mV to V CM + 525mV. There should be 8 phase difference between the inputs. A IN + A IN Ω Ω V DD V DD V DD C PARASITIC.8pF C PARASITIC.8pF R ON 24Ω R ON 24Ω C SAMPLE 7pF C SAMPLE 7pF INPUT DRIVE CIRCUITS Input filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application s input frequency. Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with V CM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 through 5) has better balance, resulting in lower A/D distortion. Amplifier Circuits Figure 6 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC coupled to the A/D so the amplifier s output common mode voltage can be optimally set to minimize distortion. If DC coupling is necessary use a differential amplifier with an output common mode set by the V CM pin (Figure 7). 5Ω V CM μf ENC +.2V k ANALOG INPUT.μF T : 25Ω 25Ω.μF A IN + 2pF ENC 25Ω 25Ω A IN k.2v T: MA/COM MABAES6 RESISTORS, CAPACITORS ARE 42 PACKAGE SIZE 2269 F3 Figure 2. Equivalent Input Circuit 2269 F2 Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from MHz to 4MHz 6

17 APPLICATIONS INFORMATION 5Ω V CM μf ANALOG INPUT.μF T T2 25Ω 2Ω.μF A IN +.μf 25Ω 2Ω 8.2pF A IN 2269 F4 T: MA/COM MABA-759- T2: COILCRAFT WBC-TL RESISTORS, CAPACITORS ARE 42 PACKAGE SIZE Figure 4. Recommended Front End Circuit for Input Frequencies from 5MHz to 8MHz 5Ω V CM μf ANALOG INPUT.μF T T2 25Ω.μF A IN +.μf 25Ω.8pF A IN 2269 F5 T: MA/COM MABA-759- T2: COILCRAFT WBC-TL RESISTORS, CAPACITORS ARE 42 PACKAGE SIZE Figure 5. Recommended Front End Circuit for Input Frequencies Above 8MHz V CM V CM HIGH SPEED DIFFERENTIAL.μF AMPLIFIER 2Ω 2Ω 25Ω μf A + IN μf 25Ω + A IN ANALOG INPUT +.μf 25Ω 2pF A IN ANALOG INPUT + CM 25Ω 25pF A IN 2pF 2269 F6 25pF 2269 F7 Figure 6. Front End Circuit Using a High Speed Differential Amplifier Figure 7. DC-Coupled Amplifier 7

18 APPLICATIONS INFORMATION Reference The has an internal.25v voltage reference. For a 2.V input range using the internal reference, connect SENSE to V DD. For a.5v input range using the internal reference, connect SENSE to ground. For a 2.V input range with an external reference, apply a.25v reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between.625v and.3v. The input range will then be.68 V SENSE. The V REF, REFH and REFL pins should be bypassed as shown in Figure 8a. A low inductance 2.2μF interdigitated capacitor is recommended for the bypass between REFH and REFL. This type of capacitor is available at a low cost from multiple suppliers. Alternatively, C can be replaced by a standard 2.2μF capacitor between REFH and REFL. The capacitor should be as close to the pins as possible (not on the back side of the circuit board). Figures 8c and 8d show the recommended circuit board layout for the REFH/REFL bypass capacitors. Note that in Figure 8c, every pin of the interdigitated capacitor (C) is connected since the pins are not internally connected in some vendors capacitors. In Figure 8d, the REFH and REFL pins are connected by short jumpers in an internal layer. To minimize the inductance of these jumpers they can be placed in a small hole in the GND plane on the second board layer. C3 μf C2 μf C 2.2μF REFH REFL REFH REFL CAPACITORS ARE 42 PACKAGE SIZE 2269 F8b Figure 8b. Alternative REFH/REFL Bypass Circuit.25V V REF 2.2μF 5Ω.25V BANDGAP REFERENCE.625V 2269 F8c TIE TO V DD FOR 2.V RANGE; TIE TO GND FOR.5V RANGE; SENSE FOR.625V < V SENSE <.3V C2 μf C3 μf C + + C: 2.2μF LOW INDUCTANCE INTERDIGITATED CAPACITOR TDK CLLEAX7SG225M MURATA LLA29C7G225M AVX W2L4Z225M OR EQUIVALENT SENSE REFH REFL REFH REFL RANGE DETECT AND CONTROL Figure 8a. Reference Circuit BUFFER INTERNAL ADC HIGH REFERENCE.84x DIFF AMP INTERNAL ADC LOW REFERENCE 2269 F8 Figure 8c. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8a Figure 8d. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8b.25V EXTERNAL REFERENCE V REF 2.2μF SENSE μf 2269 F8d 2269 F9 Figure 9. Using an External.25V Reference

19 APPLICATIONS INFORMATION Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure ), and the single-ended encode mode (Figure ). V DD V DD DIFFERENTIAL COMPARATOR.μF.μF T T = MA/COM ETC--3 RESISTORS AND CAPACITORS ARE 42 PACKAGE SIZE 5Ω 5Ω.μF Ω ENC + ENC Figure 2. Sinusoidal Encode Drive 2269 F2 ENC + ENC 5k 3k PECL OR LVDS CLOCK.μF.μF ENC + ENC 2269 F3 Figure. Equivalent Encode Input Circuit for Differential Encode Mode.8V TO 3.3V V ENC + ENC 3k CMOS LOGIC BUFFER 2269 F Figure. Equivalent Encode Input Circuit for Single-Ended Encode Mode F The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 2, 3). The encode inputs are internally biased to.2v through kω equivalent resistance. The encode inputs can be taken above V DD (up to 3.6V), and the common mode range is from.v to.6v. In the differential encode mode, ENC should stay at least 2mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC + and ENC should have fast rise and fall times. The single ended encode mode should be used with CMOS encode inputs. To select this mode, ENC is connected to ground and ENC + is driven with a square wave Figure 3. PECL or LVDS Encode Drive encode input. ENC + can be taken above V DD (up to 3.6V) enabling.8v to 3.3V CMOS logic levels to be used. The ENC + threshold is.9v. For good jitter performance ENC + should have fast rise and fall times. If the encode signal is turned off or drops below approximately 5kHz, the A/D enters nap mode. Clock Duty Cycle Stabilizer For good performance the encode signal should have a 5%(±5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from % to 9% and the duty cycle stabilizer will maintain a constant 5% internal duty cycle. If the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled by mode control register A2 (serial programming mode), or by CS (parallel programming mode). For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 5%(±5%) duty cycle. The duty cycle stabilizer should not be used below 2Msps. 9

20 APPLICATIONS INFORMATION DIGITAL OUTPUTS Digital Output Modes The can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) The output mode is set by mode control register A3 (serial programming mode), or by SCK (parallel programming mode). Note that double data rate CMOS cannot be selected in the parallel programming mode. Full Rate CMOS Mode In full rate CMOS mode the data outputs (D to D5), overflow (OF), and the data output clocks (CLKOUT +, CLKOUT ) have CMOS output levels. The outputs are powered by OV DD and OGND which are isolated from the A/D core power and ground. OV DD can range from.v to.9v, allowing.2v through.8v CMOS logic outputs. For good performance, the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than pf, a digital buffer should be used. Double Data Rate CMOS Mode In double data rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces the number of digital lines by eight, simplifying board routing and reducing the number of input pins needed to receive the data. The data outputs (D_, D2_3, D4_5, D6_7, D8_9, D_, D2_3, D4_5), overflow (OF), and the data output clocks (CLKOUT +, CLKOUT ) have CMOS output levels. The outputs are powered by OV DD and OGND which are isolated from the A/D core power and ground. OV DD can range from.v to.9v, allowing.2v through.8v CMOS logic outputs. For good performance, the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than pf, a digital buffer should be used. Double Data Rate LVDS Mode In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair. There are eight LVDS output pairs (D_ + /D_ through D4_5 + / D4_5 ) for the digital output data. Overflow (OF + /OF ) and the data output clock (CLKOUT + /CLKOUT ) each have an LVDS output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a.25v output common mode voltage. An external Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OV DD and OGND which are isolated from the A/D core power and ground. In LVDS mode, OV DD must be.8v. Programmable LVDS Output Current In LVDS mode, the default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3. Available current levels are.75ma, 2.mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases using just an external Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal Ω termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit outputs a logic high when the analog input is either overranged or underranged. The overflow bit has the same pipeline latency as the data bits. 2

21 APPLICATIONS INFORMATION Phase-Shifting the Output Clock In full rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT +, so the rising edge of CLKOUT + can be used to latch the output data. In double data rate CMOS and LVDS modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT +. To allow adequate setup and hold time when latching the data, the CLKOUT + signal may need to be phase-shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The can also phase-shift the CLKOUT + /CLKOUT signals by serially programming mode control register A2. The output clock can be shifted by, 45, 9, or 35. To use the phase-shifting feature the clock duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT + and CLKOUT, independently of the phase-shift. The combination of these two features enables phase-shifts of 45 up to 35 (Figure 4). ENC + D-D5, OF PHASE SHIFT MODE CONTROL BITS CLKINV CLKPHASE CLKPHASE 45 9 CLKOUT F4 Figure 4. Phase-Shifting CLKOUT Table. Output Codes vs Input Voltage A IN + A IN (2V RANGE) OF >.V V V +.3V +.V.3V.6V V.V <.V D5 D (OFFSET BINARY) D5 D (2 S COMPLEMENT) 2

22 APPLICATIONS INFORMATION DATA FORMAT Table shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2 s complement format can be selected by serially programming mode control register A4. PC BOARD CLKOUT OF D5/D FPGA D5 Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusive- OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied an exclusive-or operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4. Figure 5. Functional Equivalent of Digital Output Randomizer 22 D RANDOMIZER ON CLKOUT OF D5 D4 D2 D 2269 F5 CLKOUT OF D5/D D4/D D2/D D/D D D4/D D2/D D/D D Figure 6. Decoding a Randomized Digital Output Signal Alternate Bit Polarity Another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D, D3, D5, D7, D9, D, D3, D5) are inverted before the output buffers. The even bits (D, D2, D4, D6, D8, D, D2, D4), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. When there is a very small signal at the input of the A/D that is centered around mid-scale, the digital outputs toggle between mostly s and mostly s. This simultaneous switching of most of the bits will cause large currents in the ground plane. By inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. This cancels current flow in the ground plane, reducing the digital noise. The digital output is decoded at the receiver by inverting the odd bits (D, D3, D5, D7, D9, D, D3, D5.) The alternate bit polarity mode is independent of the digital output randomizer either, both or neither function can be on at the same time. The alternate bit polarity mode is enabled by serially programming mode control register A4. D4 D2 D D 2269 F6

23 APPLICATIONS INFORMATION Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes that force the A/D data outputs (OF, D5 to D) to known values: All s: all outputs are All s: all outputs are Alternating: outputs change from all s to all s on alternating samples. Checkerboard: outputs change from to on alternating samples. The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the test patterns override all other formatting modes: 2 s complement, randomizer, alternate bit polarity. Output Disable The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high-impedance disabled state is intended for in-circuit testing or long periods of inactivity it is too slow to multiplex a data bus between multiple converters at full speed. When the outputs are disabled the ADC should be put into either sleep or nap mode. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire device is powered down, resulting in.5mw power consumption. The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on V REF, REFH, and REFL. For the suggested values in Figure 8, the A/D will stabilize after 2ms. In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wake-up than from sleep mode. Recovering from nap mode requires at least clock cycles. If the application demands very accurate DC settling then an additional 5μs should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Sleep mode and nap mode are enabled by mode control register A (serial programming mode), or by SDI and SDO (parallel programming mode). DEVICE PROGRAMMING MODES The operating modes of the can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to V DD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to V DD or ground, or driven by.8v, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a kω series resistor. Table 2 shows the modes set by CS, SCK, SDI and SDO. Table 2. Parallel Programming Mode Control Bits (PAR/SER = V DD ) PIN DESCRIPTION CS Clock Duty Cycle Stabilizer Control Bit = Clock Duty Cycle Stabilizer Off = Clock Duty Cycle Stabilizer On SCK Digital Output Mode Control Bit = Full Rate CMOS Output Mode = Double Data Rate LVDS Output Mode (3.5mA LVDS Current, Internal Termination Off) SDI/SDO Power-Down Control Bits = Normal Operation = Not Used = Nap Mode = Sleep Mode (Entire Device Powered Down) 23

24 APPLICATIONS INFORMATION Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 6-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 6 rising edges of SCK. Any SCK rising edges after the first 6 are ignored. The data transfer ends when CS is taken high again. The first bit of the 6-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A). The final eight bits are the register data (D7:D). If the R/W bit is low, the serial data (D7:D) will be written to the register set by the address bits (A6:A). If the R/W bit is high, data in the register set by the address bits (A6:A) will be read back on the SDO pin (see the Timing Diagrams). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open drain output that pulls to ground with a 2Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic. To perform a software reset, bit D7 in the reset register is written with a logic. After the reset SPI write command is complete, bit D7 is automatically set back to zero. Table 3. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A: RESET REGISTER (ADDRESS h) D7 D6 D5 D4 D3 D2 D D RESET X X X X X X X Bits 7 RESET Software Reset Bit = Not Used = Software Reset. All Mode Control Registers are reset to h. The ADC is momentarily placed in sleep mode. This bit is automatically set back to zero at the end of the SPI write command. The Reset register is write-only. Data read back from the reset register will be random. Bits 6- Unused, Don t Care Bits REGISTER A: POWER DOWN REGISTER (ADDRESS h) D7 D6 D5 D4 D3 D2 D D X X X X X X PWROFF PWROFF Bits 7-2 Unused, Don t Care Bits Bits - PWROFF: PWROFF Power Down Control Bits = Normal Operation = Not Used = Nap Mode = Sleep Mode 24

25 APPLICATIONS INFORMATION REGISTER A2: TIMING REGISTER (ADDRESS 2h) D7 D6 D5 D4 D3 D2 D D X X X X CLKINV CLKPHASE CLKPHASE DCS Bits 7-4 Unused, Don t Care Bits Bit 3 CLKINV Output Clock Invert Bit = Normal CLKOUT Polarity (as shown in the Timing Diagrams) = Inverted CLKOUT Polarity Bits 2- CLKPHASE: CLKPHASE Output Clock Phase Delay Bits = No CLKOUT Delay (as shown in the Timing Diagrams) = CLKOUT + /CLKOUT Delayed by 45 (Clock Period /8) = CLKOUT + /CLKOUT Delayed by 9 (Clock Period /4) = CLKOUT + /CLKOUT Delayed by 35 (Clock Period 3/8) Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on. Bit DCS Clock Duty Cycle Stabilizer Bit = Clock Duty Cycle Stabilizer Off = Clock Duty Cycle Stabilizer On REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 3h) D7 D6 D5 D4 D3 D2 D D X ILVDS2 ILVDS ILVDS TERMON OUTOFF OUTMODE OUTMODE Bit 7 Unused, Don t Care Bit Bits 6-4 ILVDS2: ILVDS LVDS Output Current Bits = 3.5mA LVDS Output Driver Current = 4.mA LVDS Output Driver Current = 4.5mA LVDS Output Driver Current = Not Used = 3.mA LVDS Output Driver Current = 2.5mA LVDS Output Driver Current = 2.mA LVDS Output Driver Current =.75mA LVDS Output Driver Current Bit 3 TERMON LVDS Internal Termination Bit = Internal Termination Off = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS. 25

26 APPLICATIONS INFORMATION Bit 2 OUTOFF Output Disable Bit = Digital outputs are enabled. = Digital outputs are disabled and have high output impedance. Note: If the digital outputs are disabled the part should also be put in sleep mode or nap mode. Bits - OUTMODE: OUTMODE Digital Output Mode Control Bits = Full Rate CMOS Output Mode = Double Data Rate LVDS Output Mode = Double Data Rate CMOS Output Mode = Not Used REGISTER A4: DATA FORMAT REGISTER (ADDRESS 4h) D7 D6 D5 D4 D3 D2 D D X X OUTTEST2 OUTTEST OUTTEST ABP RAND TWOSCOMP Bits 7-6 Unused, Don t Care Bits Bits 5-3 OUTTEST2: OUTTEST Digital Output Test Pattern Bits = Digital Output Test Patterns Off = All Digital Outputs = = All Digital Outputs = = Checkerboard Output Pattern. OF, D5-D alternate between and. = Alternating Output Pattern. OF, D5-D alternate between and. Note: Other bit combinations are not used. Bit 2 ABP Alternate Bit Polarity Mode Control Bit = Alternate Bit Polarity Mode Off = Alternate Bit Polarity Mode On. Forces the output format to be Offset Binary. Bit RAND Data Output Randomizer Mode Control Bit = Data Output Randomizer Mode Off = Data Output Randomizer Mode On Bits TWOSCOMP Two s Complement Mode Control Bit = Offset Binary Data Format = Two s Complement Data Format 26

27 APPLICATIONS INFORMATION GROUNDING AND BYPASSING The requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the ADC. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the V DD, OV DD, V CM, V REF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Size 42 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Of particular importance is the capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. 27

28 TYPICAL APPLICATIONS Silkscreen Top Inner Layer 2 Top Side Inner Layer 3 28

29 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Bottom Side 29

30 TYPICAL APPLICATIONS C23 2.2μF SDO SENSE V DD C9.μF C5 μf C2 μf C5 μf + + CN A IN + A IN + + PAR/SER V DD V DD SENSE V REF SDO V CM A IN + A IN GND REFH REFL REFH REFL PAR/SER GND GND V DD GND OF DNC D5 D4 D3 D2 D D D9 D8 OV DD OGND CLKOUT + CLKOUT D7 D6 D5 D C37.μF OV DD DIGITAL OUTPUTS V DD V GND ENC + ENC DD CS SCK SDI GND D D D2 D3 C μF C: 2.2μF LOW INDUCTANCE INTERDIGITATED CAPACITOR TDK CLLEAX7SG225M MURATA LLA29C7G225M AVX W2L4Z225M OR EQUIVALENT C28.μF R5 Ω C32.μF SPI PORT 2269 TA3 ENCODE CLOCK 3