LTC / LTC /LTC Bit, 65Msps/40Msps/ 25Msps Low Power Quad ADCs DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

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1 FETURES n 4-Channel Simultaneous Sampling DC n 73.7dB SNR n 9dB SFDR n Low Power: 311mW/22mW/162mW Total, 78mW/51mW/41mW per Channel n Single 1.8V Supply n Serial LVDS Outputs: One or Two Bits per Channel n Selectable Input Ranges: 1V P-P to 2V P-P n 8MHz Full Power Bandwidth Sample-and-Hold n Shutdown and Nap Modes n Serial SPI Port for Confi guration n Pin-Compatible 14-Bit and 12-Bit Versions n 52-Pin (7mm 8mm) QFN Package PPLICTIONS n Communications n Cellular Base Stations n Software Defi ned Radios n Portable Medical Imaging n Multichannel Data cquisition n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. ll other trademarks are the property of their respective owners. TYPICL PPLICTION 14-Bit, 65Msps/4Msps/ 25Msps Low Power Quad DCs DESCRIPTION The LTC / are 4-channel, simultaneous sampling 14-bit /D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with C performance that includes 73.7dB SNR and 9dB spurious free dynamic range (SFDR). n ultralow jitter of.15ps RMS allows undersampling of IF frequencies with excellent noise performance. DC specifications include ±1LSB INL (typ), ±.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSB RMS. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC + and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. n internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. CHNNEL 1 CHNNEL 2 CHNNEL 3 CHNNEL 4 ENCODE S/H S/H S/H S/H 1.8V V DD 1.8V OV DD 14-BIT DC CORE 14-BIT DC CORE 14-BIT DC CORE 14-BIT DC CORE PLL DT SERILIZER OUT1 OUT1B OUT2 OUT2B OUT3 OUT3B OUT4 OUT4B DT CLOCK OUT FRME SERILIZED LVDS OUTPUTS MPLITUDE () LTC , 65Msps, 2-Tone FFT, f IN = 7MHz and 75MHz FREQUENCY (MHz) T1b GND OGND T fa 1

2 BSOLUTE MXIMUM RTINGS (Notes 1 and 2) Supply Voltages V DD, OV DD....3V to 2V nalog Input Voltage ( IN +, IN, PR/SER, SENSE) (Note 3)....3V to (V DD +.2V) Digital Input Voltage (ENC +, ENC, CS, SDI, SCK) (Note 4)....3V to 3.9V SDO (Note 4)....3V to 3.9V Digital Output Voltage....3V to (OV DD +.3V) Operating Temperature Range LTC2172C, LTC2171C, LTC217C... C to 7 C LTC2172I, LTC2171I, LTC217I... 4 C to 85 C Storage Temperature Range C to 15 C PIN CONFIGURTION IN1 + IN1 V CM12 IN2 + IN2 REFH REFH REFL 8 REFL 9 + IN3 1 IN3 11 V CM IN4 13 IN TOP VIEW V DD V DD SENSE GND VREF PR/SER SDO GND OUT1 + OUT1 OUT1B + OUT1B GND OUT2 + OUT2 OUT2B + OUT2B DCO + DCO OV DD OGND FR + FR OUT3 + OUT3 OUT3B + OUT3B V DD V DD ENC + ENC CS SCK SDI GND OUT4B OUT4B + OUT4 OUT4 + UKG PCKGE 52-LED (7mm 8mm) PLSTIC QFN T JMX = 15 C, θ J = 28 C/W EXPOSED PD (PIN 53) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMTION LED FREE FINISH TPE ND REEL PRT MRKING* PCKGE DESCRIPTION TEMPERTURE RNGE LTC2172CUKG-14#PBF LTC2172CUKG-14#TRPBF LTC2172UKG Lead (7mm 8mm) Plastic QFN C to 7 C LTC2172IUKG-14#PBF LTC2172IUKG-14#TRPBF LTC2172UKG Lead (7mm 8mm) Plastic QFN 4 C to 85 C LTC2171CUKG-14#PBF LTC2171CUKG-14#TRPBF LTC2171UKG Lead (7mm 8mm) Plastic QFN C to 7 C LTC2171IUKG-14#PBF LTC2171IUKG-14#TRPBF LTC2171UKG Lead (7mm 8mm) Plastic QFN 4 C to 85 C LTC217CUKG-14#PBF LTC217CUKG-14#TRPBF LTC217UKG Lead (7mm 8mm) Plastic QFN C to 7 C LTC217IUKG-14#PBF LTC217IUKG-14#TRPBF LTC217UKG Lead (7mm 8mm) Plastic QFN 4 C to 85 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: For more information on tape and reel specifi cations, go to: fa

3 CONVERTER CHRCTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25 C. (Note 5) LTC LTC LTC PRMETER CONDITIONS MIN TYP MX MIN TYP MX MIN TYP MX UNITS Resolution (No Missing Codes) l Bits Integral Linearity Error Differential nalog Input (Note 6) l 3.25 ± ± ± LSB Differential Linearity Error Differential nalog Input l.8 ± ± ±.3.8 LSB Offset Error (Note 7) l 12 ± ± ±3 12 mv Gain Error Internal Reference External Reference l %FS %FS Offset Drift ±2 ±2 ±2 μv/ C Full-Scale Drift Internal Reference External Reference ±35 ±25 ±35 ±25 ±35 ±25 ppm/ C ppm/ C Gain Matching External Reference ±.2 ±.2 ±.2 %FS Offset Matching ±3 ±3 ±3 mv Transition Noise External Reference LSB RMS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25 C. (Note 5) SYMBOL PRMETER CONDITIONS MIN TYP MX UNITS V IN nalog Input Range ( + IN IN ) 1.7V < V DD < 1.9V l 1 to 2 V P-P V IN(CM) nalog Input Common Mode ( + IN + IN )/2 Differential nalog Input (Note 8) l V CM 1mV V CM V CM + 1mV V V SENSE External Voltage Reference pplied to SENSE External Reference Mode l V I IN(CM) nalog Input Common Mode Current Per Pin, 65Msps Per Pin, 4Msps Per Pin, 25Msps I IN1 nalog Input Leakage Current (No Encode) < + IN, IN < V DD l 1 1 μ I IN2 PR/SER Input Leakage Current < PR/SER < V DD l 3 3 μ I IN3 SENSE Input Leakage Current.625 < SENSE < 1.3V l 6 6 μ t P Sample-and-Hold cquisition Delay Time ns t JITTER Sample-and-Hold cquisition Delay Jitter.15 ps RMS CMRR nalog Input Common Mode Rejection Ratio 8 db BW-3B Full-Power Bandwidth Figure 6 Test Circuit 8 MHz μ μ μ fa 3

4 DYNMIC CCURCY The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifications are at T = 25 C. IN = 1. (Note 5) SYMBOL PRMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 3MHz Input 7MHz Input 14MHz Input SFDR Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 3MHz Input 7MHz Input 14MHz Input S/(N+D) Spurious Free Dynamic Range 4th Harmonic or Higher Signal-to-Noise Plus Distortion Ratio 5MHz Input 3MHz Input 7MHz Input 14MHz Input 5MHz Input 3MHz Input 7MHz Input 14MHz Input l 72. l 77 l 85 l 71.2 LTC LTC LTC MIN TYP MX MIN TYP MX MIN TYP MX Crosstalk, Near Channel 1MHz Input (Note 12) dbc Crosstalk, Far Channel 1MHz Input (Note 12) dbc UNITS INTERNL REFERENCE CHRCTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25 C. IN = 1. (Note 5) PRMETER CONDITIONS MIN TYP MX UNITS V CM Output Voltage I OUT =.5 V DD 25mV.5 V DD.5 V DD + 25mV V V CM Output Temperature Drift ±25 ppm/ C V CM Output Resistance 6μ < I OUT < 1m 4 Ω V REF Output Voltage I OUT = V V REF Output Temperature Drift ±25 ppm/ C V REF Output Resistance 4μ < I OUT < 1m 7 Ω V REF Line Regulation 1.7V < V DD < 1.9V.6 mv/v fa

5 DIGITL S ND OUTPUTS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25 C. (Note 5) SYMBOL PRMETER CONDITIONS MIN TYP MX UNITS ENCODE S (ENC +, ENC ) Differential Encode Mode (ENC Not Tied to GND) V ID Differential Input Voltage (Note 8) l.2 V V ICM Common Mode Input Voltage Internally Set 1.2 V Externally Set (Note 8) l V V IN Input Voltage Range ENC +, ENC to GND l V R IN Input Resistance (See Figure 1) 1 kω C IN Input Capacitance 3.5 pf Single-Ended Encode Mode (ENC Tied to GND) V IH High Level Input Voltage V DD = 1.8V l 1.2 V V IL Low Level Input Voltage V DD = 1.8V l.6 V V IN Input Voltage Range ENC + to GND l 3.6 V R IN Input Resistance (See Figure 11) 3 kω C IN Input Capacitance 3.5 pf DIGITL S (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) V IH High Level Input Voltage V DD = 1.8V l 1.3 V V IL Low Level Input Voltage V DD = 1.8V l.6 V I IN Input Current V IN = V to 3.6V l 1 1 μ C IN Input Capacitance 3 pf SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used) R OL Logic Low Output Resistance to GND V DD = 1.8V, SDO = V 2 Ω I OH Logic High Output Leakage Current SDO = V to 3.6V l 1 1 μ C OUT Output Capacitance 3 pf DIGITL DT OUTPUTS V OD Differential Output Voltage 1Ω Differential Load, 3.5m Mode 1Ω Differential Load, 1.75m Mode V OS Common Mode Output Voltage 1Ω Differential Load, 3.5m Mode 1Ω Differential Load, 1.75m Mode l l R TERM On-Chip Termination Resistance Termination Enabled, OV DD = 1.8V 1 Ω l l mv mv V V fa 5

6 POWER REQUIREMENTS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25 C. (Note 9) LTC LTC LTC SYMBOL PRMETER CONDITIONS MIN TYP MX MIN TYP MX MIN TYP MX UNITS V DD nalog Supply Voltage (Note 1) l V OV DD Output Supply Voltage (Note 1) l V I VDD nalog Supply Current Sine Wave Input l m I OVDD Digital Supply Current 1-Lane Mode, 1.75m Mode 1-Lane Mode, 3.5m Mode 2-Lane Mode, 1.75m Mode 2-Lane Mode, 3.5m Mode P DISS Power Dissipation 1-Lane Mode, 1.75m Mode 1-Lane Mode, 3.5m Mode 2-Lane Mode, 1.75m Mode 2-Lane Mode, 3.5m Mode l l l l P SLEEP Sleep Mode Power mw P NP Nap Mode Power mw P DIFFCLK Power Increase with Differential Encode Mode Enabled (No Increase for Sleep Mode) mw m m m m mw mw mw mw TIMING CHRCTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25 C. (Note 5) LTC LTC LTC SYMBOL PRMETER CONDITIONS MIN TYP MX MIN TYP MX MIN TYP MX UNITS f S Sampling Frequency (Notes 1, 11) l MHz t ENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On t ENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On t P Sample-and-Hold cquisition Delay Time l l l l ns ns ns ns ns fa

7 TIMING CHRCTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25 C. (Note 5) SYMBOL PRMETER CONDITIONS MIN TYP MX UNITS Digital Data Outputs (R TERM = 1Ω Differential, C L = 2pF to GND on Each Output) t SER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization 1 / (8 f S ) 1 / (7 f S ) 1 / (6 f S ) 1 / (16 f S ) 1 / (14 f S ) 1 / (12 f S ) t FRME FR to DCO Delay (Note 8) l.35 t SER.5 t SER.65 t SER s t DT DT to DCO Delay (Note 8) l.35 t SER.5 t SER.65 t SER s t PD Propagation Delay (Note 8) l.7n + 2 t SER 1.1n + 2 t SER 1.5n + 2 t SER s t R Output Rise Time Data, DCO, FR, 2% to 8%.17 ns t F Output Fall Time Data, DCO, FR, 2% to 8%.17 ns DCO Cycle-to-Cycle Jitter t SER = 1ns 6 ps P-P Pipeline Latency 6 Cycles SPI Port Timing (Note 8) t SCK SCK Period Write Mode Readback Mode, C SDO = 2pF, R PULLUP = 2k t S CS to SCK Set-Up Time l 5 ns t H SCK to CS Set-Up Time l 5 ns t DS SDI Set-Up Time l 5 ns t DH SDI Hold Time l 5 ns t DO SCK Falling to SDO Valid Readback Mode C SDO = 2pF, R PULLUP = 2k l 125 ns l l 4 25 s s s s s s ns ns Note 1: Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. Exposure to any bsolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: ll voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than 1m below GND or above V DD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 1m below GND without latchup. Note 5: V DD = OV DD = 1.8V, f SMPLE = 65MHz (LTC2172), 4MHz (LTC2171), or 25MHz (LTC217), 2-lane output mode, differential ENC + /ENC = 2V P-P sine wave, input range = 2V P-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fi t straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from.5 LSB when the output code fl ickers between and in 2 s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: V DD = OV DD = 1.8V, f SMPLE = 65MHz (LTC2172), 4MHz (LTC2171), or 25MHz (LTC217), 2-lane output mode, ENC + = singleended 1.8V square wave, ENC = V, input range = 2V P-P with differential drive, unless otherwise noted. The supply current and power dissipation specifi cations are totals for the entire chip, not per channel. Note 1: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1Mbps, so t SER must be greater than or equal to 1ns. Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4. Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and Ch.2 to Ch fa 7

8 TIMING DIGRMS 2-Lane Output Mode, 16-Bit Serialization* N t P N + 1 ENC ENC + t ENCH t ENCL DCO t SER DCO + FR FR + OUT# OUT# + OUT#B OUT#B + t FRME t DT t SER t PD t SER D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D4 D2 D D12 D1 D8 D6 D4 D2 D D12 D1 D8 SMPLE N-6 SMPLE N-5 SMPLE N TD1 *SEE THE DIGITL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization ENC ENC + DCO DCO + FR N t P N + 2 N + 1 t ENCH t ENCL t SER t DT t SER t FRME FR + OUT# OUT# + OUT#B OUT#B + t PD t SER D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D6 D4 D2 D D12 D1 D8 D6 D4 D2 D D12 D1 D8 D6 D4 D2 D D12 D1 D8 SMPLE N-6 SMPLE N-5 SMPLE N-4 SMPLE N TD2 NOTE THT IN THIS MODE, FR + /FR HS TWO TIMES THE PERIOD OF ENC + /ENC fa

9 TIMING DIGRMS 2-Lane Output Mode, 12-Bit Serialization ENC ENC + DCO DCO + FR + N t P N + 1 t ENCH t ENCL t SER t DT t SER t FRME FR OUT# OUT# + OUT#B OUT#B + t PD t SER D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D1 D8 D6 D4 D2 D12 D1 D8 SMPLE N-6 SMPLE N-5 SMPLE N TD3 1-Lane Output Mode, 16-Bit Serialization ENC ENC + DCO DCO + FR N t P N + 1 t ENCH t ENCL t SER t FRME t DT t SER FR + OUT# OUT# + t PD t SER D1 D D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D D13 D12 D11 D1 SMPLE N-6 SMPLE N-5 SMPLE N TD4 OUT#B +, OUT#B RE DISBLED fa 9

10 TIMING DIGRMS 1-Lane Output Mode, 14-Bit Serialization ENC ENC + DCO DCO + FR N t P N + 1 t ENCH t ENCL t SER t FRME t DT t SER FR + OUT# OUT# + t PD t SER D3 D2 D1 D D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D D13 D12 D11 D1 SMPLE N-6 SMPLE N-5 SMPLE N TD5 OUT#B +, OUT#B RE DISBLED 1-Lane Output Mode, 12-Bit Serialization ENC ENC + DCO DCO + FR N t P N + 1 t ENCH t ENCL t SER t FRME t DT t SER FR + OUT# OUT# + t PD t SER D5 D4 D3 D2 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 SMPLE N-6 SMPLE N-5 SMPLE N TD6 OUT#B +, OUT#B RE DISBLED fa

11 TIMING DIGRMS SPI Port Timing (Readback Mode) t S t DS t DH t SCK t H CS SCK t DO SDI R/W XX XX XX XX XX XX XX XX SDO HIGH IMPEDNCE D7 D6 D5 D4 D3 D2 D1 D SPI Port Timing (Write Mode) CS SCK SDI R/W D7 D6 D5 D4 D3 D2 D1 D SDO HIGH IMPEDNCE TD fa 11

12 TYPICL PERFORMNCE CHRCTERISTICS INL ERROR (LSB) LTC : Integral Nonlinearity (INL) OUTPUT CODE G1 DNL ERROR (LSB) LTC : Differential Nonlinearity (DNL) OUTPUT CODE G2 MPLITUDE () LTC : 8k Point FFT, f IN = 5MHz 1, 65Msps FREQUENCY (MHz) G3 MPLITUDE () LTC : 8k Point FFT, f IN = 3MHz 1, 65Msps FREQUENCY (MHz) MPLITUDE () LTC : 8k Point FFT, f IN = 7MHz 1, 65Msps FREQUENCY (MHz) MPLITUDE () LTC : 8k Point FFT, f IN = 14MHz 1, 65Msps FREQUENCY (MHz) MPLITUDE () G4 LTC : 8k Point 2-Tone FFT, f IN = 68MHz, 69MHz, 1, 65Msps FREQUENCY (MHz) COUNT LTC : Shorted Input Histogram G OUTPUT CODE SNR () LTC : SNR vs Input Frequency, 1, 2V Range, 65Msps G FREQUENCY (MHz) G G G fa

13 TYPICL PERFORMNCE CHRCTERISTICS SFDR () LTC : SFDR vs Input Frequency, 1, 2V Range, 65Msps FREQUENCY (MHz) SFDR (dbc ND ) LTC : SFDR vs Input Level, f IN = 7MHz, 2V Range, 65Msps dbc LEVEL () SNR (dbc ND ) LTC : SNR vs Input Level, f IN = 7MHz, 2V Range, 65Msps dbc LEVEL () G G G5 16 LTC : I VDD vs Sample Rate, 5MHz Sine Wave Input, 1 5 I OVDD vs Sample Rate, 5MHz Sine Wave Input, 1 75 LTC : SNR vs SENSE, f IN = 5MHz, 1 I VDD (m) IO VDD (m) LNE, 3.5m 1-LNE, 3.5m 2-LNE, 1.75m 1-LNE, 1.75m SNR () SMPLE RTE (Msps) SMPLE RTE (Msps) SENSE PIN (V) G G G14 INL ERROR (LSB) LTC : Integral Nonlinearity (INL) OUTPUT CODE G15 DNL ERROR (LSB) LTC : Differential Nonlinearity (DNL) OUTPUT CODE G16 MPLITUDE () LTC : 8k Point FFT, f IN = 5MHz 1, 4Msps 1 2 FREQUENCY (MHz) G fa 13

14 TYPICL PERFORMNCE CHRCTERISTICS MPLITUDE () LTC : 8k Point FFT, f IN = 29MHz 1, 4Msps 1 2 FREQUENCY (MHz) MPLITUDE () LTC : 8k Point FFT, f IN = 69MHz 1, 4Msps 1 2 FREQUENCY (MHz) MPLITUDE () LTC : 8k Point FFT, f IN = 139MHz 1, 4Msps 1 2 FREQUENCY (MHz) MPLITUDE () G18 LTC : 8k Point 2-Tone FFT, f IN = 68MHz, 69MHz, 1, 4Msps 1 2 FREQUENCY (MHz) COUNT LTC : Shorted Input Histogram G OUTPUT CODE SNR () G2 LTC : SNR vs Input Frequency, 1, 2V Range, 4Msps FREQUENCY (MHz) G G G23 95 LTC : SFDR vs Input Frequency, 1, 2V Range, 4Msps 11 LTC : SFDR vs Input Level, f IN = 7MHz, 2V Range, 4Msps 1 LTC : I VDD vs Sample Rate, 5MHz Sine Wave Input, 1 SFDR () FREQUENCY (MHz) SFDR (dbc ND ) dbc LEVEL () I VDD (m) SMPLE RTE (Msps) G G G fa

15 TYPICL PERFORMNCE CHRCTERISTICS 74 LTC : SNR vs SENSE, f IN = 5MHz, 1 2. LTC217-14: Integral Nonlinearity (INL) 1. LTC217-14: Differential Nonlinearity (DNL) SNR () INL ERROR (LSB) DNL ERROR (LSB) SENSE PIN (V) OUTPUT CODE OUTPUT CODE G G G29 MPLITUDE () MPLITUDE () LTC217-14: 8k Point FFT, f IN = 5MHz 1, 25Msps 5 1 FREQUENCY (MHz) LTC217-14: 8k Point FFT, f IN = 14MHz 1, 25Msps 5 1 FREQUENCY (MHz) G G33 MPLITUDE () MPLITUDE () LTC217-14: 8k Point FFT, f IN = 3MHz 1, 25Msps 5 1 FREQUENCY (MHz) G31 LTC217-14: 8k Point 2-Tone FFT, f IN = 68MHz, 69MHz, 1, 25Msps 5 1 FREQUENCY (MHz) G34 MPLITUDE () COUNT LTC217-14: 8k Point FFT, f IN = 7MHz 1, 25Msps 5 1 FREQUENCY (MHz) LTC217-14: Shorted Input Histogram G OUTPUT CODE G fa 15

16 TYPICL PERFORMNCE CHRCTERISTICS SNR () LTC217-14: SNR vs Input Frequency, 1, 2V Range, 25Msps FREQUENCY (MHz) SFDR () LTC217-14: SFDR vs Input Frequency, 1, 2V Range, 25Msps FREQUENCY (MHz) SFDR (dbc ND ) LTC217-14: SFDR vs Input Level, f IN = 7MHz, 2V Range, 25Msps dbc LEVEL () G G G38 8 LTC217-14: I VDD vs Sample Rate, 5MHz Sine Wave Input, 1 74 LTC217-14: SNR vs SENSE, f IN = 5MHz, 1 35 DCO Cycle-Cycle Jitter vs Serial Data Rate 73 3 I VDD (m) SNR () PEK-TO-PEK JITTER (ps) SMPLE RTE (Msps) SENSE PIN (V) SERIL DT RTE (Mbps) G G G fa

17 PIN FUNCTIONS + IN1 (Pin 1): Channel 1 Positive Differential nalog Input. IN1 (Pin 2): Channel 1 Negative Differential nalog Input. V CM12 (Pin 3): Common Mode Bias Output, Nominally Equal to V DD /2. V CM should be used to bias the common mode of the analog inputs of channels 1 and 2. Bypass to ground with a.1μf ceramic capacitor. + IN2 (Pin 4): Channel 2 Positive Differential nalog Input. IN2 (Pin 5): Channel 2 Negative Differential nalog Input. REFH (Pins 6, 7): DC High Reference. Bypass to Pin 8 and Pin 9 with a 2.2μF ceramic capacitor, and to ground with a.1μf ceramic capacitor. REFL (Pins 8, 9): DC Low Reference. Bypass to Pin 6 and Pin 7 with a 2.2μF ceramic capacitor, and to ground with a.1μf ceramic capacitor. + IN3 (Pin 1): Channel 3 Positive Differential nalog Input. IN3 (Pin 11): Channel 3 Negative Differential nalog Input. V CM34 (Pin 12): Common Mode Bias Output, Nominally Equal to V DD /2. V CM should be used to bias the common mode of the analog inputs of channels 3 and 4. Bypass to ground with a.1μf ceramic capacitor. + IN4 (Pin 13): Channel 4 Positive Differential nalog Input. IN4 (Pin 14): Channel 4 Negative Differential nalog Input. V DD (Pins 15, 16, 51, 52): 1.8V nalog Power Supply. Bypass to ground with.1μf ceramic capacitors. djacent pins can share a bypass capacitor. ENC + (Pin 17): Encode Input. Conversion starts on the rising edge. ENC (Pin 18): Encode Complement Input. Conversion starts on the falling edge. CS (Pin 19): In serial programming mode (PR/SER = V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PR/SER = V DD ), CS selects two-lane or one-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (Pin 2): In serial programming mode (PR/SER = V), SCK is the serial interface clock input. In parallel programming mode (PR/SER = V DD ), SCK selects 3.5m or 1.75m LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 21): In serial programming mode (PR/SER = V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PR/SER = V DD ), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (Pins 22, 45, 49, Exposed Pad Pin 53): DC Power Ground. The exposed pad must be soldered to the PCB ground. OGND (Pin 33): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OV DD (Pin 34): Output Driver Supply. Bypass to ground with a.1μf ceramic capacitor. SDO (Pin 46): In serial programming mode (PR/SER = V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain N-channel MOSFET output that requires an external 2k pull-up resistor of 1.8V to 3.3V. If readback from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In parallel programming fa 17

18 PIN FUNCTIONS mode (PR/SER = V DD ), SDO is an input that enables internal 1Ω termination resistors on the digital outputs. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. PR/SER (Pin 47): Programming Mode Selection Pin. Connect to ground to enable serial programming mode. CS, SCK, SDI and SDO become a serial interface that controls the /D operating modes. Connect to V DD to enable parallel programming mode where CS, SCK, SDI and SDO become parallel logic inputs that control a reduced set of the /D operating modes. PR/SER should be connected directly to ground or the V DD of the part and not be driven by a logic signal. V REF (Pin 48): Reference Voltage Output. Bypass to ground with a 1μF ceramic capacitor, nominally 1.25V. SENSE (Pin 5): Reference Programming Pin. Connecting SENSE to V DD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±.5V input range. n external reference between.625v and 1.3V applied to SENSE selects an input range of ±.8 V SENSE. LVDS OUTPUTS The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 1Ω termination resistor between the pins of each LVDS output pair. OUT4B /OUT4B +, OUT4 /OUT4 + (Pins 23/24, Pins 25/ 26): Serial Data Outputs for Channel 4. In 1-lane output mode, only OUT4 /OUT4 + are used. OUT3B /OUT3B +, OUT3 /OUT3 + (Pins 27/28, Pins 29/3): Serial Data Outputs for Channel 3. In 1-lane output mode, only OUT3 /OUT3 + are used. FR /FR + (Pin 31/Pin 32): Frame Start Output. DCO /DCO + (Pin 35/Pin 36): Data Clock Output. OUT2B /OUT2B +, OUT2 /OUT2 + (Pins 37/38, Pins 39/4): Serial Data Outputs for Channel 2. In 1-lane output mode, only OUT2 /OUT2 + are used. OUT2B /OUT2B +, OUT2 /OUT2 + (Pins 41/42, Pins 43/44): Serial Data Outputs for Channel 1. In 1-lane output mode, only OUT1 /OUT1 + are used fa

19 FUNCTIONL BLOCK DIGRM 1.8V ENC + ENC 1.8V V DD OV DD CHNNEL 1 SMPLE- ND-HOLD 14-BIT DC CORE PLL OUT1 OUT1B CHNNEL 2 SMPLE- ND-HOLD 14-BIT DC CORE OUT2 OUT2B DT SERILIZER CHNNEL 3 SMPLE- ND-HOLD 14-BIT DC CORE OUT3 OUT3B OUT4 CHNNEL 4 SMPLE- ND-HOLD 14-BIT DC CORE OUT4B V REF 1μF 1.25V REFERENCE DT CLOCKOUT FRME RNGE SELECT OGND SENSE REF BUF REFH REFL DIFF REF MP V DD /2 MODE CONTROL REGISTERS GND REFH.1μF REFL VCM12.1μF VCM34.1μF PR/SER CS SCK SDI SDO F1 2.2μF.1μF.1μF Figure 1. Functional Block Diagram fa 19

20 PPLICTIONS INFORMTION CONVERTER OPERTION The are low power, 4-channel, 14-bit, 65Msps/4Msps/25Msps /D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the V CM12 or V CM34 output pins, which are nominally V DD /2. For the 2V input range, the inputs should swing from V CM.5V to V CM +.5V. There should be a 18 phase difference between the inputs. The four channels are simultaneously sampled by a shared encode circuit (Figure 2). DRIVE CIRCUITS Input Filtering If possible, there should be an RC lowpass fi lter right at the analog inputs. This lowpass filter isolates the drive circuitry from the /D sample-and-hold switching and limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application s input frequency. LTC Ω V CM IN + IN 1Ω 1Ω V DD V DD V DD C PRSITIC 1.8pF C PRSITIC 1.8pF R ON 25Ω R ON 25Ω C SMPLE 3.5pF C SMPLE 3.5pF.1μF T1 1:1 25Ω 25Ω T1: M/COM MBES6 RESISTORS, CPCITORS RE 42 PCKGE SIZE 25Ω.1μF 25Ω.1μF + IN 12pF IN LTC F3 ENC + 1.2V 1k Figure 3. nalog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 7MHz ENC 1.2V 1k F2 Figure 2. Equivalent Input Circuit. Only One of the Four nalog Channels Is Shown fa

21 PPLICTIONS INFORMTION Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with V CM, setting the /D input at its optimal DC level. t higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower /D distortion. mplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is C-coupled to the /D so the amplifier s output common mode voltage can be optimally set to minimize distortion. t very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the /D. 5Ω V CM 5Ω V CM.1μF T1 T2 25Ω.1μF.1μF + IN LTC μF T1 T2 25Ω.1μF.1μF + IN LTC μF 25Ω 4.7pF IN.1μF 25Ω 1.8pF IN F F5 T1: M/COM MB T2: M/COM MBES6 RESISTORS, CPCITORS RE 42 PCKGE SIZE Figure 4. Recommended Front-End Circuit for Input Frequencies from 7MHz to 17MHz T1: M/COM MB T2: COILCRFT WBC1-1LB RESISTORS, CPCITORS RE 42 PCKGE SIZE Figure 5. Recommended Front-End Circuit for Input Frequencies from 17MHz to 3MHz.1μF.1μF T1 25Ω 25Ω 5Ω 2.7nH.1μF 2.7nH V CM.1μF + IN IN LTC HIGH SPEED DIFFERENTIL.1μF MPLIFIER + +.1μF 2Ω 2Ω 25Ω 25Ω V CM.1μF + IN 12pF IN LTC T1: M/COM ETC RESISTORS, CPCITORS RE 42 PCKGE SIZE F F7 Figure 6. Recommended Front-End Circuit for Input Frequencies bove 3MHz Figure 7. Front-End Circuit Using a High Speed Differential mplifi er fa 21

22 PPLICTIONS INFORMTION Reference The has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to V DD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between.625v and 1.3V. The input range will then be 1.6 V SENSE. The reference is shared by all four DC channels, so it is not possible to independently adjust the input range of individual channels. The V REF, REFH and REFL pins should be bypassed, as shown in Figure 8. The.1μF capacitor between REFH and REFL should be as close to the pins as possible (not on the backside of the circuit board). Encode Input The signal quality of the encode inputs strongly affects the /D noise performance. The encode inputs should be treated as analog signals do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 1), and the single-ended encode mode (Figure 11). 1.25V EXTERNL REFERENCE V REF 1μF SENSE 1μF LTC F9 Figure 9. Using an External 1.25V Reference 1.25V 1μF V REF LTC Ω 1.25V BNDGP REFERENCE.625V LTC V DD V DD DIFFERENTIL COMPRTOR TIE TO V DD FOR 2V RNGE; TIE TO GND FOR 1V RNGE; RNGE = 1.6 V SENSE FOR.625V < V SENSE < 1.3V.1μF 2.2μF SENSE REFH.1μF RNGE DETECT ND CONTROL BUFFER INTERNL DC HIGH REFERENCE.8x DIFF MP ENC + ENC 15k 3k F1 Figure 1. Equivalent Encode Input Circuit for Differential Encode Mode.1μF REFL Figure 8. Reference Circuit INTERNL DC LOW REFERENCE F8 1.8V TO 3.3V V ENC + ENC LTC k CMOS LOGIC BUFFER F11 22 Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode fa

23 PPLICTIONS INFORMTION The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 1k equivalent resistance. The encode inputs can be taken above V DD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC should stay at least 2mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC + should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC is connected to ground and ENC + is driven with a square wave encode input. ENC + can be taken above V DD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC + threshold is.9v. For good jitter performance ENC + should have fast rise and fall times. Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25μs to lock onto the input clock. clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 3% to 7%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. DIGITL OUTPUTS The digital outputs of the LTC / LTC are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The data can be serialized with 16-, 14-, or 12-bit serialization (see the Timing Diagrams section for details). Note that with 12-bit serialization the two LSBs are not available this mode is included for compatibility with the 12-bit versions of these parts. The output data should be latched on the rising and falling edges of the data clockout (DCO). data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14- bit serialization mode, the frequency of the FR output is halved. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the DC will depend on the serialization mode as well as the speed grade of the DC (see Table 1). The minimum sample rate for all serialization modes is 5Msps..1μF.1μF T1 5Ω 5Ω 1Ω.1μF ENC + ENC + LTC PECL OR LVDS CLOCK.1μF ENC LTC μF ENC F13 T1 = M/COM ETC RESISTORS ND CPCITORS RE 42 PCKGE SIZE Figure 12. Sinusoidal Encode Drive F12 Figure 13. PECL or LVDS Encode Drive fa 23

24 PPLICTIONS INFORMTION Table 1. Maximum Sampling Frequency for ll Serialization Modes. Note That These Limits re for the LTC The Sampling Frequency for the Slower Speed Grades Cannot Exceed 4MHz (LTC ) or 25MHz (LTC217-14). MXIMUM SMPLING SERILIZTION MODE FREQUENCY, f S (MHz) DCO FREQUENCY FR FREQUENCY SERIL DT RTE 2-Lane 16-Bit Serialization 65 4 f S f S 8 f S 2-Lane 14-Bit Serialization f S.5 f S 7 f S 2-Lane 12-Bit Serialization 65 3 f S f S 6 f S 1-Lane 16-Bit Serialization f S f S 16 f S 1-Lane 14-Bit Serialization 65 7 f S f S 14 f S 1-Lane 12-Bit Serialization 65 6 f S f S 12 f S By default the outputs are standard LVDS levels: a 3.5m output current and a 1.25V output common mode voltage. n external 1Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OV DD and OGND which are isolated from the /D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5m. This current can be adjusted by control register 2 in serial programming mode. vailable current levels are 1.75m, 2.1m, 2.5m, 3m, 3.5m, 4m and 4.5m. In parallel programming mode the SCK pin can select either 3.5m or 1.75m. Optional LVDS Driver Internal Termination In most cases, using just an external 1Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 1Ω termination resistor can be enabled by serially programming mode control register 2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In parallel programming mode the SDO pin enables internal termination. Internal termination should only be used with 1.75m, 2.1m or 2.5m LVDS output current modes. 24 DT FORMT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2 s complement format can be selected by serially programming mode control register 1. Table 2. Output Codes vs Input Voltage + IN IN (2V RNGE) D13-D (OFFSET BINRY) >1.V V V V V 1.122V V V 1 1.V 1.V D13-D (2 s COMPLEMENT) Digital Output Randomizer Interference from the /D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the DC output spectrum. These unwanted tones can be randomized by randomizing the digital output before it is transmitted off chip, which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusive-or logic operation between the LSB and all other data output bits. To decode, the reverse operation is fa

25 PPLICTIONS INFORMTION applied an exclusive-or operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register 1. Digital Output Test Pattern To allow in-circuit testing of the digital interface to the /D, there is a test mode that forces the /D data outputs (D13-D) of all channels to known values. The digital output test patterns are enabled by serially programming mode control registers 3 and 4. When enabled, the test patterns override all other formatting modes: 2 s complement and randomizer. Output Disable The digital outputs may be disabled by serially programming mode control register 2. The current drive for all digital outputs, including DCO and FR, are disabled to save power or enable in-circuit testing. When disabled, the common mode of each output pair becomes high impedance, but the differential impedance may remain low. Sleep and Nap Modes The /D may be placed in sleep or nap modes to conserve power. In sleep mode the entire chip is powered down, resulting in 1mW power consumption. Sleep mode is enabled by mode control register 1 (serial programming mode), or by SDI (parallel programming mode). The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on V REF, REFH and REFL. For the suggested values in Figure 8, the /D will stabilize after 2ms. In nap mode any combination of /D channels can be powered down while the internal reference circuits and the PLL stay active, allowing a faster wake-up than from sleep mode. Recovering from nap mode requires at least 1 clock cycles. If the application demands very accurate DC settling, then an additional 5μs should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the /D leaves nap mode. Nap mode is enabled by the mode control register 1 in the serial programming mode. DEVICE PROGRMMING MODES The operating modes of the LTC / LTC can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PR/SER should be tied to V DD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to V DD or ground, or driven by 1.8V, 2.5V or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 3 shows the modes set by CS, SCK, SDI and SDO. Table 3. Parallel Programming Mode Control Bits (PR/SER = V DD ) PIN CS SCK SDI SDO DESCRIPTION 2-Lane/1-Lane Selection Bit = 2-Lane, 16-Bit Serialization Output Mode 1 = 1-Lane, 14-Bit Serialization Output Mode LVDS Current Selection Bit = 3.5m LVDS Current Mode 1 = 1.75m LVDS Current Mode Power Down Control Bit = Normal Operation 1 = Sleep Mode Internal 1Ω Termination Selection Bit = Internal Termination Disabled 1 = Internal Termination Enabled Serial Programming Mode To use the serial programming mode, PR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the /D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. ny SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again fa 25

26 PPLICTIONS INFORMTION The fi rst bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (6:). The fi nal eight bits are the register data (D7:D). If the R/W bit is low, the serial data (D7:D) will be written to the register set by the address bits (6:). If the R/W bit is high, data in the register set by the address bits (6: ) will be read back on the SDO pin (see the Timing Diagrams section). During a readback command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 2Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and readback is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic. To perform a software reset, bit D7 in the reset register is written with a logic 1. fter the reset is complete, bit D7 is automatically set back to zero. Table 4. Serial Programming Mode Register Map (PR/SER = GND) REGISTER : RESET REGISTER (DDRESS h) D7 D6 D5 D4 D3 D2 D1 D RESET X X X X X X X Bit 7 RESET Software Reset Bit = Not Used 1 = Software Reset. ll Mode Control Registers re Reset to h. The DC is momentarily placed in SLEEP mode. This Bit Is utomatically Set Back to Zero fter the Reset Is Complete Bits 6- Unused, Don t Care Bits. REGISTER 1: POWER-DOWN REGISTER (DDRESS 1h) D7 D6 D5 D4 D3 D2 D1 D DCSOFF RND TWOSCOMP SLEEP NP_4 NP_3 NP_2 NP_1 Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended. Bit 6 RND Data Output Randomizer Mode Control Bit = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 5 TWOSCOMP Two s Complement Mode Control Bit = Offset Binary Data Format 1 = Two s Complement Data Format Bits 4- SLEEP:NP_4:NP_1 Sleep/Nap Mode Control Bits = Normal Operation XXX1 = Channel 1 in Nap Mode XX1X = Channel 2 in Nap Mode X1XX = Channel 3 in Nap Mode 1XXX = Channel 4 in Nap Mode 1XXXX = Sleep Mode. ll Channels re Disabled Note: ny Combination of Channels Can Be Placed in Nap Mode fa

27 PPLICTIONS INFORMTION REGISTER 2: OUTPUT MODE REGISTER (DDRESS 2h) D7 D6 D5 D4 D3 D2 D1 D ILVDS2 ILVDS1 ILVDS TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE Bits 7-5 ILVDS2:ILVDS LVDS Output Current Bits = 3.5m LVDS Output Driver Current 1 = 4.m LVDS Output Driver Current 1 = 4.5m LVDS Output Driver Current 11 = Not Used 1 = 3.m LVDS Output Driver Current 11 = 2.5m LVDS Output Driver Current 11 = 2.1m LVDS Output Driver Current 111 = 1.75m LVDS Output Driver Current Bit 4 TERMON LVDS Internal Termination Bit = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS. Internal termination should only be used with 1.75m, 2.1m or 2.5m LVDS output current modes. Bit 3 OUTOFF Output Disable Bit = Digital Outputs are enabled. 1 = Digital Outputs are disabled. Bits 2- OUTMODE2:OUTMODE Digital Output Mode Control Bits = 2-Lanes, 16-Bit Serialization 1 = 2-Lanes, 14-Bit Serialization 1 = 2-Lanes, 12-Bit Serialization 11 = Not Used 1 = Not Used 11 = 1-Lane, 14-Bit Serialization 11 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization REGISTER 3: TEST PTTERN MSB REGISTER (DDRESS 3h) D7 D6 D5 D4 D3 D2 D1 D OUTTEST X TP13 TP12 TP11 TP1 TP9 TP8 Bit 7 OUTTEST Digital Output Test Pattern Control Bit = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Bit 6 Unused, Don t Care Bit. Bits 5- TP13:TP8 Test Pattern Data Bits (MSB) TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8. REGISTER 4: TEST PTTERN LSB REGISTER (DDRESS 4h) D7 D6 D5 D4 D3 D2 D1 D TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP Bits 7- TP7:TP Test Pattern Data Bits (LSB) TP7:TP Set the Test Pattern for Data Bit 7 Through Data Bit (LSB) fa 27

28 PPLICTIONS INFORMTION GROUNDING ND BYPSSING The requires a printed circuit board with a clean unbroken ground plane. multilayer board with an internal ground plane in the first layer beneath the DC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the DC. High quality ceramic bypass capacitors should be used at the V DD, OV DD, V CM, V REF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the.1μf capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the /D, and as close to the device as possible (1.5mm or less). Size 42 ceramic capacitors are recommended. The larger 2.2μF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals and digital outputs should not be routed next to each other. Ground fi ll and grounded vias should be used as barriers to isolate these signals from each other. HET TRNSFER Most of the heat generated by the LTC / LTC is transferred from the die through the bottomside exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias fa

29 TYPICL PPLICTIONS Silkscreen Top Top Side Inner Layer 2 GND Inner Layer fa 29

30 TYPICL PPLICTIONS Inner Layer 4 Inner Layer 5 Power Bottom Side Silkscreen Bottom fa

31 TYPICL PPLICTIONS LTC2172 Schematic SENSE R14 1k C4 1μF PR/SER SDO C17 1μF V DD C5 1μF IN1 IN1 IN2 IN2 IN3 IN3 IN4 IN4 C2.1μF C3.1μF C1 2.2μF C59.1μF C29.1μF C3.1μF V DD 1 + IN1 2 IN1 3 V CM IN2 5 IN2 6 REFH 7 REFH 8 REFL 9 REFL 1 + IN3 11 IN3 12 V CM IN4 14 IN4 V DD SENSE GND VREF PR/SER SDO GND OUT1 + LTC2172 V DD V DD ENC + ENC CS SCK SDI GND OUT4B OUT1 OUT4B + OUT1B + OUT4 OUT1B OUT2 + OUT2 OUT2B + OUT2B DCO + DCO OV DD OGND FR + FR OUT3 + OUT3 OUT3B + OUT3B OUT DIGITL OUTPUTS DIGITL OUTPUTS C16.1μF OV DD V DD C7.1μF C47.1μF C46.1μF SPI BUS ENCODE CLOCK ENCODE CLOCK T fa 31

32 PCKGE DESCRIPTION UKG Package 52-Lead Plastic QFN (7mm 8mm) (Reference LTC DWG # Rev Ø) 7.5 ± ± REF (2 SIDES).7 ± ± REF (2 SIDES) 7.1 ± ± ±.5 PCKGE OUTLINE.25 ±.5.5 BSC RECOMMENDED SOLDER PD PITCH ND DIMENSIONS PPLY SOLDER MSK TO RES THT RE NOT SOLDERED 7. ±.1 (2 SIDES).75 ±.5..5 R =.115 TYP 5.5 REF (2 SIDES) PIN 1 TOP MRK (SEE NOTE 6) PIN 1 NOTCH R =.3 TYP OR C CHMFER.4 ± ±.1 (2 SIDES) 6.5 REF (2 SIDES) 6.45 ± ±.1 TOP VIEW R =.1 TYP.25 ±.5.5 BSC (UKG52) QFN REV Ø ±.5.2 REF..5 BOTTOM VIEW EXPOSED PD SIDE VIEW 32 NOTE: 1. DRWING IS NOT JEDEC PCKGE OUTLINE 2. DRWING NOT TO SCLE 3. LL DIMENSIONS RE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PD ON BOTTOM OF PCKGE DO NOT INCLUDE MOLD FLSH. MOLD FLSH, IF PRESENT, SHLL NOT EXCEED.2mm ON NY SIDE, IF PRESENT 5. EXPOSED PD SHLL BE SOLDER PLTED 6. SHDED RE IS ONLY REFERENCE FOR PIN 1 LOCTION ON THE TOP ND BOTTOM OF PCKGE fa