0.8mm FH, Board to Board Vertical Plug to Vertical Receptacle, 5mm Stack Height

Transcription

1 ELECTRICAL PERFORMANCE REPORT EPR Issued: mm FH, Board to Board ertical Plug to ertical Receptacle, 5mm Stack Height ACD - AMP Circuits & Design A Division of AMP Circuits & Packaging Published by AMP Incorporated, Harrisburg, PA 17105

2 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR TABLE OF CONTENTS INTRODUCTION... iii What is an EPR?... iii Why use this EPR?... iii HOW TO USE AN EPR...iv The Simulation Page...v Simulation Graphs...v Input oltage...v Near & Far End Noise alues...vii MODEL OERIEW...viii The Single Line Model (SLM)...viii The Multi Line Model (MLM)...viii SINGLE LINE MODEL DATASHEET... ix SIMULATION DATA mm FH, BTB, ertical Plug to ertical Receptacle, 5mm Stack Height Electrical Interconnection Performance Information... 2 MODEL WIRING PATTERNS... 3 SIMULATION LOOK-UP TABLE... 4 Specifications subject to change. Consult AMP for latest design specifications. Copyright 1998 by AMP Incorporated All Rights Reserved. AMP is a registered trademark. ii Contents Printed on Recycled Paper

3 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR INTRODUCTION The first several pages of this Electrical Performance Report (EPR) are intended to give an overview of the AMP EPR. By understanding how to apply information from an AMP EPR, system designers will be able to select the best AMP product for their application. What is an EPR? EPRs (Electrical Performance Reports) are technical documents composed of electrical simulations of connector models. Each of these simulations varies in several system parameters. EPRs are used to assist system design engineers in the selection of potential connector solutions for their particular application. While there are several non-technical issues that enter into the connector selection decision, these electrical performance criteria are becoming very important. Why use this EPR? The EPR provides system designers with fundamental data relating to the electrical performance of a connector. This data, in turn, allows the system designer to decide if the connector under analysis is the proper interconnection device for his or her application. Criteria that impact the electrical performance of a connector include wiring patterns, edge rates, system impedance and logic families. The EPR permutes these criteria one step at a time, while holding all other parameters constant. This approach reveals the effects that each change may or may not cause. If used properly, an EPR can facilitate in choosing the proper connector for an application. Furthermore, the EPR can help in selecting wiring patterns, edge rates, system impedance, and logic families within an application. iii

4 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR HOW TO USE AN EPR Following a systematic method, pertinent information can be derived from the various EPR simulations. The parametric nature of simulations can best be explained by recognizing that various factors affect coupled noise: Wiring Pattern Logic Family (excitation) System Impedance (Z o ) Signal Risetime oltage Swing Connection Capacitance SIMULATION LOOK-UP TABLE Consolidates all simulations in the EPR to quickly find pertinent simulation(s). SIMULATION AND NOTES Defines Simulation Look-up Table fields. Can include graphics to relate. S Wiring patterns used for the simulations. Single-ended and differential patterns are simulated, where applicable. Select a representative model pattern that is similar to your application setup. Find the rows in the Simulation Look-Up Table that correspond to this wiring (model) pattern. In the table, you will see several parameters that vary given this model pattern. Note the simulation filename of interest, and go to that page to find graphs of electrical simulation data. iv

5 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR The Simulation Page The simulation page shows the graphical results of a simulation on a connector under defined system parameters. Referring to the figure below, it can be seen that the several parameters that effect the electro-dynamics of the connector are shown. Shows the connections to the connector model. SIMULATION GRAPHS Provide voltage versus time information. Graphs include Input oltage, Near and Far End Noise oltages. Defines connections to the connector model. SIMULATION Defines logic family, voltage swing, and rise time used in this simulation. Shows the simulation s system impedance, and the PAD (in the case of SMT) or plated through-hole capacitance. Simulation Graphs The value of the EPR is realized when voltage values are found on the simulation graphs. The plots of voltage versus time reveal both absolute values of voltage levels and where they occur in time. These values can help in determining the contribution or impact of the connector/connection on the system noise budget. In some occurrences, where multiple lines are monitored, a rough estimate of skew can be determined. The total noise tolerance should be determined, understanding that it is different for different logic families. Input oltage The Input oltage graph shows the incident and far end voltage of the connector including the connection effects (PAD or plated through hole capacitance). Overall symmetry (in the case of differential signals) can be seen. Refer to the following graph for more information: v

6 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR INPUT voltage graphs. In this case, a differential system, the INPUT voltages (IA3 & IA4) are plotted with the output voltages (OA3 & OA4) versus time Input oltage [ ] OA4 (Output voltage, pin A4) IA3 IA4 OA3 OA4 IA3 (Input voltage, pin A3) 1.8 OLTAGE(mv) OA3 (Output voltage, pin A3) 0.6 IA4 (Input voltage, pin A4) TIME(ns) The voltage response (refer to the voltage swing in following figure) of the connector should approach that of the logic family as defined in the simulation area of the EPR graph pages. The propagation delay of the connector can be determined as the difference in time that the incident and far end graphs cross the same voltage level. In the case below, the propagation delay would be: propagation delay: t = t 2 t Input oltage [ ] IA3 IA4 OA3 OA4 IA3 (Input voltage, pin A3) 1.8 OLTAGE(mv) OA3 (Output voltage, pin A3) oltage Swing Propagation delay of connector TIME(ns) t1 t2 vi

7 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR Near & Far End Noise alues Near and Far end noise values include the effects of the return path in their determination. Simulated values are absolute and can be included in their percent contribution to the total noise budget as determined by the system designer. In the following Near End Noise oltage figure, the effects of adjacent pairs that are out-of-phase can be seen (the +/- of two differentially-driven lines). Note that similar techniques are used with the Far End Noise voltage graphs Near End Noise oltage [ ] NDB3B4 NB3 NB4 NDB3B4 Differential voltage between pins B3 & B4 NB3 (Near End noise voltage, pin B3) OLTAGE(mv) NB4 (Near End noise voltage, pin B4) TIME(ns) To summarize, the EPR arms the system designer with simulation information from the simulation setups that closely match his or her design. This information can be effectively used to focus on follow-up simulations, and it is of great aid in selecting connector and wiring pattern candidates. vii

8 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR MODEL OERIEW The Single Line Model (SLM) The SLM is used to evaluate the effects of a single set of connector pins. A SLM is independent of connector wiring pattern and is an approximation of a well-referenced connector. A simulation with the SLM can show the following effects: PROPAGATION DELAY ATTENUATION REFLECTIONS DRIE POWER TIMING Single Line Model The SLM for the connector found in this EPR is listed on the next page. Note: A SLM was NOT used to generate simulation data in this EPR. (FOR CROSSTALK, A MULTI-LINE MODEL MUST BE USED.) The Multi Line Model (MLM) The MLM (Multi-Line Model) is used in all the simulations found in this EPR. The MLM accounts for the electrostatic and electromagnetic coupling (crosstalk) as well as the common impedance noise found in a connector. Its structure couples, in three dimensions, all pins to one another. This results in a complex model that uses series resistance, inductance, coupling capacitance and inductive coupling coefficients so arranged to allow connections at both the input and output. This modeling technique effectively shows coupled noise at the expense of CPU runtime. Simulations done using the MLM will show the following information: Multi Line Model - The Fundamental Structure ELECTROSTATIC COUPLING COMMON MODE NOISE ATTENUATION PROPAGATION DELAY ELECTROMAGNETIC COUPLING REFLECTIONS DRIE POWER TIMING CROSSTALK The fundamental MLM varies in the number of pins (rows & columns) and the number of sections. Note that faster rise times require multiple sections. To Learn more about AMP Simulation capabilities, please call (fax ). AMP, Harrisburg, PA In Canada, call viii

9 SINGLE LINE MODEL DATASHEET 0.8mm FH BTB, Surface Mount ALIDATED 1:1 S/G pattern Cp1 CONNECTOR R L C Cp2 Cp1 CONNECTOR Z Tpd Cp2 Connector Lumped Constant Model Connector Distributed Model RowA=RowB R (m Ω ) L (nh) C (pf) Z ( Ω ) Tpd (ps) 5mm mm mm mm mm mm mm mm mm mm mm mm Note: SINGLE LINE MODEL DATASHEET (1) The following RLC model is appropriate for edge speeds < 10*(<highest Tpd value>). To accommodate faster edge speeds, the lumped model must be divided into two or more RLC sections. Typically, a section s propagation delay should be 1/10 th of the edge speed. (2) The single line inductance and capacitance values are extracted from a specified pattern. The placement and number of ground returns effect the inductance and capacitance of the single line model. Please contact AMP for other wiring patterns. (3) The parameters for the Single Line Model are for the connector only without any mounting effects such as plated through holes or pads capacitance (Cp1 and Cp2). The impedance and propagation delay for the connector are calculated as follows: L Z = Connector C ( Ω ) and Tpd = L * Connector C ( sec ) For an interconnection path model, the mounting effects must be added because the additional capacitance of the pad to ground or plated through hole (Cp1 and Cp2) decrease impedance and increase propagation delay of the interconnection path. The impedance and propagation delay for an interconnection path are calculated as follows: Z Interconnect = L ( Ω) C + ( Cp1 + Cp2) and Tpd Interconne ct = L * ( C + Cp1 + Cp2)( sec) FOR ADDITIONAL ELECTRICAL MODELING/SIMULATION SUPPORT, CALL Datasheet Filename: ZPACK_2mmFB_5Row_-P_RA-R_TH Modeled by: [SC] Created on 01/30/98 2:06 PM Copyright 1998, AMP Incorporated ix Reviewed By: [CTK] SPICE File: [FB5] ACD Internal Form: Form_SLM-DS_1998_0304

10 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR (THIS PAGE INTENTIONALLY LEFT BLANK) x

11 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR SIMULATION DATA 0.8mm FH, Board to Board ertical Plug to ertical Receptacle, 5mm Stack Height 1

12 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR mm FH, BTB, ertical Plug to ertical Receptacle, 5mm Stack Height Electrical Interconnection Performance Information This document contains abstracts of the results of various computer simulations of electrical interconnection performance. The AMP 0.8mm FH connector evaluated in this report has been designed for parallel board stacking applications using subminiature connectors to meet today s electronic industry requirements for high-density packaging. The Model Pattern Orientation in this set of data represents a board to board interconnect. The simulations are run on the eight column model, Section a-a as shown, which is adequate for most wiring patterns. As shown in the Simulation Circuit Abstract figure to the right, the simulation model is a validated matrix circuit model (AMP Part Number ) which provides for the series resistance and inductance elements of each line, the electrostatic coupling between lines, and the electromagnetic coupling between lines. The model for this connector is multiple sections and is useful for digital signals with edge rates as fast as 250 ps. The model is configured so that any position in the matrix may be assigned as a driven line, a quiet line, or a reference line. Each line can be terminated (RT) as desired, pad capacitance (CP) can be assigned as desired, with driving functions (S) and source impedance (RS) assigned as desired. The near end and far end references are isolated to allow observation of common impedance effects of the connector. The simulation model outputs include both the electrostatic (E) and magnetic (M) crosstalk and the common mode noise contributions. This sum is reported as Near End Noise oltage and/or Far End Noise oltage. RS RC driven line(s) LC S CP CP RT B A CP signal s b Backward crosstalk Model Pattern Orientation (Section a-a) near end ref driven line quiet line(s) RC (-) (+) CONNECTOR MODEL RC reference line(s) (-) C M Simulation Circuit Abstract coupled region signal i Zc noise (+) (+) (-) Common Impedance Noise Forward crosstalk Electrostatic and Electromagnetic Crosstalk LC L M LC far end ref CP f RT RT 2

13 MODEL WIRING PATTERNS EPR - 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND B X a X A X Q X a A a X Q X a X a X 2:1 SIGNAL TO GROUND B X A Q X a a X a A a X a a X a Q X 2:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B a X Q Q X a A a X A I A X a 3:1 SIGNAL TO GROUND B X a Q a X a a a A a a X a A Q X a 4:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B A A I Q Q X a a A a a X a 5:1 SIGNAL TO GROUND B X a a Q a a X a A a Q a X A a a a 5:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B X a Q Q a X A X a A I A a X X Ground Line 3

14 EPR - 0.8mm FH, Board To Board, ertical Plug to EPR SIMULATION LOOK-UP TABLE (Indexed by S/G Ratio, then by Logic Family, then by Tr) Cp DH D GI GO Logic: S/G Ratio Tr f o Zo: Brd. Hgt. Reference Plane Table Legend: Pad or Plated Through Hole capacitance Differential signal (horizontal pairs) Differential signal (vertical pairs) Grounded Lines Towards Inside Rows Grounded Lines Towards Outside Rows Logic family simulated Ratio of signal lines to reference (ground) lines Rise time of source Source final voltage Source initial voltage Characteristic Impedance Simulation Model No. Page S/G Ratio Logic Tr (ns) o (olts) f (olts) Zo (Ohms) Pad (pf) Brd Hgt (mils) :1 ECL :1 ECL :1 ECL :1 GTL :1 ECL :1 ECL :1 ECL :1 GTL :1 DH ECL :1 DH ECL :1 DH ECL :1 DH LDS :1 DH LDS :1 ECL :1 ECL :1 ECL :1 GTL :1 DH ECL :1 DH ECL :1 DH ECL :1 DH LDS :1 DH LDS :1 ECL :1 ECL :1 ECL :1 GTL :1 DH ECL :1 DH ECL :1 DH ECL :1 DH LDS :1 DH LDS

15 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib4 vob B X a X A X Q X a A a X Q X a X a X oltage() Time(ps) NEAR END NOISE OLTAGE 2.00 vna3 vnb ECL SIMULATION Time(ps) -1.8 to vfa3 vfb6 Tr: 0.25 (20%-80%) Time(ps) Page 5 N - Near End Noise oltage

16 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib4 vob4 B X a X A X Q X a A a X Q X a X a X oltage() NEAR END NOISE OLTAGE 0.50 vna3 vnb6 ECL SIMULATION to Tr: 0.5 (20%-80%) 1 vfa3 vfb6 N - Near End Noise oltage Page 6

17 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib4 vob B X a X A X Q X a A a X Q X a X a X oltage() NEAR END NOISE OLTAGE 0.50 vna3 vnb6 ECL SIMULATION to vfa3 vfb6 Tr: 1.0 (20%-80%) Page 7 N - Near End Noise oltage

18 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib4 vob4 B X a X A X Q X a A a X Q X a X a X oltage() NEAR END NOISE OLTAGE vna3 vnb GTL SIMULATION to 1.2 Tr: 1.0 (10%-90%) 7.00 vfa3 vfb6 65 Ohm Lines N - Near End Noise oltage Page 8

19 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib2 vob B X A Q X a a X a A a X a a X a Q X oltage() Time(ps) NEAR END NOISE OLTAGE 10 9 vna7 vnb ECL SIMULATION Time(ps) -1.8 to vfa7 vfb3 Tr: 0.25 (20%-80% Time(ps) Page 9 N - Near End Noise oltage

20 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib2 vob2 B X A Q X a a X a A a X a a X a Q X oltage() NEAR END NOISE OLTAGE vna7 vnb ECL SIMULATION -1.8 to Tr: 0.5 (20%-80%) 5.00 vfa7 vfb N - Near End Noise oltage Page 10

21 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib2 vob B X A Q X a a X a A a X a a X a Q X oltage() NEAR END NOISE OLTAGE vna7 vnb ECL SIMULATION -1.8 to vfa7 vfb3 Tr: 1.0 (20%-80%) Page 11 N - Near End Noise oltage

22 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE vib2 vob2 B X A Q X a a X a A a X a a X a Q X oltage() NEAR END NOISE OLTAGE 3 vna7 vnb GTL SIMULATION to 1.2 Tr: 1.0 (10%-90%) vfa7 vfb3 65 Ohm Lines N - Near End Noise oltage Page 12

23 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE via5 via4 voa5 voa4 2:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B a X Q Q X a A a X A I A X a oltage() Time(ps) NEAR END NOISE OLTAGE vnb4b5 ECL SIMULATION Time(ps) -1.8 to vfb4b5 Tr: 0.25 (20%-80% Time(ps) Page 13 N - Near End Noise oltage

24 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B a X Q Q X a A a X A I A X a INPUT OLTAGE via5 via4 voa5 voa4 oltage() NEAR END NOISE OLTAGE vnb4b ECL SIMULATION -1.8 to -0.8 Tr: 0.5 (20%-80%) 2.00 vfb4b5 N - Near End Noise oltage Page 14

25 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE via5 via4 voa5 voa4 2:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B a X Q Q X a A a X A I A X a oltage() NEAR END NOISE OLTAGE vnb4b ECL SIMULATION -1.8 to vfb4b5 Tr: 1.0 (20%-80%) Page 15 N - Near End Noise oltage

26 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B a X Q Q X a A a X A I A X a INPUT OLTAGE via5 via4 voa5 voa oltage() NEAR END NOISE OLTAGE vnb4b LDS SIMULATION 1.0 to 1.4 Tr: 0.5 (10%-90%) vfb4b5 N - Near End Noise oltage Page 16

27 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE via5 via4 voa5 voa4 2:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B a X Q Q X a 1.40 A a X A I A X a 1.30 oltage() NEAR END NOISE OLTAGE 1.20 vnb4b LDS SIMULATION to vfb4b5 Tr: 1.0 (10%-90%) Page 17 N - Near End Noise oltage

28 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa5 B X a Q a X a a a A a a X a A Q X a oltage() Time(ps) NEAR END NOISE OLTAGE vna6 vnb ECL SIMULATION to Time(ps) Tr: 0.25 (20%-80%) 2 vfa6 vfb3 N - Near End Noise oltage Time(ps) Page 18

29 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa B X a Q a X a a a A a a X a A Q X a oltage() NEAR END NOISE OLTAGE vna6 vnb ECL SIMULATION -1.8 to vfa6 vfb3 Tr: 0.5 (20%-80%) Page 19 N - Near End Noise oltage

30 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa5 B X a Q a X a a a A a a X a A Q X a oltage() NEAR END NOISE OLTAGE vna6 vnb ECL SIMULATION to -0.8 Tr: 1.0 (20%-80%) 5.00 vfa6 vfb3 N - Near End Noise oltage Page 20

31 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa B X a Q a X a a a A a a X a A Q X a 0.90 oltage() NEAR END NOISE OLTAGE 8 7 vna6 vnb GTL SIMULATION 0.4 to vfa6 vfb3 Tr: 1.0 (10%-90% 65 Ohm Lines Page 21 N - Near End Noise oltage

32 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B A A I Q Q X a a A a a X a INPUT OLTAGE vib1 vib2 vob1 vob2 oltage() Time(ps) NEAR END NOISE OLTAGE vnb3b ECL SIMULATION to Time(ps) Tr: 0.25 (20%-80%) vfb3b4 N - Near End Noise oltage Time(ps) Page 22

33 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE vib1 vib2 vob1 vob2 4:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B A A I Q Q X a a A a a X a oltage() NEAR END NOISE OLTAGE vnb3b ECL SIMULATION to vfb3b4 Tr: 0.5 (20%-80%) Page 23 N - Near End Noise oltage

34 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B A A I Q Q X a a A a a X a INPUT OLTAGE vib1 vib2 vob1 vob2 oltage() ECL SIMULATION NEAR END NOISE OLTAGE vnb3b4-1.8 to Tr: 1.0 (20%-80%) 3.00 vfb3b4 N - Near End Noise oltage Page 24

35 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE vib1 vib2 vob1 vob2 4:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B A A I Q Q X a a 1.40 A a a X a 1.30 oltage() NEAR END NOISE OLTAGE vnb3b LDS SIMULATION to vfb3b4 Tr: 0.5 (10%-90%) Page 25 N - Near End Noise oltage

36 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B A A I Q Q X a a A a a X a INPUT OLTAGE vib1 vib2 vob1 vob oltage() NEAR END NOISE OLTAGE vnb3b LDS SIMULATION to Tr: 1.0 (10%-90%) 1.80 vfb3b4 N - Near End Noise oltage Page 26

37 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa B X a a Q a a X a A a Q a X A a a a oltage() Time(ps) NEAR END NOISE OLTAGE 35 vna2 vnb ECL SIMULATION Time(ps) -1.8 to vfa2 vfb4 Tr: 0.25 (20%-80% Time(ps) Page 27 N - Near End Noise oltage

38 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa5 B X a a Q a a X a A a Q a X A a a a oltage() NEAR END NOISE OLTAGE vna2 vnb ECL SIMULATION to -0.8 Tr: 0.5 (20%-80%) 1 vfa2 vfb4 N - Near End Noise oltage Page 28

39 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa B X a a Q a a X a A a Q a X A a a a oltage() NEAR END NOISE OLTAGE 10 9 vna2 vnb ECL SIMULATION to vfa2 vfb4 Tr: 1.0 (20%-80%) Page 29 N - Near End Noise oltage

40 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND INPUT OLTAGE via5 voa5 B X a a Q a a X a A a Q a X A a a a oltage() NEAR END NOISE OLTAGE vna2 vnb GTL SIMULATION to 1.2 Tr: 1.0 (10%-90%) 1 vfa2 vfb4 65 Ohm Lines N - Near End Noise oltage Page 30

41 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE via5 via4 voa5 voa4 5:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B X a Q Q a X A X a A I A a X oltage() Time(ps) NEAR END NOISE OLTAGE 1-1 vnb4b ECL SIMULATION Time(ps) -1.8 to vfb4b5 Tr: 0.25 (20%-80% Time(ps) Page 31 N - Near End Noise oltage

42 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B X a Q Q a X A X a A I A a X INPUT OLTAGE via5 via4 voa5 voa4 oltage() NEAR END NOISE OLTAGE vnb4b ECL SIMULATION to Tr: 0.5 (20%-80%) vfb4b5 N - Near End Noise oltage Page 32

43 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE via5 via4 voa5 voa4 5:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B X a Q Q a X A X a A I A a X oltage() NEAR END NOISE OLTAGE vnb4b ECL SIMULATION to vfb4b5 Tr: 1.0 (20%-80%) Page 33 N - Near End Noise oltage

44 EPR 0.8mm FH, Board To Board, ertical Plug to EPR :1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B X a Q Q a X A X a A I A a X INPUT OLTAGE via5 via4 voa5 voa oltage() NEAR END NOISE OLTAGE vnb4b5 LDS SIMULATION to Tr: 0.5 (10%-90%) 1 1 vfb4b5 N - Near End Noise oltage Page 34

45 EPR 0.8mm FH, Board To Board, ertical Plug to EPR INPUT OLTAGE via5 via4 voa5 voa4 5:1 SIGNAL TO GROUND DIFFERENTIAL (HORIZONTAL) PAIRS B X a Q Q a X 1.40 A X a A I A a X 1.30 oltage() NEAR END NOISE OLTAGE vnb4b LDS SIMULATION to vfb4b5 Tr: 1.0 (10%-90% Page 35 N - Near End Noise oltage

46 AMP-AMP-04/1998