EPE 2005 Dresden ESCAPEE. ESCAPEE Project. SiC Workshop. EPE 2005, September 12

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1 1 EPE 2005 Dresden ESCAPEE

2 2 The achievements of the EC funded project "Establish Silicon Carbide Applications for Power Electronics in Europe" (ESCAPEE) J. Millan 1, P. Godignon 1, D. Tournier 1, P.A. Mawby 2, S. Wilks 2, O.J. Guy 2, and L. Chen 2, R. Bassett 3, A. Hyde 3, N. Martin 4, M. Mermet-Guyennet 4, S. Pasugcio 4, S. P M. Syväjärvi 5, R.R. Ciechonski 5, R. Yakimova 5, L. Roux 6, F. Torregrosa 6, T. Bouchet 6, J-M. Bluet 7, G. Guillot 7, D. Hinchley 8, S. Jones 8, J. Rhodes 8, P. Taylor 9 and P. Waind 9 1 Centro Nacional de Microelectrónica, Campus Universidad Autónoma de Barcelona, 2 School of Engineering, University of Wales Swansea, 3 ALSTOM Research & Technology Centre, 4 ALSTOM Transport SA, 5 Department of Physics and Measurement Technology, Linköping University, Sweden, 6 Ion Beam Services, 7 Institut National des Sciences Appliquées de Lyon, Laboratoire de Physique de la Matiere CNRS, 8 Semelab Plc, 9 Dynex Semiconductor Ltd.

3 3 Overview Overview of recent results from the ESCAPEE project. Update to the information originally presented at EPE 2003 in Toulouse. Key targets Significant scientific progresses Final achievements and successes.

4 4 Key research targets (creation and introduction of SiC technology, from fundamental science through to real applications.) Produce improved quality of thick (>10μm) SiC epi-layer material suitable for high power devices. Develop device processing and fabrication technology (implantation, passivation, etching, metallization). Establish edge termination to enable high voltage applications. Develop high temperature device packaging suitable for SiC Use the created technology in a module introduction and enduser application in traction systems

5 5 Important scientific progresses Significant results from the ESCAPEE project include: Development of new sublimation epitaxial growth technique - produces epilayers at growth rates up to 20 times faster than standard CVD growth. Development of high temperature implantation equipment for SiC and the subsequent commercialisation. Development of surface cleaning processes and reduction of surface damage produced by high temperature annealing, for implant activation. Development of low resistance n-type and p-type ohmic contacts and high quality Schottky diodes. Design of edge termination and fabrication of thermally stable Schottky diodes with blocking voltages of up to 4.7kV and reverse leakage currents of less than 2e-7 A/cm 2 at 3.5kV. Increased device yield of 1.6mm 1.6mm diodes from 12% to 43% using a novel polishing technique.

6 6 Significant results from the ESCAPEE project continued Development of 1.2 kv MOSFETs. Record Field-effect mobility and drain current as a function of gate voltage for transistors with a PVT grown epilayer and a reference CVD grown epilayer. Design and production of specialized high temperature thermally stable packaging for high voltage SiC devices. Production of a demonstrator module using SiC diodes and Si IGBTs.

7 7 ESCAPEE Technological developments

8 8 ESCAPEE s results Material Fast epitaxy by PVT Sublimation of a solid source and transport of vapor to a substrate ideas based on the sublimation growth process to produce wafers but smaller distance between source and substrate Benefit of high growth rate from intrinsic sublimation to yield thick layers Develop growth conditions to achieve smooth surfaces and low doping

9 9 Achievements Low doping in the E15 range has been achieved Causes for the background doping are known and even lower doping is expected 0,04 0,03 PVT PVT, I D Higher field-effect mobility and drain current for transistors with a PVT grown epilayer than on reference CVD grown epilayer. 0,02 CVD CVD, I D A patent on the fast PVT epitaxy technology has been filed 0,01 0 t = 1550 Å, ox L = 20 μm, W= 100 μm Gate voltage [V] 50 0 Discussions with partners for commercialization are in progress

10 10 ESCAPEE s results Implantation High temperature implanter High temp chucks : - Several versions available and already sold (Univ. Madrid, INRS Canada, LETI.) V2 : Installed in Madrid Proto of V3 : Installed at INRS (Canada)

11 11 Novel process technological step Results using Graphite cap surface protection process are promising. Photoresist SiC 750 C Anneal (Ar) Carbon SiC Carbon cap produced by annealing photoresist under argon (750 C) RIE Anneal sample as before (1600 for 30 min) Remove Carbon Cap (RIE with O 2 ) SiC

12 12 Surface roughness reduced by up to a factor of 10 Improved forward I(V) characteristics Improved reverse leakage currents (a) (b) Not protected C-cap protected Carbon cap experiment

13 kv SCHOTTKY DIODES

14 kv Schottky Diodes Area dependence and wafer uniformity ESC12 - AsDep 1,00 1 0,1 Forward current (A) 0,75 0,50 0,25 Forward current (A) 0,01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 Forward voltage (V) 0.4 x 0.4 mm x 0.8 mm x 1.6 mm 2 ESC12 - AsDep 0,00 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 Forward voltage (V) Forward mode I(V) curves at 350ºC for various device area I(V) uniformity: Thickness and doping OK

15 kv SCHOTTKY DIODES - Yield Manufacturing yield versus Chip size and wafer micropipes density 100 Yield (%) = exp (Area * D) /cm 2 5/cm 2 2/cm 2 16/cm 2 30/cm 2 Unpolished Polished ESC12_UnPolished Escapee samples Escapee samples Escapee samples 40 0,5 1,0 1,5 2,0 2,5 Chip size (mm x mm)

16 16 Discrete Package New package uses DBC baseplate, eliminating separate copper baseplate and DBC substrate used in the conventional isolated TO-257. Offers reduction in weight, improved reliability and the potential to operate at elevated temperatures. Package successfully used to characterise 1000V ESCAPEE diodes at 225 C. Limited VR to 800V during hot test to avoid destroying devices. DBC TO-257 Package

17 17 Diode Characterisation Packaged devices show little area dependence and better stability and during device testing Diode Forward Characteristics Diode Reverse Characteristics

18 18 High-Temperature Operation 12 1E C 125 C 225 C 1E-03 IF (A) 6 IR (A) 1E E VF (V) 1E TJ ( C) Diode Forward Characteristics Diode Reverse Characteristics (at 800V)

19 kv SCHOTTKY DIODES switching T dependence Temperature dependence on the dynamic behavior of the 2.16 mm 2 SiC SBD No significant impact of temperature on switching characteristics

20 20 Compact modelling ESCAPEE s results 3.00E E E Ultra-fast Si PiN diode ESCAPEE SiC Schottky ESCAPEE model J (A/cm 2 ) 1.50E+02 SM d34 T=300K I (A) E E+01 SM d34 T=473 SM d34 T=573K JA d34fb25 JA d34fb E E E E E E E+00 JA d34fb Temperature (K) Time (s) DC Switching

21 21 1.2KV Hybrid Module Aerospace IGBT/diode halfbridge module. 150A 1200V Infineon Silicon IGBT. Four 1.6x1.6mm 1000V ESCAPEE SiC Schottky Diodes in parallel. AlSiC Baseplate, Al/AlN substrate, Cu lead-frame, PBT ring-frame and lid. PbSnAg solder and vacuum furnace die-attach. 5mil/12 mil Al wire-bonds. Si IGBT/SiC diode hybrid module with lid removed

22 22 Hybrid Module Characterisation Three IGBT/diode substrates exhibited IR<300uA at 1000V. One IGBT/diode substrate suffered fractured breakdown characteristic above 600V. VF < 3V at 50A, 25 C. Module successfully switched 25 C, 50A, 600V, 500A/us. IF (A) VF (V) Hybrid Module SiC Diode Forward Characteristics

23 23 Hybrid Module Switching ESCAPEE s results Si IGBT/SiC diode hybrid module inductive-load switching at 25 C, 50A, 600V, 500A/us.

24 kv SCHOTTKY DIODES

25 25 Diodes fabrication for module 4.5 kv ESCAPEE Schottky diodes fabricated at CNM for hybrid module Good current density uniformity vs diodes size R ON = 40mΩ.cm 2 close to theoretical expected value (31mΩ.cm 2 ). Reverse Current (A) 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1,6 x 1,6 mm 2 Id Ni used as Schottky contact - stability demonstrated up to 200 C 1E Reverse voltage (V) Schottky diode reverse characteristics Very low reverse leakage current density (JR<10 3.5kV) No breakdown differences between measurements made in the air and inside galden on polyimide passivated devices. 4.7kV Breakdown voltage measured = termination efficiency of at least 80% Current density (A/cm 2 ) x x x x1.6 R ON = 40 mω.cm 2 Φ B = 0,74ev 0 0,0 0,5 1,0 1,5 2,0 2,5 3,0 Voltage (V) Schottky diode forward characteristics versus size.

26 kv- 8A Module fabrication Power Modules have been constructed integrating Si IGBTs and SiC Schottky diodes in chopper configuration Arm electrical equivalent circuit, packaged diodes 3D-High voltage module CAD view. High voltage 4.5 kv SiC diodes have been successfully assembled with high-voltage Si IGBTs into modules and characterized by Dynex Semiconductor. High voltage packaging technology successfully applied to Si/SiC hybrid module fabrication

27 27 Module characterisation I F (A) (module) I F (20ºC) I F (125ºC) V F (V) J F (A) (per die) The measured on-resistance of the diode is lower and nearer to the theoretical value when measured on packaged devices. SiC Schottky diodes show excellent behaviour in forward mode up to 125ºC Schottky diode forward characteristics. Module I(V) left, Die J(V) right, at 20ºC and 125ºC

28 28 Module characterisation Forward 20 C Forward 125 C kv, 20 C Diode arm VF=3V VF=3V 8µA IGBT arm 3µA very low leakage current values have been measured at 3.1kV (curve tracer limit) in the reverse mode. diode arm leakage current 3.1kV) is in the same range than that of the Si-IGBT arm. Experimental SiC-Schottky diode and Si-IGBT modules forward characteristics and reverse leakage current at 3.1kV reverse bias. SiC Schottky diode leakage current level compatible with Si-IGBT

29 29 Module dynamic switching Dynamic switching has been performed at 125 C I C (R G =2.2Ω) I C (R G =7.5Ω) I C (R G =15Ω) I C (R G =30Ω) V CE (R G =2.2Ω) V CE (R G =7.5Ω) V CE (R G =15Ω) V CE (R G =30Ω) I C (A) V CE (V) µ 11µ 12µ 13µ 14µ time (s) time (s) Current waveform versus gate resistance at 125 C (VCE=1.8kV) VCE fall time versus gate resistance at 125 C 10A, 1800V switching at 125 C 0 10µ 11µ 12µ 13µ 14µ 4.5kV-8A SiC-Schottky diodes allow significant switching loss reduction and higher temperature working operation in comparison to Si-PIN diodes

30 30 Power MOSFET Fabrication

31 31 Gate oxide capacitances Interface density state in the SiC gap near the conduction band Interface Density States [cm -2 ev -1 ] N 2 O + TEOS O 2 + TEOS + Ar 100 nm TEOS TEOS + RTA N 2 O O 2 + TEOS +O 2 TEOS + N E C -E T [ev]

32 32 Lateral N-MOSFET test structure N-MOSFET on 4H-SiC: Thermal N 2 O /100nm TEOS / 950ºC O 2 Drain Current [ma] 1,5 Vg=10V 1,0 Vg=8V Vg=6V 0,5 Vg=4V Vg=2V 0, Drain-Source Bias [V] Effective Mobility μ eff [cm 2 /Vs] Channel mobility vs gate bias N 2 O + TEOS Thermal Oxide Gate Bias [V] Current higher than usual (x4 compared to LiU S230) Threshold voltage: in the range 1V / 0.5V ( short/long channel) Channel mobility: cm 2 /Vs (on epilayer layer annealed at 1600ºC) Stable up to 15V

33 33 ESCAPEE CURRENT STATUS: 1.2 kv Schottky diodes process stable with good yield 3.5 kv Schottky diodes process repetitive: yield depends on wafer quality Gate dielectric with channel mobility on implanted layer: 50 cm 2 /Vs 1.2 kv and 3.5 kv Power MOSFETs in processing

34 34 Si/SiC hybride modules