V6000 Datasheet. Version: 0.3 Release Date: June 27, Specifications are subject to change without notice Vango Technologies, Inc.

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1 Version: 0.3 Release Date: June 27, 2016 Specifications are subject to change without notice This document contains information that is proprietary to Unauthorized reproduction of this information in whole or in part is strictly prohibited.

2 Revision History Date Version Description Initial release Updated single power supply range from 9V~18V to 9V~15V Added serial number and updated format - 1 -

3 General Description The V6000 is a receiver (RX) integrated line driver, providing a high-current capability for driving the low-impedance line applications. The fully-differential design can achieve a superior performance in terms of MTPR (Multi-Tone Power Ratio) at 16 V ppd when 4 A peak current outputs. It also retains the bandwidth and the linearity while operates at single power supply of 9V~15V and temperature range of -40 C ~ +85 C. The V6000 contains a voltage-feedback TX amplifier and a programmable RX gain amplifier. Both of the amplifiers are designed to deal with the high-swing signal. The V6000 is protected against Over Temperature (OT) and Over Current (OC) by the built-in sensor. An internal-forced shutdown signal can be used to set the device back to the initial state. Besides, the OC condition can be avoided once the alarm alerts and is fed into the signal source. Via the SPI/I 2 C interface, the V6000 can be fully-controlled and optimized by firmware configuration. The V6000 is housed in a thermally-enhanced 40-pin QFN package. Features Supporting 4 A output driving capability Accurate thermal sensor for Over Temperature (OT) protection Supporting built-in Over Current (OC) protection Programmable TX and RX gain Single power supply range: 9V~15V Zero-crossing detectors Supporting SPI/I 2 C control interface Package: 40-pin QFN EPAD Operating temperature: -40 C ~ +85 C Applications: Power Line Communication (PLC) 28 V ppd output under 18 V power supply - 2 -

4 Table of Contents Revision History... 1 General Description... 2 Features... 2 Table of Contents... 2 Figure List... 3 Table List Electrical Characteristics Absolute Maximum Ratings Analog Specifications Digital Interface Specifications SPI Timing Specifications Pin Assignments Pin Descriptions System Block Diagram Outline Dimensions

5 Figure List Figure 1-1 Timing Diagram... 8 Figure 4-1 System Block Diagram Figure 5-1 Outline Dimensions

6 Table List Table 1-1 Absolut Maximum Ratings... 5 Table 1-2 Analog Specifications for General Characteristics... 5 Table 1-3 Analog Specifications for RX PGA... 6 Table 1-4 Analog Specifications for TX LD... 6 Table 1-5 Digital Interface Specifications... 6 Table 1-6 SPI Timing Specifications (SPI Mode 0)

7 1. Electrical Characteristics 1.1. Absolute Maximum Ratings While the operating circumstance exceeding Absolute Maximum Ratings, it may cause the permanent damage to the device. Table 1-1 Absolut Maximum Ratings Parameter Min. Typ. Max. Unit Conditions/Comments Analog Power Supply(AVDD_PA) V Analog Power Supply(AVDD33) V Digital Power Supply(DVDD_IO) V Storage Temperature C Operating Temperature C ESD 4000 V HBM V CDM Junction Temperature C Lead Temperature (Soldering, 10s) C 1.2. Analog Specifications All maximum and minimum specifications apply to the entire recommended operation range (T = -40 C ~ +85 C, AVDD33 = 3.3 V ± 10%), unless otherwise noted. All typical specifications are at TA = 25 C and AVDD33 = 3.3 V ± 10%, unless otherwise noted. Table 1-2 Analog Specifications for General Characteristics Parameter Min. Typ. Max. Unit Conditions/Comments Analog Power Supply(AVDD_PA) V High voltage supply Analog Power Supply(AVDD33) V 3.3V supply Temperature C - 5 -

8 Table 1-3 Analog Specifications for RX PGA Parameter Min. Typ. Max. Unit Conditions/Comments Gain db 6dB per step Noise 40 nv/hz 0.5 Distortion (Worst Harmonic) -80 dbc Fc = 1MHz, Vout=4V ppd -70 dbc Fc = 2MHz, Vout=4V ppd Input 30 V Differential peak-to-peak Output 4 V Differential peak-to-peak Table 1-4 Analog Specifications for TX LD Parameter Min. Typ. Max. Unit Conditions/Comments Gain 4 7 Distortion(Worst Harmonic) -55 dbc RL=10Ω, V out =16V ppd -50 dbc RL=4Ω, V out =16V ppd Input 4 V Differential peak-to-peak Output V Differential peak-to-peak Quiescent Current 100 ma 1.3. Digital Interface Specifications All maximum and minimum specifications apply to the entire recommended operation range (T = -40 C ~ +85 C, DVDD_IO = 3.3 V ± 10%), unless otherwise noted. Table 1-5 Digital Interface Specifications Parameter Min. Typ. Max. Unit Conditions/Comments Digital Power Supply(DVDD_IO) V Digital IO, Output Output High Voltage, V OH 2.4 V Output Low Voltage, V OL 0.4 V I SOURCE 4 ma - 6 -

9 Digital IO, Input Input High Voltage, V IH V Input Low Voltage, V INL V Internal Pull Resistance 22 k 1.4. SPI Timing Specifications All maximum and minimum specifications apply to the entire recommended operation range (T = -40 C ~ +85 C, DVDD_IO = 3.3 V ± 10%), unless otherwise noted. Table 1-6 SPI Timing Specifications (SPI Mode 0) Parameter Min. Max. Unit t CYC SPI_CLK cycle time 8Ts ns t PH SPI_CLK pulse high 3Ts ns t PL SPI_CLK pulse low 3Ts ns t DLY SPI_MISO delay time after SPI_CLK falling 2Ts 3Ts ns t VLD SPI_MISO valid time after SPI_CLK rising 6Ts 7Ts ns t SETUP SPI_MOSI setup time before SPI_CLK rising 2Ts ns t HOLD SPI_MOSI hold time after SPI_CLK rising 2Ts ns t CS_SETUP SPI_CS setup time before SPI_CLK rising 2Ts ns t CS_HOLD SPI_CS hold time after SPI_CLK falling 2Ts ns Note: Ts=1/Fs (Fs is the clock frequency of CLKIN input)

10 t SETUP t CYC t PH t PL SPI_CLK t HOLD SPI_MOSI t DLY t VLD SPI_MISO t CS_HOLD SPI_CS t CS_SETUP Figure 1-1 Timing Diagram - 8 -

11 2. Pin Assignments 40-pin QFN SPI_CLK SPI_MISO SPI_CS ZCOUT2 TXINP TXINN PWR_RDY RXINP RXINN AVDD33 REXT 31 DVDD_IO AVDD_PA CLKIN DVSS_IO ZCOUT1 16 ZCIN2 ZCIN1 V6000 TXOUTP TXOUTP RXOUTN AVDD_PA RXOUTP SPI_MOSI GPIO0 GPIO1 TEST AVDD_PA TXOUTN 35 TXOUTN AVDD_PA 40 NOTE: The exposed thermal pad is connected to the ground

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13 3. Pin Descriptions (Pin type: O =Output, I = Input, P =Power, G =Ground) No. Mnemonic Type Description 1 2 TXINP I Line driver differential positive input 3 TXINN I Line driver differential negative input 4 PWR_RDY O Power ready signal output 5 RXINP I Receiver amplifier differential positive input 6 RXINN I Receiver amplifier differential negative input 7 AVDD33 P Analog 3.3 V power 8 REXT I/O For external resistor connection AVDD_PA P Line driver high-voltage power 13 AVDD_PA P Line driver high-voltage power 14 TXOUTP O Line driver differential positive output 15 TXOUTP O Line driver differential positive output 16 TXOUTN O Line driver differential negative output 17 TXOUTN O Line driver differential negative output 18 AVDD_PA P Line driver high-voltage power 19 AVDD_PA P Line driver high-voltage power TEST For test only 23 GPIO1 O General purpose output 1 24 GPIO0 O General purpose output 0 25 ZCOUT2 O Zero-crossing detector2 output

14 No. Mnemonic Type Description 26 SPI_CS I SPI chip select input. Used as I2C_SCL in proprietary I 2 C mode 27 SPI_MOSI I SPI slave input 28 SPI_MISO I/O SPI slave output. Used as I2C_SDA in proprietary I 2 C mode 29 SPI_CLK I SPI clock input DVDD_IO P IO 3.3 V power 33 CLKIN I 24 MHz clock input 34 DVSS_IO G IO 3.3 V ground 35 ZCOUT1 O Zero-crossing detector1 output 36 ZCIN2 I Zero-crossing detector2 input 37 ZCIN1 I Zero-crossing detector1 input 38 RXOUTN O Receiver amplifier differential negative output 39 RXOUTP O Receiver amplifier differential positive output

15 4. System Block Diagram V6000 PowerOnReset OverTemp Sensor I2C/SPI Interface ZeroCrossing Detector OverCurrent Protection MISC PGA LD Figure 4-1 System Block Diagram RX TX

16 5. Outline Dimensions

17 Figure 5-1 Outline Dimensions