4-to-1 RF Multiplexer XT06

Transcription

1 4-to-1 RF Multiplexer XT06 DATA SHEET FEATURES FUNCTIONAL BLOCK DIAGRAM 3 db bandwidth of 230 MHz Total harmonic distortion of -55 db and better Externally adjustable gain Slew rate 470 V/us Channel switching time 10.6 ns Quiescent current 0.5 ma HIGHLIGHTS Internal output amplifier with current feedback Input stage cascade implemented in CMOS transistors providing low input bias current Option of using of two 4-to-1 multiplexers as one 8-to-1 APPLICATIONS Pixel switching for «Picture-in-Picture» LCD and Plasma displays Video Routers DELIVERABLES Datasheet GDSII database Customer support GENERAL DESCRIPTION The is a 4-to-1 Rf multiplexer designed with an internal current feedback output amplifier whose gain can be adjusted externally. The choice of the input is defined by the combination of address signals «SEL0»/«SEL1». There is a possibility of optional usage of two 4- to-1 devices as one 8-to-1 multiplexer by disabling all the inputs. The device architecture allows to switch off the current source power that sufficiently reduces the quiescent current. The multiplexer can be used as an amplifier with externally adjustable gain. GDSII database contains a ring of pads with built-in ESD protection up to 2000 V. 1/6

2 LIST OF CONTENTS Features 1 Functional block diagram 1 Highlights 1 Applications 1 Deliverables 1 General description 1 Device parameters 3 Pin configuration 4 Pin functional description 5 Esd-protection 5 Equivalent circuits 5 Timing diagram 6 2/6

3 DEVICE PARAMETERS VDDA = V; VSSA = -VDDA; RL=150 Ω; RF=500 Ω; G=+2; Cl=2 pf; T = С, unless otherwise noted. Parameter Conditions Min Typ Max DYNAMIC PERFORMANCE -3 db large signal bandwidth, MHz V0=1V; RL=100 Ω; Bandwidth for 0.1 db flatness, MHz V0=50mV; RF=500 Ω; RL=100Ω Rise and fall time (10% to 90%), ns VSTEP=2V Slew rate, V/us VSTEP=2V Settling time, ns 0.1%, VSTEP=2V SWITCHING CHARACTERISTICS 50% Address logic to 10% output settling switching time, ns 50% Address logic to 90% output settling switching time, ns % nen to 90% output settling channel ON time, ns % nen to 90% output settling channel OFF time, ns 50% ShutDown (SD) to 90% output settling channel ON time, ns 5,9 7, % ShutDown (SD) to 90% output settling channel OFF time, ns Channel switching transient (Glitch), mv All inputs grounded -24/96-59/133-95/177 Total Harmonic Distortion, THD, db Disable isolation, db DISTORTION/NOISE PERFORMANCE FC=10MHz; V0=2V p-p; RL=150Ω; FC=10MHz; V0=2V p-p; RL=1KΩ; F=5MHz; RL=100Ω; F=30MHz; RL=100Ω; Output offset, mv RL=1KΩ Open-Loop Voltage Gain, V/V DC/TRANSFER CHARACTERISTICS RF ; RL=1KΩ 9600 RF ; RL=150 Ω 2125 Gain Matching, % VIN=0.5V 0.01 Gain Accuracy, % VIN=0.5V /6

4 DEVICE PARAMETERS (continued) Parameter Conditions Min Typ Max INPUT CHARACTERISTICS Input Capacitance, pf 3.5 Input Voltage Range, V +/-3.3 Logic 1 Voltage, V SEL0; SEL1; nen; SD >2 Logic 0 Voltage, V SEL0; SEL1; nen; SD <0.8 Quiescent current, ma Output Voltage Swing, V RL=50Ω; VIN=3.3V; nen=0; SD=0 RL=50Ω; V IN=3.3V; nen=1; SD=0 RL=50Ω; VIN=3.3V; nen=0; 1 Limited by maximum VIA current densities in output OpAmp cascade. Value for average current is given, while peak value can be SD=1 OUTPUT CHARACTERISTICS 10 times bigger. Using the Device under consideration with RL< 50 Ω is not recommended RL=1KΩ 5.3/ / /-4.3 RL=150Ω 4.8/ / /-3.8 Output Current, ma RL=50Ω; V IN=3.3V 65.7 Short Circuit Current, ma 1 ~80 PIN CONFIGURATION Figure 1. Pin configuration 4/6

5 PIN FUNCTIONAL DESCRIPTION Pin name Description Comments 1 IN1 Input signal (1) 2 GND Digital Ground Typical value: 0 V 3 GND Digital Ground Typical value: 0 V 4 IN2 Input signal (2) 5 GND Digital Ground Typical value: 0 V 6 IN3 Input signal (3) 7 VSSA Analog Ground Typical value: -5 V 8 FB Feedback input 9 OUT Output 10 SD ShutDown Typical value: 0/5 V 11 nen Enable input Typical value: 0/5 V 12 SEL1 Address input (1) Typical value: 0/5 V 13 SEL0 Address input (0) Typical value: 0/5 V 14 VDDA Analog Power Typical value: 5 V 15 IN0 Input signal (0) 16 GND Digital Ground Typical value: 0 V ESD-PROTECTION ESD-protection of not less than 2 kv level for HBM discharge is provided for all analog inputs and outputs of the Multiplexer. EQUIVALENT CIRCUITS PAD I/O ESDstructure Figure 2. Analog input/output 5/6

6 TIMING DIAGRAM Figure 3. Timing diagram of the multiplexer, G=+2 The timing diagram represents dependence of the output on the logic signal combinations, IN0=IN2=0.5 V, IN1=IN3=-0.5 V. Table 1. Truth table SEL0 SEl1 nen SD VOUT IN IN IN IN , Iq= , Iq=0.5 6/6